blob: 94f682f8ecce44ff182effb37c280363b191b01f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
|
/*
* (C) Copyright 2008
*
* Georg Schardt <schardt@team-ctech.de>
*
* SPDX-License-Identifier: GPL-2.0+
*
* CAUTION: This file is based on the xparameters.h automatically
* generated by libgen. Version: Xilinx EDK 10.1.02 Build EDK_K_SP2.5
*/
#ifndef __XPARAMETER_H__
#define __XPARAMETER_H__
/* RS232 */
#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ 100000000
#define XPAR_UARTNS550_0_BASEADDR 0x83E00000
/* INT_C */
#define XPAR_XPS_INTC_0_DEVICE_ID 0
#define XPAR_XPS_INTC_0_BASEADDR 0x81800000
#define XPAR_INTC_MAX_NUM_INTR_INPUTS 2
/* CPU core clock */
#define XPAR_CORE_CLOCK_FREQ_HZ 300000000
#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
/* RAM */
#define XPAR_DDR2_SDRAM_MEM_BASEADDR 0x00000000
/* FLASH */
#define XPAR_FLASH_MEM0_BASEADDR 0xFFC00000
#endif
|
