blob: 533356c6a1c7a94a1c6ba759516719d378dcfb67 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
|
/*
* Copyright (C) 2015-2016 Wills Wang <wills.wang@live.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include <common.h>
#include <asm/io.h>
#include <asm/addrspace.h>
#include <asm/types.h>
#include <mach/ar71xx_regs.h>
#include <mach/ath79.h>
DECLARE_GLOBAL_DATA_PTR;
static u32 qca953x_get_xtal(void)
{
u32 val;
val = ath79_get_bootstrap();
if (val & QCA953X_BOOTSTRAP_REF_CLK_40)
return 40000000;
else
return 25000000;
}
int get_serial_clock(void)
{
return qca953x_get_xtal();
}
int get_clocks(void)
{
void __iomem *regs;
u32 val, ctrl, xtal, pll, div;
regs = map_physmem(AR71XX_PLL_BASE, AR71XX_PLL_SIZE,
MAP_NOCACHE);
xtal = qca953x_get_xtal();
ctrl = readl(regs + QCA953X_PLL_CLK_CTRL_REG);
val = readl(regs + QCA953X_PLL_CPU_CONFIG_REG);
/* VCOOUT = XTAL * DIV_INT */
div = (val >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT)
& QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
pll = xtal / div;
/* PLLOUT = VCOOUT * (1/2^OUTDIV) */
div = (val >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT)
& QCA953X_PLL_CPU_CONFIG_NINT_MASK;
pll *= div;
div = (val >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT)
& QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
if (!div)
div = 1;
pll >>= div;
/* CPU_CLK = PLLOUT / CPU_POST_DIV */
div = ((ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT)
& QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK) + 1;
gd->cpu_clk = pll / div;
val = readl(regs + QCA953X_PLL_DDR_CONFIG_REG);
/* VCOOUT = XTAL * DIV_INT */
div = (val >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT)
& QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
pll = xtal / div;
/* PLLOUT = VCOOUT * (1/2^OUTDIV) */
div = (val >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT)
& QCA953X_PLL_DDR_CONFIG_NINT_MASK;
pll *= div;
div = (val >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT)
& QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
if (!div)
div = 1;
pll >>= div;
/* DDR_CLK = PLLOUT / DDR_POST_DIV */
div = ((ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT)
& QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK) + 1;
gd->mem_clk = pll / div;
div = ((ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT)
& QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK) + 1;
if (ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL) {
/* AHB_CLK = DDR_CLK / AHB_POST_DIV */
gd->bus_clk = gd->mem_clk / (div + 1);
} else {
/* AHB_CLK = CPU_CLK / AHB_POST_DIV */
gd->bus_clk = gd->cpu_clk / (div + 1);
}
return 0;
}
ulong get_bus_freq(ulong dummy)
{
if (!gd->bus_clk)
get_clocks();
return gd->bus_clk;
}
ulong get_ddr_freq(ulong dummy)
{
if (!gd->mem_clk)
get_clocks();
return gd->mem_clk;
}
|
