summaryrefslogtreecommitdiffstats
path: root/arch/mips/cpu/xburst/timer.c
blob: 79f34f00c9f14bd6329658c7f6b37587da2c2c2b (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
/*
 *  Copyright (c) 2006
 *  Ingenic Semiconductor, <jlwei@ingenic.cn>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <config.h>
#include <common.h>
#include <asm/io.h>

#include <asm/jz4740.h>

#define TIMER_CHAN  0
#define TIMER_FDATA 0xffff  /* Timer full data value */

DECLARE_GLOBAL_DATA_PTR;

static struct jz4740_tcu *tcu = (struct jz4740_tcu *)JZ4740_TCU_BASE;

void reset_timer_masked(void)
{
	/* reset time */
	gd->arch.lastinc = readl(&tcu->tcnt0);
	gd->arch.tbl = 0;
}

ulong get_timer_masked(void)
{
	ulong now = readl(&tcu->tcnt0);

	if (gd->arch.lastinc <= now)
		gd->arch.tbl += now - gd->arch.lastinc; /* normal mode */
	else {
		/* we have an overflow ... */
		gd->arch.tbl += TIMER_FDATA + now - gd->arch.lastinc;
	}

	gd->arch.lastinc = now;

	return gd->arch.tbl;
}

void udelay_masked(unsigned long usec)
{
	ulong tmo;
	ulong endtime;
	signed long diff;

	/* normalize */
	if (usec >= 1000) {
		tmo = usec / 1000;
		tmo *= CONFIG_SYS_HZ;
		tmo /= 1000;
	} else {
		if (usec > 1) {
			tmo = usec * CONFIG_SYS_HZ;
			tmo /= 1000*1000;
		} else
			tmo = 1;
	}

	endtime = get_timer_masked() + tmo;

	do {
		ulong now = get_timer_masked();
		diff = endtime - now;
	} while (diff >= 0);
}

int timer_init(void)
{
	writel(TCU_TCSR_PRESCALE256 | TCU_TCSR_EXT_EN, &tcu->tcsr0);

	writel(0, &tcu->tcnt0);
	writel(0, &tcu->tdhr0);
	writel(TIMER_FDATA, &tcu->tdfr0);

	/* mask irqs */
	writel((1 << TIMER_CHAN) | (1 << (TIMER_CHAN + 16)), &tcu->tmsr);
	writel(1 << TIMER_CHAN, &tcu->tscr); /* enable timer clock */
	writeb(1 << TIMER_CHAN, &tcu->tesr); /* start counting up */

	gd->arch.lastinc = 0;
	gd->arch.tbl = 0;

	return 0;
}

void reset_timer(void)
{
	reset_timer_masked();
}

ulong get_timer(ulong base)
{
	return get_timer_masked() - base;
}

void set_timer(ulong t)
{
	gd->arch.tbl = t;
}

void __udelay(unsigned long usec)
{
	ulong tmo, tmp;

	/* normalize */
	if (usec >= 1000) {
		tmo = usec / 1000;
		tmo *= CONFIG_SYS_HZ;
		tmo /= 1000;
	} else {
		if (usec >= 1) {
			tmo = usec * CONFIG_SYS_HZ;
			tmo /= 1000 * 1000;
		} else
			tmo = 1;
	}

	/* check for rollover during this delay */
	tmp = get_timer(0);
	if ((tmp + tmo) < tmp)
		reset_timer_masked();  /* timer would roll over */
	else
		tmo += tmp;

	while (get_timer_masked() < tmo)
		;
}

/*
 * This function is derived from PowerPC code (read timebase as long long).
 * On MIPS it just returns the timer value.
 */
unsigned long long get_ticks(void)
{
	return get_timer(0);
}

/*
 * This function is derived from PowerPC code (timebase clock frequency).
 * On MIPS it returns the number of timer ticks per second.
 */
ulong get_tbclk(void)
{
	return CONFIG_SYS_HZ;
}
OpenPOWER on IntegriCloud