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* sandbox: Convert serial driver to use driver modelSimon Glass2014-09-101-0/+3
| | | | | | | Adjust the sandbox serial driver to use the new driver model uclass. The driver works much as before, but within the new framework. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Add a uclass for serial devicesSimon Glass2014-09-102-0/+93
| | | | | | | | Serial devices support simple byte input/output and a few operations to find out whether data is available. Add a basic uclass for serial devices to be used by drivers that are converted to driver model. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Adjust lists_bind_fdt() to return the bound deviceSimon Glass2014-09-101-1/+5
| | | | | | | Allow the caller to find out the device that was bound in response to this call. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: fdt: Add a function to look up a chosen nodeSimon Glass2014-09-101-0/+12
| | | | | | | Within /chosen we may have a node which points to another node, similar to how /aliases works. Add a helper function to do this lookup. Signed-off-by: Simon Glass <sjg@chromium.org>
* tegra: Convert tegra GPIO driver to use driver modelSimon Glass2014-09-101-0/+1
| | | | | | | | | | | | | | | | This is an implementation of GPIOs for Tegra that uses driver model. It has been tested on trimslice and also using the new iotrace feature. The implementation uses a top-level GPIO device (which has no actual GPIOS). Under this all the banks are created as separate GPIO devices. The GPIOs are named as per the Tegra datasheet/header files: A0..A7, B0..B7, ..., Z0..Z7, AA0..AA7, etc. Since driver model is not yet available before relocation, or in SPL, a special function is provided for seaboard's SPL code. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: tegra: Set up a pre-reloc malloc()Simon Glass2014-09-101-0/+1
| | | | | | Allocate 1KB so that driver model can operate before relocation. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Make driver model available before board_init()Simon Glass2014-09-101-1/+23
| | | | | | | | | | | For some boards board_init() will change GPIOs, so we need to have driver model available before then. Adjust the board init to arrange this, but enable it for driver model only, just to be safe. This does create additional #ifdef logic, but it is safer than trying to make a pervasive change which may cause some boards to break. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://www.denx.de/git/u-boot-microblazeTom Rini2014-09-101-1/+0
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| * microblaze: remove #ident directive to fix build errorMasahiro Yamada2014-09-101-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The microblaze-generic board fails to build at least with the kernel.org crosstool: https://www.kernel.org/pub/tools/crosstool/files/bin/x86_64/4.9.0/ x86_64-gcc-4.9.0-nolibc_microblaze-linux.tar.xz $ make CROSS_COMPILE=microblaze-linux- microblaze-generic_defconfig all [ snip ] CC disk/part.o CC disk/part_dos.o LD disk/built-in.o CC drivers/block/systemace.o {standard input}: Assembler messages: {standard input}:2495: Error: operation combines symbols in different segments {standard input}:2496: Error: operation combines symbols in different segments {standard input}:2499: Error: operation combines symbols in different segments {standard input}:2500: Error: operation combines symbols in different segments {standard input}:2505: Error: operation combines symbols in different segments {standard input}:2506: Error: operation combines symbols in different segments {standard input}:2515: Error: operation combines symbols in different segments {standard input}:2516: Error: operation combines symbols in different segments {standard input}:2519: Error: operation combines symbols in different segments {standard input}:2520: Error: operation combines symbols in different segments {standard input}:2529: Error: operation combines symbols in different segments {standard input}:2530: Error: operation combines symbols in different segments {standard input}:2533: Error: operation combines symbols in different segments {standard input}:2534: Error: operation combines symbols in different segments {standard input}:2539: Error: operation combines symbols in different segments {standard input}:2540: Error: operation combines symbols in different segments {standard input}:2549: Error: operation combines symbols in different segments {standard input}:2550: Error: operation combines symbols in different segments make[3]: *** [drivers/block/systemace.o] Error 1 make[2]: *** [drivers/block] Error 2 make[1]: *** [drivers] Error 2 make: *** [__build_one_by_one] Error 2 It looks like the cause of this error message is the "#ident" directive. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ls102xa: dcu: Add platform support for DCU on LS1021ATWR boardWang Huan2014-09-081-0/+18
| | | | | | | | | | | | | | This patch adds the TWR_LCD_RGB card/HDMI options and the common configuration for DCU on LS1021ATWR board. Signed-off-by: Alison Wang <alison.wang@freescale.com>
* | video: dcu: Add DCU driver supportWang Huan2014-09-081-0/+16
| | | | | | | | | | | | | | | | | | This patch is to add DCU driver support. DCU also named 2D-ACE(Two Dimensional Animation and Compositing Engine) is a system master that fetches graphics stored in internal or external memory and displays them on a TFT LCD panel. Signed-off-by: Alison Wang <alison.wang@freescale.com>
* | net: tsec: Remove tx snooping support from LS1Claudiu Manoil2014-09-081-0/+4
| | | | | | | | | | | | | | | | | | | | Remove the DMCTRL Tx snooping bits (TDSEN and TBDSEN) as a workaround for LS1. It has been observed that currently the Tx stops functioning after a fair amount of Tx traffic with these settings on. These bits are sticky and once set they cannot be reset from Linux, for instance. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
* | arm: ls102xa: Add basic support for LS1021ATWR boardWang Huan2014-09-081-0/+273
| | | | | | | | | | | | | | | | | | | | | | | | | | LS102xA is an ARMv7 implementation. This patch is to add basic support for LS1021ATWR board. One DDR controller DUART1 is used as the console For the detail board information, please refer to README. Signed-off-by: Chen Lu <chen.lu@freescale.com> Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Signed-off-by: Alison Wang <alison.wang@freescale.com>
* | arm: ls102xa: Add basic support for LS1021AQDS boardWang Huan2014-09-081-0/+389
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS102xA is an ARMv7 implementation. This patch is to add basic support for LS1021AQDS board. One DDR controller DUART1 is used as the console For the detail board information, please refer to README. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Jason Jin <jason.jin@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Yuan Yao <yao.yuan@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
* | driver/ddr/fsl: Add support of overriding chip select write levelingYork Sun2014-09-081-0/+2
| | | | | | | | | | | | | | | | | | | | JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This is not an issue unless some DQ pins are not connected. If a platform uses regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on those floating pins for the second rank. The workaround is to use a known good chip select for this purpose. Signed-off-by: York Sun <yorksun@freescale.com>
* | esdhc: Add CONFIG_SYS_FSL_ESDHC_LE and CONFIG_SYS_FSL_ESDHC_BE macrosWang Huan2014-09-081-1/+13
| | | | | | | | | | | | | | | | | | For LS102xA, the processor is in little-endian mode, while esdhc IP is in big-endian mode. CONFIG_SYS_FSL_ESDHC_LE and CONFIG_SYS_FSL_ESDHC_BE are added. So accessing ESDHC registers can be determined by ESDHC IP's endian mode. Signed-off-by: Alison Wang <alison.wang@freescale.com>
* | ls102xa: etsec: Add etsec support for LS102xAAlison Wang2014-09-081-1/+6
| | | | | | | | | | | | | | | | | | This patch is to add etsec support for LS102xA. First, Little-endian descriptor mode should be enabled. So RxBDs and TxBDs are interpreted with little-endian byte ordering. Second, TSEC_SIZE and TSEC_MDIO_OFFSET are different from PowerPC, redefine them for LS1021xA. Signed-off-by: Alison Wang <alison.wang@freescale.com>
* | net: Merge asm/fsl_enet.h into fsl_mdio.hClaudiu Manoil2014-09-083-3/+14
|/ | | | | | | | | | | | | | | fsl_enet.h defines the mapping of the usual MII management registers, which are included in the MDIO register block common to Freescale ethernet controllers. So it shouldn't depend on the CPU architecture but it should be actually part of the arch independent fsl_mdio.h. To remove the arch dependency, merge the content of asm/fsl_enet.h into fsl_mdio.h. Some files (like fm_eth.h) were simply including fsl_enet.h only for phy.h. These were updated to include phy.h instead. Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com>
* Merge git://git.denx.de/u-boot-usbTom Rini2014-09-021-1/+4
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| * dfu: Provide means to find difference between dfu-util -e and -RLukasz Majewski2014-09-021-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit provides distinction between DFU device detach and reset. The -R behavior is preserved with proper handling of the dfu-util's -e switch, which detach the DFU device. By running dfu-util -e; one can force device to finish the execution of dfu command on target and execute some other scripted commands. Moreover, some naming has been changed - the dfu_reset() method now is known as dfu_detach(). New name better reflects the purpose of the code. It was also necessary to increase the number of usb_gadget_handle_interrupts() calls since we also must wait for detection of the USB reset event. Example usage: 1. -e (detach) switch dfu-util -a0 -D file1.bin;dfu-util -a3 -D uImage;dfu-util -e access to u-boot prompt. 2. -R (reset) switch dfu-util -a0 -D file1.bin;dfu-util -R -a3 -D uImage target board reset Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com>
* | dm: gpio: Enhance gpio command to show only active GPIOsSimon Glass2014-08-311-2/+13
|/ | | | | | | | | | | | The GPIO list is very long in many cases and most of them are not used. By default, show only the GPIOs that are in use, and provide a flag to show all of them. This makes the 'gpio status' command much more pleasant. In order to do this, driver model now exposes a method for obtaining the 'function' of a GPIO, which describes whether it is an input or output, for example. Implementation of this method is optional. Signed-off-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-niosTom Rini2014-08-314-294/+9
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| * nios2: rebase nios2-generic board to 3c120 reference designThomas Chou2014-08-301-2/+9
| | | | | | | | | | | | | | | | | | Though nios2-generic board meant to be a template, it is helpful to be able to test on a real hardware. As the nios2 linux is developed and tested on a 3c120 FPGA based Golden Hardware Reference Design, it makes sense to rebase nios2-generic on this FPGA design. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
| * serial: move nios2-yanu.h into opencores_yanu driverThomas Chou2014-08-301-99/+0
| | | | | | | | | | | | | | | | | | The nios2-yanu.h contains hardware registers and bits of opencores yanu. As there is no other user of this header , it should be moved into the driver. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> CC: Renato Andreola <renato.andreola@imagos.it>
| * nios2: move nios2.h to arch asm directoryThomas Chou2014-08-301-40/+0
| | | | | | | | | | | | | | The nios2.h is nios2 cpu specific, and should go arch asm directory. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
| * nios2: divide nios2-io.h into each specific drivers and remove itThomas Chou2014-08-301-153/+0
| | | | | | | | | | | | | | | | | | | | The nios2-io.h defines hardware registers and bits of several FPGA IP cores. It could be divided in to the specific drivers, including altera timer, altera sysid, altera uart and altera jtag uart. The altera pio and altera spi drivers use their own hardware definitions. The removal of nios2-io.h will help modularity and maintenance. Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
* | nomadik: kconfig: move board select menu and common settingsMasahiro Yamada2014-08-301-2/+0
| | | | | | | | | | | | | | | | | | | | Becuase the board select menu in arch/arm/Kconfig is too big, move the Nomadik board select menu to nomadik/Kconfig. Move also common settings (CONFIG_SYS_CPU="arm926ejs" and CONFIG_SYS_SOC="nomadik"). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | orion5x: kconfig: move board select menu and common settingsMasahiro Yamada2014-08-301-1/+0
| | | | | | | | | | | | | | | | | | | | | | Becuase the board select menu in arch/arm/Kconfig is too big, move the Orion5x board select menu to orion5x/Kconfig. Move also common settings (CONFIG_SYS_CPU="arm926ejs" and CONFIG_SYS_SOC="orion5x"). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Albert ARIBAUD <albert.u.boot@aribaud.net>
* | omap5: kconfig: move board select menu and common settingsMasahiro Yamada2014-08-301-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | Becuase the board select menu in arch/arm/Kconfig is too big, move the OMAP5 board select menu to omap5/Kconfig. Move also common settings (CONFIG_SYS_CPU="armv7" and CONFIG_SYS_SOC="omap5"). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Tom Rini <trini@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com>
* | omap4: kconfig: move board select menu and common settingsMasahiro Yamada2014-08-301-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | Becuase the board select menu in arch/arm/Kconfig is too big, move the OMAP4 board select menu to omap4/Kconfig. Move also common settings (CONFIG_SYS_CPU="armv7" and CONFIG_SYS_SOC="omap4"). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Tom Rini <trini@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com>
* | omap3: kconfig: move board select menu and common settingsMasahiro Yamada2014-08-3016-16/+0
| | | | | | | | | | | | | | | | | | | | | | Becuase the board select menu in arch/arm/Kconfig is too big, move the OMAP3 board select menu to omap3/Kconfig. Move also common settings (CONFIG_SYS_CPU="armv7" and CONFIG_SYS_SOC="omap3 Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Tom Rini <trini@ti.com>
* | kirkwood: kconfig: refactor Kconfig and defconfigMasahiro Yamada2014-08-3017-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | Becuase the board select menu in arch/arm/Kconfig is too big, move the KirkWood board select menu to kirkwood/Kconfig. Consolidate also common settings (CONFIG_SYS_CPU="arm926ejs" and CONFIG_SYS_SOC="kirkwood"). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Prafulla Wadasdkar <prafulla@marvell.com> Cc: Luka Perkov <luka@openwrt.org>
* | rmobile: kconfig: move board select menu and common settingsMasahiro Yamada2014-08-305-5/+0
| | | | | | | | | | | | | | | | | | | | | | Becuase the board select menu in arch/arm/Kconfig is too big, move the Rmobile board select menu to rmobile/Kconfig. Consolidate also common settings (CONFIG_SYS_CPU="armv7" and CONFIG_SYS_SOC="rmobile"). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
* | tegra: kconfig: move board select menu and common settingsMasahiro Yamada2014-08-301-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Becuase the board select menu in arch/arm/Kconfig is too big, move the Tegra board select menu to tegra/Kconfig. Insert the Tegra SoC select menu between the arch select and the board select. Architecture select |-- Tegra Platform (Tegra) |- Tegra SoC select (Tegra20 / 30 / 114 / 124) |- Board select Consolidate also common settings (CONFIG_SYS_CPU="armv7" and CONFIG_SYS_SOC="tegra*") and always "select" CONFIG_SPL as follows: config TEGRA bool select SPL Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Stephen Warren <swarren@nvidia.com> Cc: Tom Warren <twarren@nvidia.com>
* | zynq: kconfig: move board select menu and common settingsMasahiro Yamada2014-08-301-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | Becuase the board select menu in arch/arm/Kconfig is too big, move the Zynq board select menu to zynq/Kconfig. Consolidate also common settings (CONFIG_SYS_CPU="armv7" and CONFIG_SYS_SOC="zynq"). Refactor board/xilinx/zynq/MAINTAINERS too. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Tested-by: Michal Simek <michal.simek@xilinx.com>
* | arm/km: disable subpage write for km_kirkwood_pci and kmsuv31 targetHolger Brunck2014-08-301-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | Newer FLASH types used on these boards don't allow writing of subpages. So disable subpage write in the NAND driver. Additionally we need to tell the UBI layer in the kernel that he also should only write 2048 bytes. This is done with an additional command line parameter for the kernel commandline. Signed-off-by: Holger Brunck <holger.brunck@keymile.com> cc: Valentin Longchamp <valentin.longchamp@keymile.com> cc: Prafulla Wadaskar <prafulla@marvell.com>
* | vexpress_aemv8a.h: Enable CONFIG_CMD_BOOTI and CONFIG_CMD_UNZIPTom Rini2014-08-301-0/+2
| | | | | | | | | | | | Add support for booting Images and for unzipping Image.gz files. Signed-off-by: Tom Rini <trini@ti.com>
* | vexpress_aemv8a.h: Clean up the configTom Rini2014-08-301-8/+5
| | | | | | | | | | | | | | | | | | - Drop DEBUG - Drop defines we can use the default of. - Provide a larger malloc pool. - Correct default locations for kernel / initrd / device tree Signed-off-by: Tom Rini <trini@ti.com>
* | cmd_bootm.c: Add 'booti' for ARM64 Linux kernel ImagesTom Rini2014-08-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The default format for arm64 Linux kernels is the "Image" format, described in Documentation/arm64/booting.txt. This, along with an optional gzip compression on top is all that is generated by default. The Image format has a magic number within the header for verification, a text_offset where the Image must be run from, an image_size that includes the BSS and reserved fields. This does not support automatic detection of a gzip compressed image. Signed-off-by: Tom Rini <trini@ti.com>
* | arm: add Cygnus and NSP boardsScott Branden2014-08-301-0/+115
| | | | | | | | | | | | | | | | | | The bcm_ep board configuration is used by a number of boards including Cygnus and NSP. Add builds for the bcm958300k and the bcm958622hr boards. Signed-off-by: Scott Branden <sbranden@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com>
* | arm: bcm281xx: net: Add Ethernet DriverJiandong Zheng2014-08-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | The Broadcom StarFighter2 Ethernet driver is used in multiple Broadcom SoC(s) and: - supports multiple MAC blocks, - provides support for the Broadcom GMAC. This driver requires MII and PHYLIB. Signed-off-by: Jiandong Zheng <jdzheng@broadcom.com> Signed-off-by: Steve Rae <srae@broadcom.com>
* | ARM: enable ARMv7 virt support for the Arndale boardAndre Przywara2014-08-301-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | To enable hypervisors utilizing the ARMv7 virtualization extension on the Arndale board, add the simple SMP pen address writer function and add the required configuration variables to switch all cores to HYP mode before launching the OS. This allows booting KVM and Xen directly from u-boot. Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Andre Przywara <andre.przywara@linaro.org> Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | socfpga: initialize designware ethernetPavel Machek2014-08-301-0/+32
| | | | | | | | | | | | | | | | Enable initialization fo designware ethernet controller. With this patch, ethernet works in my configuration, provided I set ethernet address in the environment. Signed-off-by: Pavel Machek <pavel@denx.de>
* | socfpga: Fix SOCFPGA build error for Altera dev kitChin Liang See2014-08-291-1/+1
|/ | | | | | | | | | | | | To fix the build error when build for Altera dev kit, not virtual target. At same time, set the build for Altera dev kit as default instead virtual target. With that, U-Boot is booting well and SPL still lack of few drivers. Signed-off-by: Chin Liang See <clsee@altera.com> Cc: Pavel Machek <pavel@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@ti.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
* Merge branch 'master' of git://git.denx.de/u-boot-tiTom Rini2014-08-298-178/+211
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| * pcm051: use ti_am335x_common.h configMatwey V. Kornilov2014-08-251-136/+4
| | | | | | | | | | | | Include general configs/ti_am335x_common.h and drop redundant #defines. Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
| * ARM: DRA: Enable VTT regulatorLokesh Vutla2014-08-251-0/+1
| | | | | | | | | | | | | | | | | | | | DRA7 evm REV G and later boards uses a vtt regulator for DDR3 termination and this is controlled by gpio7_11. Configuring gpio7_11. The pad A22(offset 0x3b4) is used by gpio7_11 on REV G and later boards, and left unused on previous boards, so it is safe enough to enable gpio on all DRA7 boards. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * cm-t54: convert to generic boardDmitry Lifshitz2014-08-251-0/+3
| | | | | | | | | | | | | | Use generic board setup functions by defining CONFIG_SYS_GENERIC_BOARD. Signed-off-by: Dmitry Lifshitz <lifshitz@compulab.co.il>
| * SOM: tam3517: convert to generic boardJeroen Hofstee2014-08-251-0/+1
| | | | | | | | | | | | Cc: Raphael Assenat <raph@8d.com> Cc: Stefano Babic <sbabic@denx.de> Signed-off-by: Jeroen Hofstee <jeroen@myspectrum.nl>
| * board/ti/dra7xx: add support for parallel NORpekon gupta2014-08-251-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for parallel NOR device (S29GL512S10) present on J6-EVM. The Flash device is connected to GPMC controller on chip-select[0] and accessed as memory-mapped device. It has data-witdh=x16, capacity-64MBytes(512Mbits) and is CFI compatible. As multiple devices are share GPMC pins on this board, so following board settings are required to detect NOR device: SW5.1 (NAND_BOOTn) = OFF (logic-1) SW5.2 (NOR_BOOTn) = ON (logic-0) /* Active-low */ SW5.3 (eMMC_BOOTn) = OFF (logic-1) SW5.4 (QSPI_BOOTn) = OFF (logic-1) And also set appropriate SYSBOOT configurations: SW3.1 (SYSBOOT[ 8])= ON (logic-1) /* selects SYS_CLK1 speed */ SW3.2 (SYSBOOT[ 9])= OFF (logic-0) /* selects SYS_CLK1 speed */ SW3.3 (SYSBOOT[10])= ON (logic-1) /* wait-pin monitoring = enabled */ SW3.4 (SYSBOOT[11])= OFF (logic-0) /* device type: Non Muxed */ SW3.5 (SYSBOOT[12])= OFF (logic-0) /* device type: Non Muxed */ SW3.6 (SYSBOOT[13])= ON (logic-1) /* device bus-width: 1(x16) */ SW3.7 (SYSBOOT[14])= OFF (logic-0) /* reserved */ SW3.8 (SYSBOOT[15])= ON (logic-1) /* reserved */ Also, following changes are required to enable NOR Flash support in dra7xx_evm board profile:
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