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* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-241-17/+1
| | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de> [trini: Fixup common/cmd_io.c] Signed-off-by: Tom Rini <trini@ti.com>
* powerpc/boot: Change the macro of Boot from SRIO and PCIE master moduleLiu Gang2013-06-201-1/+1
| | | | | | | | | | | | | | | | | Currently, the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" can enable the master module of Boot from SRIO and PCIE on a platform. But this is not a silicon feature, it's just a specific booting mode based on the SRIO and PCIE interfaces. So it's inappropriate to put the macro into the file arch/powerpc/include/asm/config_mpc85xx.h. Change the macro "CONFIG_SYS_FSL_SRIO_PCIE_BOOT_MASTER" to "CONFIG_SRIO_PCIE_BOOT_MASTER", remove them from arch/powerpc/include/asm/config_mpc85xx.h file, and add those macros in configuration header file of each board which can support the master module of Boot from SRIO and PCIE. Signed-off-by: Liu Gang <Gang.Liu@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/corenet_ds: move SATA config to board configurationZang Roy-R619112012-11-271-0/+1
| | | | | | | | | | | | | | | | | | | | board configuration file is included before asm/config_mpc85xx.h. however, CONFIG_FSL_SATA_V2 is defined in asm/config_mpc85xx.h. it will never take effective in the board configuration file for this kind of code : #ifdef CONFIG_FSL_SATA_V2 ... #endif To solve this problem, move CONFIG_FSL_SATA_V2 to board configuration header file. This patch reverts Timur's commit:3e0529f742e893653848494ffb9f7cd0d91304bf Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx: move SRIO configuration out of corenet_ds.hTimur Tabi2012-10-221-0/+4
| | | | | | | | The P5040 does not have SRIO, so don't put the SRIO definitions in corenet_ds.h. They belong in the board-specific header files. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/fsl-corenet: remove dead variant symbolsScott Wood2012-08-231-1/+1
| | | | | | | | | | | These are not supported as individual build targets, but instead are supported by another target. The dead p4040 defines in particular had bitrotted significantly. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
* powerpc/85xx: CONFIG_FSL_SATA_V2 should be defined in config_mpc85xx.hTimur Tabi2011-11-291-1/+0
| | | | | | | | | | | Macro CONFIG_FSL_SATA_V2 is defined if the SOC has a V2 Freescale SATA controller, so it should be defined in config_mpc85xx.h instead of the various board header files. So now CONFIG_FSL_SATA_V2 is always defined on the P1013, P1022, P2041, P3041, P5010, and P5020. It was already defined for the P1010 and P1014. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add support for RMan LIODN initializationKumar Gala2011-10-181-0/+1
| | | | | | | | | This patch is intended to initialize RMan LIODN related registers on P2041, P304S and P5020 SocS. It also adds the "rman@0" child node to qman-portal nodes, adds "fsl,liodn" property to RMan inbound block nodes. Signed-off-by: Minghuan Lian <Minghuan.Lian@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Add support for setting up RAID engine liodns on P5020Kumar Gala2011-10-031-0/+1
| | | | | | | | | Add support for Job Queue/Ring LIODN for the RAID Engine on P5020. Each Job Queue/Ring combo needs one id assigned for a total of 4 (2 JQs/2 Rings per JQ). This just handles RAID Engine in non-DPAA mode. Signed-off-by: Santosh Shukla <santosh.shukla@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* powerpc/85xx: Refactor some defines out of corenet_ds.hKumar Gala2011-10-031-0/+5
| | | | | | | | | | | Move some SoC/board specific defines out of corenet_ds.h and into the corresponding P3041DS/P4080DS/P5020.h. We moved CONFIG_MMC, CONFIG_PCIE3, & CONFIG_FSL_NGPIXIS because the P3060 SoC/reference board does not have these devices and it will share the same board code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Minor coding style cleanup.Wolfgang Denk2011-05-191-1/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* powerpc: Add P3041DS/P5020DS board support (uses corenet_ds code)Kumar Gala2011-04-271-0/+37
The P3041DS & P5020DS boards are almost identical (except for the processor in them). Additionally they are based on the P4080DS board design so we use the some board code for all 3 boards. Some ngPIXIS (FPGA) registers where reserved on P4080DS and now have meaning on P3041DS/P5020DS. We utilize some of these for SERDES clock configuration. Additionally, the P3041DS/P5020DS support NAND. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Shaohui Xie <b21989@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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