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* dm: drop CONFIG_DM_DEVICE_REMOVE from uncmd listMasahiro Yamada2015-08-183-6/+6
| | | | | | | | | | | | | | | We do not want to compile the DM remove code for SPL. Currently, we undef it in include/config_uncmd_spl.h (for C files) and in scripts/Makefile.uncmd_spl (for Makefiles). This is really ugly. This commit demonstrates how we can deprecate those two files. Use $(SPL_) for the entry in the Makfile and CONFIG_IS_ENABLED() in C files. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* led: unify obj-$(CONFIG_LED) and obj-$(CONFIG_SPL_LED) entriesMasahiro Yamada2015-08-181-2/+1
| | | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* led: rename CONFIG_SPL_LED_SUPPORT to CONFIG_SPL_LEDMasahiro Yamada2015-08-182-2/+2
| | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ram: unify obj-$(CONFIG_RAM) and obj-$(CONFIG_SPL_RAM) entriesMasahiro Yamada2015-08-181-2/+1
| | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ram: rename CONFIG_SPL_RAM_SUPPORT to CONFIG_SPL_RAMMasahiro Yamada2015-08-182-2/+2
| | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* clk: unify obj-$(CONFIG_CLK) and obj-$(CONFIG_SPL_CLK) entriesMasahiro Yamada2015-08-181-2/+1
| | | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* clk: rename CONFIG_SPL_CLK_SUPPORT to CONFIG_SPL_CLKMasahiro Yamada2015-08-182-2/+2
| | | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: unify obj-$(CONFIG_DM) and obj-$(CONFIG_SPL_DM) entriesMasahiro Yamada2015-08-181-2/+2
| | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* spl: move SPL driver entries to driver/MakefileMasahiro Yamada2015-08-181-0/+37
| | | | | | | | | | | | | Just preparing for upcoming cleaning. The board-specific linker script board/vpac270/u-boot-spl.lds has been touched to avoid build error. It does not change the size of spl/u-boot-spl.bin for this board, so it should be OK. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Stefano Babic <sbabic@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* i2c: lpc32xx: correct sanity check for requested bus speedVladimir Zapolskiy2015-08-181-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | LPC32xx has 3 I2C bus controllers, 2 of them are used as generic ones and their parent clock is HCLK and CLK_HI/CLK_LO registers are 10 bit wide. This means that if HCLK is 104MHz, then minimal configurable I2C clock speed is about 51KHz. Only USB OTG I2C bus controller CLK registers are 8 bit wide, thus in assumption that peripheral clock is 13MHz it allows to set the minimal bus speed about 25.5KHz. Check for negative half clock value is removed since it is always false. The change fixes the following problem for I2C busses 0 and 1: => i2c dev 0 Setting bus to 0 => i2c speed 100000 Setting bus speed to 100000 Hz Failure changing bus speed (-22) Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
* usb: lpc32xx: add host USB driverSylvain Lemieux2015-08-182-0/+232
| | | | | | | | | | | | | Incorporate USB driver from legacy LPCLinux NXP BSP. The files taken from the legacy patch are: - lpc32xx USB driver - lpc3250 header file USB registers definition. The legacy driver was updated and clean-up as part of the integration with the latest u-boot. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Vladimir Zapolskiy <vz@mleia.com>
* i2c: lpc32xx: add support for OTG I2CSylvain Lemieux2015-08-181-3/+17
| | | | | | | | Updated the LPC32xx I2C driver to support the OTG I2C that is part of the USB module. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> Acked-by: Marek Vasut <marex@denx.de>
* nand: lpc32xx: add ECC layout for small page NANDSylvain Lemieux2015-08-181-1/+17
| | | | | | | | | | Incorporate ECC layout for small page NAND from legacy LPCLinux NXP BSP. The code taken from the legacy patch is: - lpc32xx SLC NAND driver (ECC layout for small page) This layout is matching the lpc32xx NAND SLC Linux Kernel driver. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
* nand: lpc32xx: add hardware ECC supportSylvain Lemieux2015-08-181-4/+409
| | | | | | | | | | | | Incorporate NAND SLC hardware ECC support from legacy LPCLinux NXP BSP. The code taken from the legacy patch is: - lpc32xx SLC NAND driver (hardware ECC support) - lpc3250 header file missing SLC NAND registers definition The legacy driver was updated and clean-up as part of the integration with the existing NAND SLC driver. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> Tested-by: Vladimir Zapolskiy <vz@mleia.com>
* dma: lpc32xx: add DMA driverSylvain Lemieux2015-08-182-0/+148
| | | | | | | | | | | | | Incorporate DMA driver from legacy LPCLinux NXP BSP. The files taken from the legacy patch are: - lpc32xx DMA driver - lpc3250 header file DMA registers definition. The legacy driver was updated and clean-up as part of the integration with the latest u-boot. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Vladimir Zapolskiy <vz@mleia.com>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2015-08-185-2/+130
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| * spi: ti_qspi: Use DMA to read from qspi flashVignesh R2015-08-171-0/+25
| | | | | | | | | | | | | | | | ti_qspi uses memory map mode for faster read. Enabling DMA will increase read speed by 3x @48MHz on DRA74 EVM. Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * dma: ti-edma3: Add helper function to support edma3 transferVignesh R2015-08-171-0/+78
| | | | | | | | | | Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * sf: ops: Add spi_flash_copy_mmap functionTom Rini2015-08-171-1/+7
| | | | | | | | | | | | | | | | | | | | When doing a memory mapped copy we may have DMA available and thus need to have this copy abstracted so that the driver can do it, rather than a simple memcpy. Signed-off-by: Tom Rini <trini@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * ti: qspi: set flash quad bit based on quad support flagvishalm@ti.com2015-08-171-1/+1
| | | | | | | | | | | | | | | | Update op_mode_rx flag based on CONFIG_QSPI_QUAD_SUPPORT flag, instead of platform. Signed-off-by: Vishal Mahaveer <vishalm@ti.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
| * sf: Make 4K sector support configurableMarek Vasut2015-08-172-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make the support for 4K subpage I/O on a SPI NOR flash configurable. A board which requires the SPI NOR to be accessed in larger 32KiB or 64KiB pages can disable the 4K subpage support, but by default, the support for 4K subpage I/O is enabled. The functionality of this option is the same as CONFIG_MTD_SPI_NOR_USE_4K_SECTORS in Linux. This is extremely useful in case one uses UBI on a SPI NOR flash. UBI needs at least 15k EBs and can not work on a flash which uses 4k ones, so disabling the support for 4k subpages lets UBI work on such flash. Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-samsungTom Rini2015-08-181-1/+1
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| * | ARM: exynos: move SoC sources to mach-exynosThomas Abraham2015-08-171-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | Move arch/arm/cpu/armv7/exynos/* to arch/arm/mach-exynos/* to allow reuse of existing code for ARMv8 based Exynos platforms. Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Przemyslaw Marczak <p.marczak@samsung.com> Acked-by: Przemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | pci: mvebu: Add PCIe driverAnton Schubert2015-08-172-0/+424
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a PCI driver for the controllers found on Marvell MVEBU SoCs. Besides the driver, this patch also removes the statically defined PCI MBUS windows. As they are not needed anymore, since this PCIe driver now creates the windows dynamically. Tested on Armada XP db-mv784mp-gp eval board using an Intel E1000 PCIe card in all 3 PCIe slots. And on the Armada 38x db-88f6820-gp eval board using this Intel E1000 PCIe card in the PCIe 0 slot. This port was done in cooperation with Anton Schubert. Signed-off-by: Anton Schubert <anton.schubert@gmx.de> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Dirk Eibach <eibach@gdsys.de>
* | arm: mvebu: Add complete SDRAM ECC scrubbingStefan Roese2015-08-172-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | This patch introduces the SDRAM scrubbing for ECC enabled board to fill/initialize the ECC bytes. This is done via the XOR engine to speed up the process. The scrubbing is a 2-stage process: 1) SPL scrubs the area 0 - 0x100.0000 (16MiB) for the main U-Boot 2) U-Boot scrubs the remaining SDRAM area(s) Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | arm: mvebu: add multiple usb-hostcontroller support for AXPAnton Schubert2015-08-171-8/+11
| | | | | | | | | | | | | | | | | | | | | | This patch adds support for multiple hostcontrollers to the ehci-marvell driver and enables all 3 usb-hcs on the db-mv784mp-gp board. It depends on the initial Armada XP usb support patch from Stefan. Signed-off-by: Anton Schubert <anton.schubert@gmx.de> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | arm: mvebu: Enable USB EHCI support on Armada XPStefan Roese2015-08-171-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables the USB EHCI support for the Marvell Armada XP (AXP) SoCs. In compatism to the Armada 38x (A38x), the AXP needs to configure the USB PLL and the USB PHY's specifically in U-Boot. The A38x has done this already in the bin_hdr (SPL U-Boot). Without this, accessing the controller registers in U-Boot or Linux will hang the CPU. Additionally, the AXP uses a different USB EHCI base address. This patch also takes care of this by runtime SoC detection in the Marvell EHCI driver. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Anton Schubert <anton.schubert@gmx.de> Cc: Marek Vasut <marex@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | arm: mvebu: Enable NAND controller on MVEBU SoC'sStefan Roese2015-08-171-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables the NAND controller on the Armada XP/38x and provides a new function that returns the NAND controller input clock. This function will be used by the MVEBU NAND driver. As part of this patch, the multiple BIT macro definitions are moved to a common place in soc.h. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Peter Morrow <peter@senient.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | arm: mvebu: sdram: Enable ECC support on Armada XPStefan Roese2015-08-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is tested on the DB-MV784MP-GP eval board. To really enable ECC support on this board the I2C EEPROM needs to get changed. As it saves the enabling of ECC support internally. For this the following commands can be used to enable ECC support on this board: Its recommended for first save (print) the value(s) in this EEPROM address: => i2c md 4e 0.1 2 0000: 05 00 .. To enable ECC support you need to set bit 1 in the 2nd byte: Marvell>> i2c mw 4e 1.1 02 Marvell>> i2c md 4e 0.1 2 0000: 05 02 .. To disable ECC support again, please use this command: Marvell>> i2c mw 4e 1.1 00 Marvell>> i2c md 4e 0.1 2 0000: 05 00 .. On other AXP boards, simply plugging an ECC DIMM should be enough to enable ECC support. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | i2c: lpc32xx: fix write timeoutSylvain Lemieux2015-08-171-0/+2
| | | | | | | | | | | | Fix a condition that generate watchdog timeout inside "lpc32xx_i2c_write" when parameters alen = 0 and len = 0. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
* | i2c: lpc32xx: fix read timeoutSylvain Lemieux2015-08-171-5/+5
| | | | | | | | | | | | Fix a condition that generate watchdog timeout inside "lpc32xx_i2c_read" when parameters alen != 0 and len = 0. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
* | i2c: lpc32xx: use api to get hclk instead of fix valueSylvain Lemieux2015-08-171-1/+1
|/ | | | | | The HCLK is not constant and can take different value; use the api function to get the value of the HCLK for the I2C clock high and low computation. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
* Merge git://git.denx.de/u-boot-x86Tom Rini2015-08-142-1/+141
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| * video: vesa: Correct a typo in the Kconfig VESA mode stringBin Meng2015-08-141-1/+1
| | | | | | | | | | | | | | There is one typo in the VESA mode 105h string. Correct it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * Revert "dm: pci: Allow scan bridge child devices before relocation"Simon Glass2015-08-141-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | This reverts commit df189d9ba3f8fd1bc67e3c0c3c4ace16cd065ee1. Unfortunately this commit breaks chromebook_link because it adds lots of PCI devices before relocation and there is not enough pre-reloc malloc() memory. Rathar then increase this memory, revert for now until we figure this out. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * dm: pci: Add a way to iterate through all PCI devicesSimon Glass2015-08-141-0/+60
| | | | | | | | | | | | | | | | | | These functions allow iteration through all PCI devices including bridges. The children of each PCI bus are returned in turn. This can be useful for configuring, checking or enumerating all the devices. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * dm: pci: Provide friendly config access functionsSimon Glass2015-08-141-0/+76
| | | | | | | | | | | | | | | | | | At present there are no PCI functions which allow access to PCI configuration using a struct udevice. This is a sad situation for driver model as it makes use of PCI harder. Add these functions. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-pmicTom Rini2015-08-143-1/+104
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| * | Add missing part of: "power: pmic: pfuze100 support driver model"Peng Fan2015-08-143-1/+104
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This part of mentioned commit, was missed by my mistake during the rebase. Signed-off-by: Przemyslaw Marczak <p.marczak@samsung.com> Original commit message: power: pmic: pfuze100 support driver model 1. Support driver model for pfuze100. 2. Introduce a new Kconfig entry DM_PMIC_PFUZE100 for pfuze100 3. This driver intends to support PF100, PF200 and PF3000, so add the device id into the udevice_id array. 4. Rename PMIC_NUM_OF_REGS macro to PFUZE100_NUM_OF_REGS. Change-Id: I4fc88414f3c0285f9648e47ec7aed60addeccc4d Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Przemyslaw Marczak <p.marczak@samsung.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* | sunxi: Display: Add support for eDP panels connected via an anx9804 bridgeHans de Goede2015-08-141-1/+18
| | | | | | | | | | | | | | | | | | | | | | Add support for 4 1.62G lane eDP panels connected via an anx9804 bridge, such as found on the Colombus devkit. While at it also fix the wrong indentation of the SSD2828 Kconfig help text in board/sunxi/Kconfig. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | video: Add support for the ANX9804 parallel lcd to dp bridge chipHans de Goede2015-08-144-0/+222
| | | | | | | | | | | | | | | | | | Add support for the ANX9804 bridge chip, which can take pixel data coming from a parallel LCD interface and translate it on the fly into a DP interface for driving eDP TFT displays. It uses I2C for configuration. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Anatolij Gustschin <agust@denx.de>
* | sun6i: display: Add support for using the mipi pll as lcd clock sourceHans de Goede2015-08-141-7/+34
| | | | | | | | | | | | | | | | | | Add support for using the mipi pll as lcd clock source, this is necessary for getting higher dotclocks with lcd panels. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Anatolij Gustschin <agust@denx.de>
* | sunxi: gpio: Add support for the gpio banks which are part of the R-io clusterHans de Goede2015-08-141-4/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | sun6i and later have a couple of io-blocks which are shared between the main CPU core and the "R" cpu which is small embedded cpu which can be active while the main system is suspended. These gpio banks sit at a different mmio address then the normal banks, and have a separate devicetree node and compatible, this adds support for these banks to the sunxi-gpio code when built with device-model support. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: display: Fix composite video out on sun5iHans de Goede2015-08-141-0/+11
| | | | | | | | | | | | | | | | The tv-encoder on sun5i is slightly different compared to the one on sun4i/sun7i. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: display: Add overscan correctionHans de Goede2015-08-141-12/+39
| | | | | | | | | | | | | | | | | | | | | | Add support for making the visual area of the framebuffer smaller and drawing a black border around it. This is intended for use with overscanning monitors (esp. with composite video out), to avoid part of the picture being invisible. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Anatolij Gustschin <agust@denx.de>
* | cfbconsole: Add support for stride != widthHans de Goede2015-08-141-35/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | cfbconsole currently assumes that the width and stride of the framebuffer are the same, in most places where stride matters it uses a VIDEO_LINE_LEN helper macro. This commit changes the few places not using VIDEO_LINE_LEN to also use VIDEO_LINE_LEN, and protects the default VIDEO_LINE_LEN with a #ifndef guard, allowing the boards config.h to override and, and thus support cases where stride != width. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Anatolij Gustschin <agust@denx.de>
* | cfbconsole: Remove width argument from the logo functionsHans de Goede2015-08-141-13/+8
|/ | | | | | | | The passed in width is always VIDEO_COLS. This is a preparation patch for adding stride != width support to the cfbconsole code. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Anatolij Gustschin <agust@denx.de>
* tegra: nand: disable subpage writesMarcel Ziswiler2015-08-131-0/+3
| | | | | | | | Disable subpage writes as we do not provide ecc->hwctl. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* mtd/nand/tegra: alignment workaroundMarcel Ziswiler2015-08-131-51/+36
| | | | | | | | | | | | | | | | | | | | | | | | | Integrate cache alignment bounce buffer to workaround issues as follows: Loading file '/boot/zImage' to addr 0x01000000 with size 4499152 (0x0044a6d0)... ERROR: v7_dcache_inval_range - start address is not aligned - 0x1f7f0108 ERROR: v7_dcache_inval_range - stop address is not aligned - 0x1f7f1108 Done Kernel image @ 0x1000000 [ 0x000000 - 0x44a6d0 ] Starting kernel ... undefined instruction pc : [<005ff03c>] lr : [<0000800c>] sp : 0144b6e8 ip : 01000188 fp : 0144a6c8 r10: 00000000 r9 : 411fc090 r8 : 00000100 r7 : 00000cfb r6 : 0144a6d0 r5 : 00000000 r4 : 00008000 r3 : 0000000c r2 : 00000100 r1 : 00000cfb r0 : 00000000 Flags: nZCv IRQs off FIQs off Mode SVC_32 Resetting CPU ... Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: nand: fix read_byte required for proper onfi detectionMarcel Ziswiler2015-08-131-31/+7
| | | | | | | | | | | | | | | | | | Fix PIO read_byte() implementation not only used for the legacy READ ID but also the PARAM command required for proper ONFI detection. This fix is inspired by Lucas Stach's Linux Tegra NAND driver of late (not mainline yet but getting there soon I hope). I vaguely remember that those commands are special on 16-bit bus NAND (e.g. always return 8-bit data regardless) and later Linux MTD fixed/ changed the way this is handled which in turn broke once U-Boot pulled that in. Basically instead of doing PIO read regular DMA block read is now used which this patch actually fixes. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
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