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* net/fm: Add QSGMII PCS initShaohui Xie2015-10-291-5/+13
| | | | | | | | | | | | QSGMII PCS needed to be programmed same as SGMII PCS, and there are four ports in QSGMII PCS, port 0, 1, 2, 3, all the four ports shared port 0's MDIO controller, so when programming port 0, we continue to program other three ports. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* net: Move some header files to include/Shaohui Xie2015-10-295-6/+6
| | | | | | | | | | The fsl_dtsec.h & fsl_tgec.h & fsl_fman.h can be shared on both ARM and PPC, move it out of ppc to include/, and change the path in drivers accordingly. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* net: fm: bug fix when CONFIG_PHYLIB not definedShaohui Xie2015-10-291-1/+7
| | | | | | | | codes related to phylib operations should be wrapped by CONFIG_PHYLIB. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* net/fm: Make the return value logic consistent with conventionHou Zhiqiang2015-10-291-24/+36
| | | | | | | | | | In convention, the '0' is a normal return value indicating there isn't an error. While some functions of FMan IM driver treat '0' as an error return value. Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* net/fm: Add support for 64-bit platformsHou Zhiqiang2015-10-293-33/+60
| | | | | | | | | | | | The FMan IM driver is developed for 32-bit platfroms and isn't friendly to 64-bit platforms, so do the minimal refactor: 1. Refine the MURAM management and access. 2. Correct the initialization and operations for QDs and BDs. Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* net/fm: Fix the endian issue to support both endianness platformsHou Zhiqiang2015-10-292-38/+43
| | | | | | | | | | | | | | | The Frame Manager(FMan) is a big-endian peripheral, so the registers, internal MURAM and BDs, which are allocated in main memory and used to communication between core and FMan, should be accessed in big-endian. The big-endian platforms can access them directly as the code implemented so far, while for the little-endian platforms it need to swap the byte-order. Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* driver: net: ldpaa_eth: Set MAC address during interface openPrabhakar Kushwaha2015-10-291-12/+3
| | | | | | | | | | Currently ldpaa ethernet driver rely on DPL file to statically configure mac address for the DPNIs. It is not a correct approach. Add support setting MAC address from env variable or Random MAC address. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* crypto/fsl: SEC driver cleanup for 64 bit and endiannessAneesh Bansal2015-10-294-20/+107
| | | | | | | | | | | | | | | | | The SEC driver code has been cleaned up to work for 64 bit physical addresses and systems where endianess of SEC block is different from the Core. Changes: 1. Descriptor created on Core is modified as per SEC block endianness before the job is submitted. 2. The read/write of physical addresses to Job Rings will be depend on endianness of SEC block as 32 bit low and high part of the 64 bit address will vary. 3. The 32 bit low and high part of the 64 bit address in descriptor will vary depending on endianness of SEC. Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* Fix bad return value checks (detected with Coccinelle)Thomas Huth2015-10-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | In the "Getting Started with Coccinelle - KVM edition" presentation that has been held by Julia Lawall at the KVM forum 2015 (see the slides at http://events.linuxfoundation.org/sites/events/files/slides/tutorial_kvm_0.pdf), she pointed out some bad return value checks in U-Boot that can be detected with Coccinelle by using the following config file: @@ identifier x,y; identifier f; statement S; @@ x = f(...); ( if (x < 0) S | if ( - y + x < 0) S ) This patch now fixes these issues. Signed-off-by: Thomas Huth <huth@tuxfamily.org>
* allow LED initialization without STATUS_LED_BOOTBernhard Nortmann2015-10-242-2/+6
| | | | | | | | | | | | | | | | | | | | For current U-Boot to initialize status LEDs via status_led_init(), it is required to have both CONFIG_STATUS_LED and STATUS_LED_BOOT defined. This may be a particular concern with GPIO LEDs, where __led_init() is required to correctly set up the GPIO (gpio_request and gpio_direction_output). Without STATUS_LED_BOOT the initialization isn't called, which could leave the user with a non-functional "led" command - due to the fact that the LED routines in gpio_led.c use gpio_set_value() just fine, but the GPIO never got set up properly in the first place. I think having CONFIG_STATUS_LED is sufficient to justify a corresponding call to status_led_init(), even with no STATUS_LED_BOOT defined. To do so, common/board_r.c needs call that routine, so it now is exposed via status_led.h. Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de> [trini: Add dummy __led_init to pca9551_led.c] Signed-off-by: Tom Rini <trini@konsulko.com>
* add generic stubs for GPIO LEDsBernhard Nortmann2015-10-231-0/+54
| | | | | | | | | | | | | | | | | For boards that support LEDs driven via GPIO (CONFIG_GPIO_LED), it may be useful to have some generic stubs (wrapper functions) for the "colored" LEDs. This allows defining STATUS_LED_* values directly to GPIO numbers, e.g.: #define STATUS_LED_GREEN 248 /* = PH24 */ To keep those optional, it's probably best to introduce an additional configuration setting. I've chosen CONFIG_GPIO_LED_STUBS for that. Placing the code in drivers/misc/gpio_led.c also ensures that it automatically depends on CONFIG_GPIO_LED too. Signed-off-by: Bernhard Nortmann <bernhard.nortmann@web.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: keystone: serial: Add driver model supportLokesh Vutla2015-10-232-0/+49
| | | | | | | Add driver model support for keystone serial driver. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Simon Glass <sjg@chromium.org>
* net: convert altera_tse to driver model and phylibThomas Chou2015-10-233-1047/+382
| | | | | | | | Convert altera_tse to driver model and phylib. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* nios2: convert altera sysid to driver modelThomas Chou2015-10-233-0/+109
| | | | | | | | Convert altera sysid to driver model with misc uclass. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: implement a Miscellaneous uclassThomas Chou2015-10-233-0/+61
| | | | | | | | | Implement a Miscellaneous uclass with generic read or write operations. This class is used only for those do not fit other more general classes. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org>
* serial: remove altera serial initializationsThomas Chou2015-10-231-4/+0
| | | | | | | | | | Both altera_jtag_serial_initialize() and altera_serial_initialize() are no longer used after they are converted to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de>
* nios2: convert altera timer to driver modelThomas Chou2015-10-233-0/+112
| | | | | | | Convert altera timer to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com>
* dm: implement a Timer uclassThomas Chou2015-10-235-0/+64
| | | | | | | Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org>
* nios2 : convert altera_pio to driver modelThomas Chou2015-10-232-240/+83
| | | | | | | | Convert altera_pio to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* spi : convert altera_spi to driver modelThomas Chou2015-10-232-86/+119
| | | | | | | Convert altera_spi to driver model Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Jagan Teki <jteki@openedev.com>
* nios2: convert altera_uart to driver modelThomas Chou2015-10-232-91/+121
| | | | | | | | Convert altera_uart to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Marek Vasut <marex@denx.de>
* nios2: convert altera_jtag_uart to driver modelThomas Chou2015-10-232-60/+137
| | | | | | | | Convert altera_jtag_uart to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* drivers: gpio: omap: add support for parsing additional gpio parametersMugunthan V N2015-10-221-0/+11
| | | | | | | | | | | | | With DM_GPIO, gpio parameters like ACTIVE_(LOW/HIGH) are to be parsed in xlate gpio drivers-ops. Since xlate is not implemented in omap_gpio driver, the driver considers all gpio to be ACTIVE_HIGH which is the default case and fails to return actual gpio status for ACTIVE_LOW gpios. So adding .xlate ops to omap_gpio. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* drivers: serial: serial_omap: add comaptibles for all ti platformsMugunthan V N2015-10-221-0/+4
| | | | | | | Adding compatibles for am335x, am437x and dra7 platforms. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* drivers: serial: serial_omap: populate default clock frequency when not ↵Mugunthan V N2015-10-221-1/+3
| | | | | | | | | | | found in dt In some platforms like am437x, serial node is not populated with clock-frequency node. So in that case have a default clock-clock frequency. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
* drivers: mmc: omap_hsmmc: convert driver to adopt device driver modelMugunthan V N2015-10-221-1/+116
| | | | | | adopt omap_hsmmc driver to device driver model Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
* ARM: k2g: add SD card and eMMC supportRoger Quadros2015-10-221-2/+5
| | | | | | | | Add MMC support for k2g Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Mugunthan V N <mugunthanvnm@ti.com>
* driver: net: keystone_net: removing unused codeMugunthan V N2015-10-221-10/+0
| | | | | | | | remove unused code as the same is achieved when configuring sgmii and link status is verifed. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* driver: net: keystone_net: add support for rgmii phyVitaly Andrianov2015-10-221-1/+43
| | | | | | | | | In K2G, Ethernet doesn't support SGMII instead it support RGMII, adding support to the driver to connect to RGMII phy. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* dma: keystone_nav: Fix linkram sizeVitaly Andrianov2015-10-221-1/+1
| | | | | | | | Fix Linkram size. Signed-off-by: Vitaly Andrianov <vitalya@ti.com> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* driver: net: keystone_net: fix phy mode configurationMugunthan V N2015-10-221-2/+2
| | | | | | | | | | Phy mode is a board property and it can be different between multiple board and ports, so it should not be hardcoded in driver to one specific mode. So adding a field in eth_priv_t structure to pass phy mode to driver. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
* remoteproc: Introduce a sandbox dummy driverNishanth Menon2015-10-223-0/+348
| | | | | | | | | | | | | | | Introduce a dummy driver for sandbox that allows us to verify basic functionality. This is not meant to do anything functional - but is more or less meant as a framework plumbing debug helper. The sandbox remoteproc driver maintains absolutey no states and is a simple driver which just is filled with empty hooks. Idea being to give an approximate idea to implement own remoteproc driver using this as a template. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Simon Glass <sjg@chromium.org>
* drivers: Introduce a simplified remoteproc frameworkNishanth Menon2015-10-225-0/+442
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many System on Chip(SoC) solutions are complex with multiple processors on the same die dedicated to either general purpose of specialized functions. Many examples do exist in today's SoCs from various vendors. Typical examples are micro controllers such as an ARM M3/M0 doing a offload of specific function such as event integration or power management or controlling camera etc. Traditionally, the responsibility of loading up such a processor with a firmware and communication has been with a High Level Operating System(HLOS) such as Linux. However, there exists classes of products where Linux would need to expect services from such a processor or the delay of Linux and operating system being able to load up such a firmware is unacceptable. To address these needs, we need some minimal capability to load such a system and ensure it is started prior to an Operating System(Linux or any other) is started up. NOTE: This is NOT meant to be a solve-all solution, instead, it tries to address certain class of SoCs and products that need such a solution. A very simple model is introduced here as part of the initial support that supports microcontrollers with internal memory (no MMU, no execution from external memory, or specific image format needs). This basic framework can then (hopefully) be extensible to other complex SoC processor support as need be. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Simon Glass <sjg@chromium.org>
* drivers: net: cpsw: convert driver to adopt device driver modelMugunthan V N2015-10-221-1/+244
| | | | | | | adopt cpsw driver to device driver model Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* drivers: net: cpsw: prepare driver for device model migrationMugunthan V N2015-10-221-44/+89
| | | | | | | prepare driver for device model migration Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-x86Tom Rini2015-10-2110-50/+89
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| * dm: rtc: Correct rtc_read32() return valueSimon Glass2015-10-211-1/+1
| | | | | | | | | | | | | | | | The current check is incorrect and will fail when any non-zero byte is read. Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * rtc: mc146818: Use probe() to set up the deviceSimon Glass2015-10-211-2/+2
| | | | | | | | | | | | | | At present this driver uses bind() to set up the device. The bind() method should not touch the hardware, so move the init code to probe(). Signed-off-by: Simon Glass <sjg@chromium.org>
| * rtc: mc146818: Add a comment to the #endifSimon Glass2015-10-211-1/+1
| | | | | | | | | | | | | | Add a comment to make it clear to which block the #endif relates. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * debug_uart: Add an option to announce the debug UARTSimon Glass2015-10-211-0/+10
| | | | | | | | | | | | | | | | | | It is useful to see a message from the debug UART early during boot so that you know things are working. Add an option to enable this. The message will be displayed as soon as debug_uart_init() is called. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * debug_uart: Support board-specific UART initialisationSimon Glass2015-10-211-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | Some boards need to set things up before the debug UART can be used. On these boards a call to debug_uart_init() is insufficient. When this option is enabled, the function board_debug_uart_init() will be called when debug_uart_init() is called. You can put any code here that is needed to set up the UART ready for use, such as set pin multiplexing or enable clocks. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * debug_uart: Adjust the declaration of debug_uart_init()Simon Glass2015-10-213-3/+3
| | | | | | | | | | | | | | | | | | | | | | We want to be able to add other common code to this function. So change the driver's version to have an underscore before it, just like _debug_uart_putc(). Define debug_uart_init() to call this version. Update all drivers to this new method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: spi: Add support for Wildcat PointGeorge McCollister2015-10-211-1/+2
| | | | | | | | | | | | | | Add the Wildcat Point ID so Broadwell U based boards can use SPI. Signed-off-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * dm: pci: Enable VGA address forwarding on bridgesBin Meng2015-10-211-0/+18
| | | | | | | | | | | | | | | | | | To support graphics card behind a PCI bridge, the bridge control register (offset 0x3e) in the configuration space must turn on VGA address forwarding. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * dm: pci: Fix pci_last_busno() to return the real last bus noBin Meng2015-10-211-24/+1
| | | | | | | | | | | | | | | | | | Currently pci_last_busno() only checks the last bridge device under the first UCLASS_PCI device. This is not the case when there are multiple bridge devices. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * video: vesa_fb: Fix wrong return value check of pci_find_class()Bin Meng2015-10-211-1/+1
| | | | | | | | | | | | | | | | | | When pci_find_class() fails to find a device, it returns -ENODEV. But now we check the return value against -1. Fix it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
| * pci: Set PCI_COMMAND_IO bit for VGA deviceBin Meng2015-10-211-0/+6
| | | | | | | | | | | | | | | | PCI_COMMAND_IO bit must be set for VGA device as it needs to respond to legacy VGA IO address. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * dm: pci: Adjust pci_find_and_bind_driver() to return -EPERMSimon Glass2015-10-211-12/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The current code returns 0 even if it failed to find or bind a driver. The caller then has to check the returned device to see if it is NULL. It is better to return an error code in this case so that it is clear what happened. Adjust the code to return -EPERM, indicating that the device was not bound because it is not needed for pre-relocation use. Add comments so that the return value is clear. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * dm: pci: Correct a few debug() statementsSimon Glass2015-10-211-2/+2
| | | | | | | | | | | | | | | | One debug() statement is missing a newline. The other has a repeated word. Fix these. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * dm: pci: Tidy up auto-config error handlingSimon Glass2015-10-211-3/+12
| | | | | | | | | | | | | | | | | | | | | | When the auto-configuration process fails for a device (generally due to lack of memory) we should return the error correctly so that we don't continue to try memory allocations which will fail. Adjust the code to check for errors and abort if something goes wrong. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
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