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path: root/drivers/net/designware.c
Commit message (Expand)AuthorAgeFilesLines
* net: designware: Add driver remove supportBin Meng2015-10-291-0/+12
* net: designware: Add support to PCI designware devicesBin Meng2015-09-161-0/+42
* net: designware: Fix build warningsBin Meng2015-09-091-4/+4
* net: designware: Rename the driver var name to eth_designwareMarek Vasut2015-08-081-1/+1
* net: designware: Add SoCFPGA GMAC DT compatible stringMarek Vasut2015-08-081-0/+1
* dm: eth: Avoid blocking on packet receptionSimon Glass2015-07-211-1/+1
* net: designware: Program MAC address to hardware after soft resetBin Meng2015-07-081-0/+6
* net: Update hardware MAC address if it changes in envJoe Hershberger2015-05-191-4/+0
* dm: net: Adjust designware driver to support driver modelSimon Glass2015-04-181-16/+151
* dm: net: Tidy up designware driver ready for driver modelSimon Glass2015-04-181-34/+53
* net: cosmetic: Fix var naming net <-> eth driversJoe Hershberger2015-04-181-1/+1
* net: Support DMA threshold mode in DWMAC driverSonic Zhang2015-03-051-0/+5
* net: configure DWMAC DMA by default AXI burst lengthSonic Zhang2015-03-051-0/+4
* net/designware: add error message on DMA reset timeoutAlexey Brodkin2015-01-301-1/+3
* net: dwc: Make the cache handling less crypticMarek Vasut2014-10-061-25/+23
* net: dwc: Fix cache alignment issuesMarek Vasut2014-10-061-2/+4
* net/designware: Make DMA burst length configurable and reduce by defaultIan Campbell2014-05-251-1/+1
* net/designware: ensure cache invalidations are aligned to ARCH_DMA_MINALIGNIan Campbell2014-05-251-5/+13
* net/designware: ensure device private data is DMA aligned.Ian Campbell2014-05-251-1/+2
* net/designware: call phy_connect_dev() to properly setup phylib deviceIan Campbell2014-05-121-0/+2
* net/designware: make driver compatible with data cacheAlexey Brodkin2014-02-071-3/+50
* net/designware - switch driver to phylib usageAlexey Brodkin2014-02-071-311/+149
* net/designware: add explicit reset of {tx|rx}_currdescnumAlexey Brodkin2014-02-071-0/+2
* net: designware: Respect "bus mode" register contents on SW resetAlexey Brodkin2013-11-221-1/+1
* Add GPL-2.0+ SPDX-License-Identifier to source filesWolfgang Denk2013-07-241-17/+1
* net/designware: Do not select MIIPORT for RGMII interfaceVipin Kumar2013-06-241-1/+3
* net/designware: Consecutive writes to the same register to be avoidedDinh Nguyen2012-07-111-2/+2
* net: Multiple updates/enhancements to designware.cStefan Roese2012-07-071-69/+49
* SPEAr: Add interface information in initializationVipin Kumar2012-07-071-1/+9
* net: Fix remaining API interface breakageJoe Hershberger2012-05-231-3/+2
* net/designware: Change timeout loop implementationAmit Virdi2012-04-041-16/+38
* net/designware: Set ANAR to 0x1e1Armando Visconti2012-04-041-0/+3
* net/designware: Program phy registers when auto-negotiation is ONVikas Manocha2012-04-041-14/+29
* net/designware: Try configuring phy on each dw_eth_initVipin Kumar2012-04-041-21/+29
* net/designware: Consecutive writes must have delayArmando Visconti2012-04-041-2/+1
* net/designware: Phy address fixVipin KUMAR2012-04-041-1/+1
* net/designware: Fix to restore hw mac addressVipin KUMAR2012-04-041-1/+6
* Add Ethernet hardware MAC address framework to usbnetSimon Glass2011-08-081-1/+1
* net: designware: fix uninitialized phy_addr usageMike Frysinger2011-07-251-0/+2
* net: designware: fix unused warning when CONFIG_DW_AUTONEG is enabledMike Frysinger2011-07-251-1/+3
* miiphy: convert to linux/mii.hMike Frysinger2011-01-091-27/+27
* miiphy: constify device nameMike Frysinger2010-08-091-2/+2
* SPEAr : Network driver support addedVipin KUMAR2010-07-121-0/+531
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