summaryrefslogtreecommitdiffstats
path: root/drivers/ddr
Commit message (Expand)AuthorAgeFilesLines
* arm: mvebu: Add complete SDRAM ECC scrubbingStefan Roese2015-08-172-2/+2
* arm: mvebu: sdram: Enable ECC support on Armada XPStefan Roese2015-08-171-1/+1
* ddr: altera: sequencer: Clean checkpatch issuesMarek Vasut2015-08-081-71/+88
* ddr: altera: sequencer: Clean data typesMarek Vasut2015-08-081-48/+48
* ddr: altera: sequencer: Pluck out misc macros from codeMarek Vasut2015-08-081-22/+15
* ddr: altera: sequencer: Zap SEQ_T(INIT|RESET)_CNTR._VALMarek Vasut2015-08-082-49/+4
* ddr: altera: sequencer: Zap VFIFO_SIZEMarek Vasut2015-08-082-7/+4
* ddr: altera: sequencer: Wrap misc remaining macrosMarek Vasut2015-08-081-0/+2
* ddr: altera: sequencer: Pluck out IO_* macros from codeMarek Vasut2015-08-081-101/+100
* ddr: altera: sequencer: Wrap IO_* macrosMarek Vasut2015-08-081-0/+2
* ddr: altera: sequencer: Pluck out RW_MGR_* macros from codeMarek Vasut2015-08-082-154/+154
* ddr: altera: sequencer: Wrap RW_MGR_* macrosMarek Vasut2015-08-081-0/+4
* ddr: altera: sequencer: Wrap ac_rom_init and inst_rom_initMarek Vasut2015-08-081-6/+8
* ddr: altera: sequencer: Zap bogus redefinition of RW_MGR_MEM_NUMBER_OF_RANKSMarek Vasut2015-08-081-1/+0
* ddr: altera: sequencer: Zap unused params and macrosMarek Vasut2015-08-082-75/+5
* ddr: altera: sequencer: Move qts-generated files to board dirMarek Vasut2015-08-085-605/+9
* ddr: altera: sdram: Make sdram_start and sdram_end into u32Marek Vasut2015-08-081-11/+12
* ddr: altera: sdram: Minor cleanup in sdram_get_rule()Marek Vasut2015-08-081-4/+4
* ddr: altera: sdram: Minor cleanup in sdram_set_rule()Marek Vasut2015-08-081-4/+4
* ddr: altera: sdram: Add missing kerneldocMarek Vasut2015-08-081-0/+12
* ddr: altera: sdram: Clean up sdram_write_verify()Marek Vasut2015-08-081-25/+26
* ddr: altera: sdram: Clean up sdram_calculate_size() part 2Marek Vasut2015-08-081-23/+12
* ddr: altera: sdram: Clean up sdram_calculate_size() part 1Marek Vasut2015-08-081-9/+10
* ddr: altera: sdram: Introduce socfpga_sdram_get_config()Marek Vasut2015-08-081-211/+5
* ddr: altera: sdram: Clean up sdram_mmr_init_full() part 8Marek Vasut2015-08-081-1/+2
* ddr: altera: sdram: Clean up sdram_mmr_init_full() part 7Marek Vasut2015-08-081-1/+6
* ddr: altera: sdram: Clean up sdram_mmr_init_full() part 6Marek Vasut2015-08-081-10/+21
* ddr: altera: sdram: Clean up sdram_mmr_init_full() part 5Marek Vasut2015-08-081-10/+11
* ddr: altera: sdram: Clean up sdram_mmr_init_full() part 4Marek Vasut2015-08-081-62/+36
* ddr: altera: sdram: Clean up sdram_mmr_init_full() part 3Marek Vasut2015-08-081-28/+39
* ddr: altera: sdram: Clean up sdram_mmr_init_full() part 2Marek Vasut2015-08-081-67/+83
* ddr: altera: sdram: Clean up sdram_mmr_init_full() part 1Marek Vasut2015-08-081-44/+0
* ddr: altera: sdram: Introduce socfpga_sdram_config() structureMarek Vasut2015-08-081-162/+179
* ddr: altera: sdram: Clean up set_sdr_mp_threshold()Marek Vasut2015-08-081-13/+11
* ddr: altera: sdram: Clean up set_sdr_mp_pacing()Marek Vasut2015-08-081-21/+16
* ddr: altera: sdram: Clean up set_sdr_mp_weight()Marek Vasut2015-08-081-21/+16
* ddr: altera: sdram: Clean up set_sdr_fifo_cfg()Marek Vasut2015-08-081-7/+7
* ddr: altera: sdram: Clean up set_sdr_static_cfg()Marek Vasut2015-08-081-8/+7
* ddr: altera: sdram: Clean up set_sdr_addr_rw()Marek Vasut2015-08-081-20/+10
* ddr: altera: sdram: Clean up set_sdr_dram_timing*()Marek Vasut2015-08-081-93/+53
* ddr: altera: sdram: Clean up set_sdr_ctrlcfg()Marek Vasut2015-08-081-38/+24
* ddr: altera: sdram: Clean up compute_errata_rows() part 2Marek Vasut2015-08-081-15/+20
* ddr: altera: sdram: Clean up compute_errata_rows() part 1Marek Vasut2015-08-081-7/+7
* ddr: altera: sdram: Switch to generic_hweight32()Marek Vasut2015-08-081-1/+1
* ddr: altera: Clean up of delay_for_n_mem_clocks() part 5Marek Vasut2015-08-081-3/+5
* ddr: altera: Clean up of delay_for_n_mem_clocks() part 4Marek Vasut2015-08-081-12/+5
* ddr: altera: Clean up of delay_for_n_mem_clocks() part 3Marek Vasut2015-08-081-18/+6
* ddr: altera: Clean up of delay_for_n_mem_clocks() part 2Marek Vasut2015-08-081-8/+10
* ddr: altera: Clean up of delay_for_n_mem_clocks() part 1Marek Vasut2015-08-081-14/+13
* ddr: altera: Minor clean up of rw_mgr_mem_handoff()Marek Vasut2015-08-081-7/+8
OpenPOWER on IntegriCloud