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* driver/ddr/fsl: Fix driver to support empty first slotYork Sun2015-04-231-2/+3
| | | | | | | | CS0 was not allowed to be empty by u-boot driver in the past to simplify the driver. This may be inconvenient for some debugging. This patch lifts the restrictions. Controller interleaving still requires CS0 populated. Signed-off-by: York Sun <yorksun@freescale.com>
* drivers/ddr/fsl: Update DDR driver for DDR4York Sun2015-04-231-1/+50
| | | | | | | | | | Add/update registers for DDR4, including DQ mappings. Allow raw timing method used for all controllers. Update mode_9 register to 0x500 for improved stability. Check DDR controller version number individually in case a SoC has multiple DDR controllers of different versions. Increase read-write turnaround for DDR4 high speeds. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Fix tXP and tCKEYork Sun2014-09-251-2/+0
| | | | | | | | The driver was written using old DDR3 spec which only covers low speeds. The value would be suboptimal for higher speeds. Fix both timing according to latest DDR3 spec, remove tCKE as an config option. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Add support of overriding chip select write levelingYork Sun2014-09-081-0/+2
| | | | | | | | | | JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This is not an issue unless some DQ pins are not connected. If a platform uses regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on those floating pins for the second rank. The workaround is to use a known good chip select for this purpose. Signed-off-by: York Sun <yorksun@freescale.com>
* driver/ddr/fsl: Fix printing unspecified module info for DDR4York Sun2014-06-051-1/+1
| | | | | | The offset of module information is at 128, different from DDR3. Signed-off-by: York Sun <yorksun@freescale.com>
* Add cli_ prefix to readline functionsSimon Glass2014-05-291-3/+4
| | | | | | This makes it clear where the code resides. Signed-off-by: Simon Glass <sjg@chromium.org>
* move CLI prototypes to cli.h and add commentsSimon Glass2014-05-291-0/+1
| | | | | | | Move the CLI prototypes from common.h to cli.h as part of an effort to reduce the size of common.h. Signed-off-by: Simon Glass <sjg@chromium.org>
* driver/ddr/fsl: Add DDR4 support to Freescale DDR driverYork Sun2014-04-221-11/+380
| | | | | | | Mostly reusing DDR3 driver, this patch adds DDR4 SPD handling, register calculation and programming. Signed-off-by: York Sun <yorksun@freescale.com>
* Driver/DDR: Moving Freescale DDR driver to a common driverYork Sun2013-11-251-0/+1871
Freescale DDR driver has been used for mpc83xx, mpc85xx, mpc86xx SoCs. The similar DDR controllers will be used for ARM-based SoCs. Signed-off-by: York Sun <yorksun@freescale.com>
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