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| author | York Sun <yorksun@freescale.com> | 2014-09-05 13:52:43 +0800 |
|---|---|---|
| committer | York Sun <yorksun@freescale.com> | 2014-09-08 10:30:34 -0700 |
| commit | ef87cab66492fe530bb6ec2e499b030c5ae60286 (patch) | |
| tree | 5e96a47140a0a142c05e936ffbb66f8ff0c31c8c /drivers/ddr/fsl/interactive.c | |
| parent | 5cb27c5d44ac789f0f0583b57c15dc708ca55c69 (diff) | |
| download | talos-obmc-uboot-ef87cab66492fe530bb6ec2e499b030c5ae60286.tar.gz talos-obmc-uboot-ef87cab66492fe530bb6ec2e499b030c5ae60286.zip | |
driver/ddr/fsl: Add support of overriding chip select write leveling
JEDEC spec allows DRAM vendors to use prime DQ for write leveling. This
is not an issue unless some DQ pins are not connected. If a platform uses
regular DIMMs but with reduced DDR ECC pins, the prime DQ may end up on
those floating pins for the second rank. The workaround is to use a known
good chip select for this purpose.
Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'drivers/ddr/fsl/interactive.c')
| -rw-r--r-- | drivers/ddr/fsl/interactive.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/ddr/fsl/interactive.c b/drivers/ddr/fsl/interactive.c index 7fb418744e..6aa16b23dd 100644 --- a/drivers/ddr/fsl/interactive.c +++ b/drivers/ddr/fsl/interactive.c @@ -511,6 +511,7 @@ static void fsl_ddr_options_edit(fsl_ddr_info_t *pinfo, CTRL_OPTIONS(wrlvl_override), CTRL_OPTIONS(wrlvl_sample), CTRL_OPTIONS(wrlvl_start), + CTRL_OPTIONS(cswl_override), CTRL_OPTIONS(rcw_override), CTRL_OPTIONS(rcw_1), CTRL_OPTIONS(rcw_2), @@ -801,6 +802,7 @@ static void print_memctl_options(const memctl_options_t *popts) CTRL_OPTIONS(wrlvl_override), CTRL_OPTIONS(wrlvl_sample), CTRL_OPTIONS(wrlvl_start), + CTRL_OPTIONS_HEX(cswl_override), CTRL_OPTIONS(rcw_override), CTRL_OPTIONS(rcw_1), CTRL_OPTIONS(rcw_2), |
