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* Merge git://git.denx.de/u-boot-dmTom Rini2015-06-055-80/+104
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| * sandbox: Compile test device tree when CONFIG_UT_DM is definedSimon Glass2015-06-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | A conflict between the PMIC and unit test work means that the sandbox test device tree file is no-longer built. Fix this. Series-to: u-boot Series-cc: joe, prz Change-Id: I6616428e05713e5306f848e7dd0a645dedf0934e Signed-off-by: Simon Glass <sjg@chromium.org>
| * sandbox: dts: Add the real-time-clock test nodes back inSimon Glass2015-06-041-0/+18
| | | | | | | | | | | | | | | | | | These were lost when the PMIC series was applied. Add them back so that the tests pass again. Reported-by: Joe Hershberger <joe.hershberger@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * sandbox: dts: Sort the sandbox.dts fileSimon Glass2015-06-041-52/+54
| | | | | | | | | | | | Sort this by node name for easier browsing. Signed-off-by: Simon Glass <sjg@chromium.org>
| * sandbox: dts: Sort the test.dts file a littleSimon Glass2015-06-041-24/+24
| | | | | | | | | | | | | | | | There are some core test nodes near the beginning of the file which should be grouped together. But for other nodes, let's sort them. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * sandbox: Tidy up terminal restoreSimon Glass2015-06-042-3/+7
| | | | | | | | | | | | | | | | | | For some reason 'u-boot -D' does not restore the terminal correctly when the 'reset' command is used. Call the terminal restore function explicitly in this case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* | x86: gpio: add pinctrl support from the device treeGabriel Huau2015-06-042-0/+24
| | | | | | | | | | | | | | | | | | Every pin can be configured now from the device tree. A dt-bindings has been added to describe the different property available. Change-Id: I1668886062655f83700d0e7bbbe3ad09b19ee975 Signed-off-by: Gabriel Huau <contact@huau-gabriel.fr> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: baytrail: pci region 3 is not always mapped to end of ramAndrew Bradford2015-06-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Baytrail physically maps the first 2 GB of SDRAM from 0x0 to 0x7FFFFFFF and additional SDRAM is mapped from 0x100000000 and up. There is a physical memory hole from 0x80000000 to 0xFFFFFFFF for other uses. Because of this, PCI region 3 should only try to use up to the amount of SDRAM or 0x80000000, which ever is less. Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: qemu: Implement PIRQ routingBin Meng2015-06-044-0/+61
| | | | | | | | | | | | | | | | | | Support QEMU PIRQ routing via device tree on both i440fx and q35 platforms. With this commit, Linux booting on QEMU from U-Boot has working ATA/SATA, USB and ethernet. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: coreboot: Control I/O port 0xb2 writing via device treeBin Meng2015-06-042-3/+10
| | | | | | | | | | | | | | | | | | | | Writing 0xcb to I/O port 0xb2 (Advanced Power Management Control) causes U-Boot to hang on QEMU q35 target. We introduce a config option in the device tree "u-boot,no-apm-finalize" under /config node if we don't want to do that. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: qemu: Create separate i440fx and q35 device treesBin Meng2015-06-043-2/+37
| | | | | | | | | | | | | | | | | | | | Although the two qemu-x86 targets (i440fx and q35) share a lot in common, they still have something that cannot easily handled in one single device tree). Split to create two dedicated device tree files and make the i440fx be the default build target. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: coreboot: Fix cosmetic issuesBin Meng2015-06-042-25/+3
| | | | | | | | | | | | | | Clean up arch/x86/cpu/coreboot.c to fix several cosmetic issues. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: kconfig: Make FSP_TEMP_RAM_ADDR depend on HAVE_FSPBin Meng2015-06-041-0/+1
| | | | | | | | | | | | | | FSP_TEMP_RAM_ADDR should only be visible when HAVE_FSP is on. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: qemu: Adjust VGA initializationBin Meng2015-06-042-19/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | As VGA option rom needs to run at C segment, although QEMU PAM emulation seems to only guard E/F segments, for correctness, move VGA initialization after PAM decode C/D/E/F segments. Also since we already tested QEMU targets to differentiate I440FX and Q35 platforms, change to locate the VGA device via hardcoded b.d.f instead of dynamic search for its vendor id & device id pair. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: qemu: Enable legacy IDE I/O ports decodeBin Meng2015-06-043-0/+38
| | | | | | | | | | | | | | | | | | QEMU always decode legacy IDE I/O ports on PIIX chipset. However Linux ata_piix driver does sanity check to see whether legacy ports decode is turned on. To make Linux ata_piix driver happy, turn on the decode via IDE_TIMING register. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: qemu: Turn on legacy segments decodeBin Meng2015-06-042-0/+26
| | | | | | | | | | | | | | | | | | By default the legacy segments C/D/E/F do not decode to system RAM. Turn on the decode via Programmable Attribute Map (PAM) registers so that we can write configuration tables in the F segment. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: fsp_support: Correct high mem comment typoAndrew Bradford2015-06-041-1/+1
| | | | | | | | | | | | | | | | High mem starts at 4 GiB. Signed-off-by: Andrew Bradford <andrew.bradford@kodakalaris.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: Do sanity test on pirq table before writingBin Meng2015-06-041-0/+3
| | | | | | | | | | | | | | | | | | If pirq_routing_table points to NULL, that means U-Boot fails to generate the table before in create_pirq_routing_table(), so we test it against NULL before actually writing it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: quark: Implement PIRQ routingBin Meng2015-06-044-15/+123
| | | | | | | | | | | | | | | | | | Intel Quark SoC has the same interrupt routing mechanism as the Queensbay platform, only the difference is that PCI devices' INTA/B/C/D are harcoded and cannot be changed freely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: Refactor PIRQ routing supportBin Meng2015-06-048-300/+383
| | | | | | | | | | | | | | | | | | | | | | | | PIRQ routing is pretty much common in Intel chipset. It has several PIRQ links (normally 8) and corresponding registers (either in PCI configuration space or memory-mapped IBASE) to configure the legacy 8259 IRQ vector mapping. Refactor current Queensbay PIRQ routing support using device tree and move it to a common place, so that we can easily add PIRQ routing support on a new platform. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: qemu: Add graphics supportBin Meng2015-06-041-1/+23
| | | | | | | | | | | | | | | | It turns out that QEMU x86 emulated graphic card has a built-in option ROM which can be run perfectly with native mode by U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: Move FRAMEBUFFER_SET_VESA_MODE etc to video KconfigBin Meng2015-06-041-141/+0
| | | | | | | | | | | | | | | | | | | | CONFIG_FRAMEBUFFER_SET_VESA_MODE and CONFIG_FRAMEBUFFER_VESA_MODE are not x86-specific, so move them to drivers/video/Kconfig and make them depend on VIDEO_VESA driver. Some cosmetic fixes are applied to the Kconfig help text as well. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | x86: Make QEMU the default vendorBin Meng2015-06-041-1/+1
| | | | | | | | | | | | | | | | | | Now that we have QEMU support, make it the default vendor in the 'make menuconfig' screen. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* | x86: Support QEMU x86 targetsBin Meng2015-06-0412-1/+259
|/ | | | | | | | | | | This commit introduces the initial U-Boot support for QEMU x86 targets. U-Boot can boot from coreboot as a payload, or directly without coreboot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Merged in patch 'x86: qemu: Add CMD_NET to qemu-x86_defconfig https://patchwork.ozlabs.org/patch/479745/
* Merge branch 'rmobile' of git://git.denx.de/u-boot-shTom Rini2015-06-012-0/+26
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| * arm: rmobile: alt: Update to QoS revision 0.31 and 0.321Nobuhiro Iwamatsu2015-06-012-1/+5
| | | | | | | | | | | | | | | | This updates r8a7794 QoS to revision 0.31 for ES1 and revision 0.321 for ES2. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * arm: rmobile: gose: Update to QoS revision 0.311Nobuhiro Iwamatsu2015-06-011-1/+1
| | | | | | | | | | | | | | | | This updates r8a7793 QoS to revision 0.311. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * arm: rmobile: koelsch: Update to QoS revision 0.411Nobuhiro Iwamatsu2015-06-011-1/+1
| | | | | | | | | | | | | | | | This updates r8a7791 QoS to revision 0.411. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * arm: rmobile: lager: Update to QoS revision 0.973Nobuhiro Iwamatsu2015-06-011-0/+22
| | | | | | | | | | | | | | | | | | This updates r8a7790 QoS to revision 0.973. This commit can changed from KConfig to fit contents of the QoS. Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2015-05-3043-146/+98
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| * | ARM: UniPhier: add pin mux setting for NAND CS1 of PH1-Pro4Masahiro Yamada2015-05-311-0/+2
| | | | | | | | | | | | | | | | | | | | | The chip select 1 of the NAND controller is available if you want to use, although the pins are shared with UART port 2. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: UniPhier: fix pin mux setting for USB port 2 of PH1-sLD8Masahiro Yamada2015-05-311-2/+2
| | | | | | | | | | | | | | | | | | The register value should be 1, not 4. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: UniPhier: update DDR PHY register map for PH1-Pro5Masahiro Yamada2015-05-311-4/+7
| | | | | | | | | | | | | | | | | | | | | PH1-Pro5 includes a newer version of DDR PHY IP. Some registers have been added to the reserved areas. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: UniPhier: set MACH_PH1_PRO4 as default SoCMasahiro Yamada2015-05-311-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One disadvantage of commit a26cd04920dc (arch: Make board selection choices optional) is that Kconfig could create such an insane .config file that no board is selected. As PH1-Pro4 is the main stream of UniPhier SoC family, rip off the "optional" again in favor of PH1-Pro4 as the default SoC. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: UniPhier: remove meaningless CONFIG_SPL_BUILD ifdefsMasahiro Yamada2015-05-311-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | This file is only built for SPL. These ifdef conditionals are unnecessary because UniPhier platform now supports UART on SPL. Show appropriate messages on error. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: UniPhier: remove unnecessary cache coherency codeMasahiro Yamada2015-05-311-23/+1
| | | | | | | | | | | | | | | | | | | | | | | | Cache coherency for SMP is cared by Linux. In U-Boot, the secondary CPU(s) are just sleeping. Nothing in memory is shared with the primary CPU. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: UniPhier: use 32 bit register access for debug UART settingMasahiro Yamada2015-05-311-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | For the same reason as commit d0c47b3ef7c5 (serial: UniPhier: use 32 bit register access), use "str" instead of "strb" for the LCR register setting. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: UniPhier: update the vendor name of UniPhier in KconfigMasahiro Yamada2015-05-312-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | The business for UniPhier Soc family has been transferred from Panasonic Corporation to Socionext Inc. Update the SoC select menu in Kconfig. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: UniPhier: replace <asm/io.h> with <linux/io.h>Masahiro Yamada2015-05-3138-104/+76
| |/ | | | | | | | | | | | | In the Linux coding style, it is recommended to include <linux/io.h> rather than <asm/io.h>. Follow this trend. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: sunxi: Share sun6i PSCI backend with sun8iChen-Yu Tsai2015-05-292-0/+5
| | | | | | | | | | | | | | | | | | sun8i can share the PSCI backend with sun6i. Only difference is sun8i does not have CPU power clamp controls. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | ARM: sunxi: Add sun6i specific PSCI implementationChen-Yu Tsai2015-05-292-0/+277
| | | | | | | | | | | | | | | | | | This adds PSCI support for sun6i. So far it only supports the PWR_ON method. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | ARM: sunxi: Make PSCI code sun7i specificChen-Yu Tsai2015-05-292-1/+1
| | | | | | | | | | | | | | | | | | | | | | The PSCI code only works for sun7i. Rename it with _sun7i suffix, and build only if building for sun7i. This paves the way for adding PSCI support for other platforms. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | ARM: sunxi: Document registers in PSCI codeChen-Yu Tsai2015-05-291-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | The PSCI CPU_ON code accesses quite a few registers. Document their names to make it easier to cross reference. Also explain "lock cpu" and "unlock cpu" as enabling/disabling debug access. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi/nand: Add support to the SPL for loading u-boot from internal NAND memoryDaniel Kochmański2015-05-293-2/+81
| | | | | | | | | | | | | | | | | | | | | | This commit adds support to the sunxi SPL to load u-boot from the internal NAND. Note this only adds support to access the boot partitions to load u-boot, full NAND support to load the kernel, etc. from the nand data partition will come later. Signed-off-by: Roy Spliet <r.spliet@ultimaker.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi: Match sun4i, sun6i, sun9i CCI definitions for NAND and DMARoy Spliet2015-05-293-3/+10
| | | | | | | | | | | | | | | | | | Make sure definitions for NAND clock and DMA gate bits are the same across boards. Signed-off-by: Roy Spliet <r.spliet@ultimaker.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi: Add DMA definitionsRoy Spliet2015-05-292-0/+84
| | | | | | | | | | | | Signed-off-by: Roy Spliet <r.spliet@ultimaker.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sun9i: Basic sun9i (A80) supportHans de Goede2015-05-294-0/+10
| | | | | | | | | | | | | | Add initial sun9i (A80) support, only uart + mmc are supported for now. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Remove support for building "old-fashioned" fel binariesHans de Goede2015-05-291-8/+0
| | | | | | | | | | | | | | | | | | | | The latest versions of the fel tool support loading normal u-boot builds directly, and this is now the preferred way to use the fel boot method. This commit removes support for the old deprecated standalone fel builds. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Use axp221 sid on a33Hans de Goede2015-05-291-5/+3
|/ | | | | | | | | Unlike the A31 and the A23 the A33 actually has a SID inside the SoC again, but sid[3] is 0 (at least on some SoCs), so it is better to use the axp221 sid. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARMv7M: add STM32F1 supportMatt Porter2015-05-288-0/+782
| | | | | | Add ARMv7M STM32F1 support including clocks, timer, gpio, and flash. Signed-off-by: Matt Porter <mporter@konsulko.com>
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