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* x86: Add ACPI table support to QEMUSaket Sinha2015-08-262-0/+177
| | | | | | | | | This patch mainly adds ACPI support to QEMU. Verified by booting Linux kernel on QEMU Q35. Signed-off-by: Saket Sinha <saket.sinha89@gmail.com> Minor whitespace fixes and dropped mention of i440FX in commit message: Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Generate a valid ACPI tableSaket Sinha2015-08-265-0/+844
| | | | | | | | | | | | | | | | | Implement write_acpi_table() to create a minimal working ACPI table. This includes writing FACS, XSDT, RSDP, FADT, MCFG, MADT, DSDT & SSDT ACPI table entries. Use a Kconfig option GENERATE_ACPI_TABLE to tell U-Boot whether we need actually write the APCI table just like we did for PIRQ routing, MP table and SFI tables. With ACPI table existence, linux kernel gets control of power management, thermal management, configuration management and monitoring in hardware. Signed-off-by: Saket Sinha <saket.sinha89@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tidied up whitespace and aligned some tabs: Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: superio: Add keyboard controller support to smsc_lpc47m driverBin Meng2015-08-261-0/+3
| | | | | | | | | Add an api to enable and configure the integrated keyboard controller on SMSC LPC47m superio chipset. It also adds several macros to help future extension. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: Remove the fsp_init_phase_pci() callBin Meng2015-08-261-7/+1
| | | | | | | | | It turns out that calling fsp_init_phase_pci() in arch_misc_init() is subject to break pci device drivers as with driver model, when the bus enumeration happens is not deterministic. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: queensbay: Move unprotect_spi_flash() to arch_misc_init()Bin Meng2015-08-261-2/+2
| | | | | | | | | | With dm pci conversion, pci config read/write in unprotect_spi_flash() silently fails as at that time dm pci is not ready and bus enumeration is not done yet. Actually we don't need to do this in that early phase, hence we delay this call to arch_misc_init(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Add comments about U-Boot entering start.S twiceBin Meng2015-08-263-4/+6
| | | | | | | | | Add some comments in start.S for the fact that with FSP U-Boot actually enters the code twice. Also change to use fsp_init() and fsp_continue for accuracy. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Enlarge the size of malloc() pool before relocationBin Meng2015-08-263-1/+30
| | | | | | | | | | After fsp_init() returns, the stack has already been switched to a place within system memory as defined by CONFIG_FSP_TEMP_RAM_ADDR. Enlarge the size of malloc() pool before relocation since we have plenty of memory now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: Support multiple microcode copiesBin Meng2015-08-262-0/+9
| | | | | | | | | | | | Intel FSP has the capability to walk through the microcode blocks which are passed as the TempRamInit() parameter from U-Boot and finds the most appropriate microcode which is suitable for the cpu on which it is running. Now we've seen several steppings for Intel BayTrail series processors, adding those microcodes to the Intel BayleyBay and MinnowMax board device tree files. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: Add microcode for BayTrail-I D0 steppingBin Meng2015-08-261-0/+3284
| | | | | | | | This commit adds the microcode blob for BayTrail-I D0 stepping, CPUID signature 30679h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: kconfig: Hide "System tables" for corebootBin Meng2015-08-261-1/+1
| | | | | | | When booting as a coreboot payload, we don't need write any configuration tables as coreboot does that for us. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: kconfig: Hide "System tables" for EFIBin Meng2015-08-261-3/+1
| | | | | | | Instead of hiding each menu entries under "System tables" for EFI, hide the main menu completely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: coreboot: Allow >=4GiB memory bank sizeBin Meng2015-08-261-5/+4
| | | | | | | Some platforms may have >=4GiB memory, so we need make U-Boot report such configuration correctly when booting as the coreboot payload. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Remove calculate_relocation_address()Bin Meng2015-08-263-60/+2
| | | | | | | Now that we have generic routine to calculate relocation address, remove the x86 specific one which is now only used by coreboot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: coreboot: Correctly report E820 typesBin Meng2015-08-261-2/+13
| | | | | | | coreboot has some extensions (type 6 & 16) to the E820 types. When we detect this, mark it as E820_RESERVED. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: coreboot: Increase memrange entry number to 32Bin Meng2015-08-261-6/+3
| | | | | | | | | Increase lib_sysinfo memrange entry number to 32 to sync with coreboot. This allows a complete E820 table to be reported to the kernel, as on some platforms (eg: Bayley Bay) having only 16 entires does not cover all the memory ranges. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* Merge git://git.denx.de/u-boot-pxaTom Rini2015-08-246-72/+57
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| * arm: pxa: clean-up include file orderMarcel Ziswiler2015-08-242-3/+3
| | | | | | | | | | | | | | Cleaning up order of include files by sorting them alphabetically keeping in mind to leave common.h on top. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
| * arm: pxa: use common timer functionsAndrew Ruder2015-08-243-69/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves pxa to the common timer functions added in commit 8dfafdd - Introduce common timer functions <Rob Herring> The (removed) pxa timer code (specifically __udelay()) could deadlock at the 32-bit boundary of get_ticks(). get_ticks() returned a 32-bit value cast up to a 64-bit value. If get_ticks() + tmo in __udelay() crossed the 32-bit boundary, the while condition became unconditionally true and locked the processor. Rather than patch the specific pxa issues, simply move everything over to the common code. Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsuiko.com>
| * pxa: Fix boot hang by avoiding vector relocationAndrew Ruder2015-08-242-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 3ff46cc42b9d73d0 ("arm: relocate the exception vectors") pxa does not boot anymore. Add a specific relocate_vectors macro that skips the vector relocation, as the pxa SoC does not provide RAM at the high vectors address (0xFFFF0000), and (0x00000000) maps to ROM. This allows pxa to boot again. Cc: Marek Vasut <marex@denx.de> Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2015-08-242-4/+4
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| * MIPS: fix syntax for fdt_chosen/initrd.Govindraj Raja2015-08-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | The syntax for the fdt_chosen/initrd functions seem to deprecated in usage from MIPS bootm implementation. Third parameter is no more used in these api's Refer to : include/fdt_support.h Signed-off-by: Govindraj Raja <govindraj.raja@imgtec.com>
| * mips: Use unsigned int when reading c0 registersChris Packham2015-08-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit a18a477 (MIPS: use common code from lib/time.c) MIPS platforms started using common the common timer functions which are based around the fact that many platforms have a 32-bit free running counter register that can be used see commit 8dfafdd (Introduce common timer functions). Even MIPS64 has such a 32-bit register (some have an additional 64-bit free running counter, but that's something for another time). The problem is that in __read_32bit_c0_register() we read the value from this register into an _signed_ int and as it's returned up the call chain to timer_read_counter() it gets assigned to an unsigned long. On a 32-bit system there is no problem. On a 64-bit system odd things happen, sign extension seems to kick in and all of a sudden if the counter register happens to have the MSb (i.e. the sign bit) set the negative int gets sign extended into a very large unsigned long value. This in turn throws out things from get_ticks() up. Update __read_32bit_c0_register() and __read_32bit_c0_ctrl_register() to use "unsigned int res;" instead of "int res;". There seems to be little reason to treat these register values as signed. They are either counters (which by definition are unsigned) or are made up of various bit fields to be interpreted as per the CPU datasheet. Reported-by: Sachin Surendran <sachin.surendran@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com>
* | Merge git://git.denx.de/u-boot-socfpgaTom Rini2015-08-2315-34/+769
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: configs/socfpga_arria5_defconfig configs/socfpga_cyclone5_defconfig configs/socfpga_socrates_defconfig Merged these by hand and re-ran savedefconfig on them. Signed-off-by: Tom Rini <trini@konsulko.com>
| * | arm: socfpga: Fix SD/MMC boot on ArriaV SoCDKMarek Vasut2015-08-231-0/+6
| | | | | | | | | | | | | | | | | | | | | Add the missing DT nodes, so that ArriaV SoCDK can boot from SD card. The SD card must be in slot J5 and BSEL must be 0x5. Signed-off-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: dts: Add bank-name property to each GPIO bankMarek Vasut2015-08-231-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Add "bank-name" property to each GPIO bank to give it unique name. The approach here is exactly the same as with the "regulator-name" property for regulators. Signed-off-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: Make the pinmux table const u8Marek Vasut2015-08-234-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we're actually converting the QTS-generated header files, we can even adjust their data types. A good candidate for this is the pinmux table, where each entry can have value in the range of 0..3, but each element is declared as unsigned long. By changing the type to u8, we can save over 600 Bytes from the SPL, so do it. This patch also constifies the array. Signed-off-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: Switch to filtered QTS filesMarek Vasut2015-08-233-30/+8
| | | | | | | | | | | | Signed-off-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: Add qts-filter.sh scriptMarek Vasut2015-08-231-0/+205
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add script which loads the QTS-generated sources and headers and converts them into sensible format which can be used with much more easy in mainline U-Boot. The script also filters out macros which makes no sense anymore, so they don't pollute namespace and waste space. Signed-off-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: Split Altera socfpga into AV and CV SoCDKMarek Vasut2015-08-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The board/altera/socfpga directory is not a generic SoCFPGA machine anymore, but instead it represents the Altera SoCDK board. To make matters more complicated, it represents both CycloneV and ArriaV variant. On the other hand, nowadays, the content of this board directory is mostly comprised of QTS-generated header files, while all the generic code is in arch/arm/mach-socfpga already. Thus, this patch splits the board/altera/socfpga into a separate board directory for ArriaV SoCDK and CycloneV SoCDK, so that each can be populated with the correct QTS-generated header files for that particular board. Signed-off-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: Unbind CPU type from board typeMarek Vasut2015-08-231-8/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CONFIG_TARGET_SOCFPGA_CYCLONE5 and CONFIG_TARGET_SOCFPGA_ARRIA5 selected both a board and a CPU. This is not correct as these macros are supposed to select only board. All would be good, if QTS-generated header files didn't check for these macros exactly to determine if the platform is Cyclone V or Arria V. Thus, for the sake of compatibility with not well fleshed out header file generator, this patch makes these two macros into a stub config option and introduces new CONFIG_TARGET_SOCFPGA_CYCLONE5_SOCDK and CONFIG_TARGET_SOCFPGA_ARRIA5_SOCDK targets, which select the previous stub config option. The result is that compatibility with QTS is preserved and the new CONFIG_TARGET_* select actual target boards. Signed-off-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: Move wrappers into platform directoryMarek Vasut2015-08-235-0/+545
| | | | | | | | | | | | | | | | | | | | | | | | | | | Move the wrappers for QTS-generated files into platform directory out of the board directory. The trick here is to add -I to CFLAGS such that it points to the board directory in source tree and thus the qts/ directory there is still reachable. Signed-off-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: Do not enable gmac1 in Cyclone V dtsiMarek Vasut2015-08-232-6/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GMAC which is enabled is purely board property, so do not enable arbitrary GMAC in DT include files. Same goes for PHY mode, which is again a board property. The CycloneV SoCDK does this correctly, but SoCrates doesn't. This bug never manifested itself though, since all the boards ever used the GMAC1 . This bug manifests itself only on boards that utilise GMAC0. Signed-off-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: Make the DT mmc node consistentMarek Vasut2015-08-232-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | The socfpga_cyclone5.dtsi has an mmc0 node, socrates has mmc node. This makes aliases not very usable, so make everything into mmc0. Moreover, zap the useless mmc alias while at this. Signed-off-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: Fix delay in clock managerMarek Vasut2015-08-231-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | This code claims it needs to wait 7us, yet it uses get_timer() function which operates with millisecond granularity. Use timer_get_us() instead, which operates with microsecond granularity. Signed-off-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: Fix delay in freeze controllerMarek Vasut2015-08-231-7/+5
| |/ | | | | | | | | | | | | | | | | | | | | | | Based on observation, this udelay(20) was apparently too high and caused subsequent failure to calibrate DDR when U-Boot was compiled with certain toolchains. Lowering this delay fixed the problem. Instead of permanently lowering the delay, calculate the correct delay based on the original comment, that is, obtain EOSC1 frequency and use it to calculate the precise delay. Signed-off-by: Marek Vasut <marex@denx.de>
* | arm: at91: add support for mini-box picosam9g45 boardErik van Luijk2015-08-212-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bootlog: U-Boot SPL 2015.10-rc1-00452-g96a7ed1 (Aug 17 2015 - 10:32:21) mci: setting clock 258000 Hz, block size 512 mci: setting clock 258000 Hz, block size 512 mci: setting clock 258000 Hz, block size 512 mci: setting clock 33024000 Hz, block size 512 reading u-boot.img reading u-boot.img U-Boot 2015.10-rc1-00452-g96a7ed1 (Aug 17 2015 - 10:32:21 +0000) CPU: AT91SAM9G45 Crystal frequency: 12 MHz CPU clock : 400 MHz Master clock : 133.333 MHz Watchdog enabled DRAM: 256 MiB WARNING: Caches not enabled MMC: mci: 0 mci: setting clock 260416 Hz, block size 512 mci: setting clock 260416 Hz, block size 512 mci: setting clock 260416 Hz, block size 512 mci: setting clock 33333333 Hz, block size 512 reading uboot.env In: serial Out: serial Err: serial Net: macb0 Error: macb0 address not set. Hit any key to stop autoboot: 0 U-Boot> Signed-off-by: Erik van Luijk <evanluijk@interact.nl> [add 'picosam9g45_defconfig' to MAINTAINERS] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | arm: at91: pmc: replace the constant with a define in at91_pmc.hErik van Luijk2015-08-211-0/+1
| | | | | | | | | | | | | | | | To enable the clocks on the at91 boards a constant (0x4) is used. This is replaced with a define in at91_pmc.h (1 << 2). Signed-off-by: Erik van Luijk <evanluijk@interact.nl> Reviewed-by: Andreas Bießmann <andreas.devel@googlemail.com>
* | arm: at91: mpddr: allow multiple DDR controllersErik van Luijk2015-08-212-21/+26
|/ | | | | | | | | The mpddr.c depends on ATMEL_BASE_MPDDRC for the base address to configure the controller. This cannot be used when there is more than one controller (i.e. AT91SAM9G45, AT91SAM9M10). Signed-off-by: Erik van Luijk <evanluijk@interact.nl> [remove 'new blank line at EOF'] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* ARM: davinci: remove support for cam_enc_4xxMasahiro Yamada2015-08-201-5/+0
| | | | | | | | | This has not been converted to Generic Board, so should be removed. (See doc/README.generic-board for details.) Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Heiko Schocher <hs@denx.de> Acked-by: Marek Vasut <marex@denx.de>
* Merge git://git.denx.de/u-boot-usbTom Rini2015-08-192-0/+6
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| * usb: spear: Add support for both SPEAr600 EHCI controllersStefan Roese2015-08-192-0/+6
| | | | | | | | | | | | | | | | | | | | | | USB EHCI on SPEAr600 has not been tested for a while. The base controller addresses are missing. This patch adds the defines to the header. And adds the missing code. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Viresh Kumar <viresh.kumar@linaro.org> Cc: Vipin Kumar <vk.vipin@gmail.com> Cc: Marek Vasut <marex@denx.de>
* | ARM: dts: Rename memory@0 to memoryMichal Simek2015-08-194-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | zynq-7000.dtsi include skeleton.dtsi which contains memory node with base address and size zero. If you add memory@0 node to the platform DTS in final DTB there are two memory nodes and U-Boot works with the first one (with zeros) which end up in failing in dram_init because size is zero. Platform memory node should rewrite default memory node setup from skeleton.dtsi that's why platfroms needs to also use memory as node name instead of memory@0. Reported-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | zynqmp: usb: Add usb dwc3 driver support for zynqmpSiva Durga Prasad Paladugu2015-08-192-0/+6
| | | | | | | | | | | | | | | | | | | | Added usb dwc3 driver support for zynqmp this also supports the DFU and LTHOR to download the linux images on to RAM and cen be booted from those linux images. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynq: drop "optional" from board select in favor of ZC702Masahiro Yamada2015-08-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | One disadvantage of commit a26cd04920dc (arch: Make board selection choices optional) is that Kconfig could create such an insane .config file that no board is selected. Rip off the "optional" again in favor of ZC702 as the default target. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | ARM: zynqmp: Add platform specific arch_get_page_tableMichal Simek2015-08-191-0/+5
| | | | | | | | | | | | | | | | | | Based on the patch: "armv8: caches: Added routine to set non cacheable region" (sha1: dad17fd51027ad02ac8f02deed186d08109d61fd) it is necessary to add platform specific hook. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | zynqmp: Enable U-Boot run in EL3Michal Simek2015-08-192-0/+8
|/ | | | | | | Enable Secure IOU setup to enable U-Boot to run in EL3 without setting from ATF. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* of: clean up OF_CONTROL ifdef conditionalsMasahiro Yamada2015-08-189-17/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We have flipped CONFIG_SPL_DISABLE_OF_CONTROL. We have cleansing devices, $(SPL_) and CONFIG_IS_ENABLED(), so we are ready to clear away the ugly logic in include/fdtdec.h: #ifdef CONFIG_OF_CONTROL # if defined(CONFIG_SPL_BUILD) && !defined(SPL_OF_CONTROL) # define OF_CONTROL 0 # else # define OF_CONTROL 1 # endif #else # define OF_CONTROL 0 #endif Now CONFIG_IS_ENABLED(OF_CONTROL) is the substitute. It refers to CONFIG_OF_CONTROL for U-boot proper and CONFIG_SPL_OF_CONTROL for SPL. Also, we no longer have to cancel CONFIG_OF_CONTROL in include/config_uncmd_spl.h and scripts/Makefile.spl. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Linus Walleij <linus.walleij@linaro.org>
* of: flip CONFIG_SPL_DISABLE_OF_CONTROL into CONFIG_SPL_OF_CONTROLMasahiro Yamada2015-08-184-14/+0
| | | | | | | | | | | | | | | | | | | As we discussed a couple of times, negative CONFIG options make our life difficult; CONFIG_SYS_NO_FLASH, CONFIG_SYS_DCACHE_OFF, ... and here is another one. Now, there are three boards enabling OF_CONTROL on SPL: - socfpga_arria5_defconfig - socfpga_cyclone5_defconfig - socfpga_socrates_defconfig This commit adds CONFIG_SPL_OF_CONTROL for them and deletes CONFIG_SPL_DISABLE_OF_CONTROL from the other boards to invert the logic. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* lpc32xx: add common USB OHCI defines for all LPC32xx boardsVladimir Zapolskiy2015-08-181-0/+9
| | | | | | | | The change adds a number of macro definitions used by USB OHCI driver, if CONFIG_USB_OHCI_LPC32XX is selected from a board config file. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
* usb: lpc32xx: add host USB driverSylvain Lemieux2015-08-183-0/+19
| | | | | | | | | | | | | Incorporate USB driver from legacy LPCLinux NXP BSP. The files taken from the legacy patch are: - lpc32xx USB driver - lpc3250 header file USB registers definition. The legacy driver was updated and clean-up as part of the integration with the latest u-boot. Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com> Acked-by: Marek Vasut <marex@denx.de> Tested-by: Vladimir Zapolskiy <vz@mleia.com>
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