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* EXYNOS: EXYNOS4X12: Populate Exynos4x12 register addressesChander Kashyap2012-12-261-6/+42
| | | | | | | This patch populates base addresses of Exynos4x12 registers. Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
*---. Merge samsung, imx, tegra into u-boot-arm/masterAlbert ARIBAUD2012-12-22119-706/+3884
|\ \ \ | | | | | | | | | | | | | | | | | | | | This commit merges branches from samsung, imx and tegra meant to fix merge issues between u-boot/master and u-boot-arm/master, as well as a few manual merge fixes.
| | | * Merge remote-tracking branch 'u-boot/master' into u-boot-arm-mergedAllen Martin2012-12-19113-445/+3766
| | | |\ | |_|/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: README arch/arm/cpu/armv7/exynos/clock.c board/samsung/universal_c210/universal.c drivers/misc/Makefile drivers/power/power_fsl.c include/configs/mx35pdk.h include/configs/mx53loco.h include/configs/seaboard.h
| | | * env: Use getenv_yesno() more generallyJoe Hershberger2012-12-136-20/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the getenv_yesno() to env_common.c and change most checks for 'y' or 'n' to use this helper. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com>
| | | * Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2012-12-121-1/+4
| | | |\
| | | | * mips: serial: Fix busted manual relocationJoe Hershberger2012-12-121-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | serial_initialize() must be called after relocation to adjust the pointers to putc(), getc(), etc. This is busted ever since the serial driver-model-ification series. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| | | | * MIPS: constify mips_io_port_baseDaniel Schwierzeck2012-12-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mips_io_port_base is exported as 'extern const unsigned long mips_io_port_base;' in arch/mips/include/asm/io.h. Thus make the variable const too. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| | | * | Add strcasecmp() and strncasecmp()Simon Glass2012-12-113-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | strncasecmp() is present as strnicmp() but disabled. Make it available and define strcasecmp() also. There is a only a small performance penalty to having strcasecmp() call strncasecmp(), so do this instead of a standalone function, to save code space. Update the prototype in arch-specific headers as needed to avoid warnings. Signed-off-by: Simon Glass <sjg@chromium.org>
| | | * | exynos:pinmux: Add pinmux support for i2cPiotr Wilczek2012-12-111-0/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add pinmux for I2C for Exynos4 Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> CC: Minkyu Kang <mk7.kang@samsung.com>
| | | * | exynos:cpu: Add Exynos4 I2C spacingPiotr Wilczek2012-12-111-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add the spacing for i2c for Exynos4 Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> CC: Minkyu Kang <mk7.kang@samsung.com>
| | | * | exynos:clock: Add i2c clockPiotr Wilczek2012-12-111-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds i2c clock for Exynos4 Signed-off-by: Piotr Wilczek <p.wilczek@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> CC: Minkyu Kang <mk7.kang@samsung.com>
| | | * | mxs: i2c: Implement algorithm to set up arbitrary i2c speedMarek Vasut2012-12-112-0/+3
| | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This algorithm computes the values of TIMING{0,1,2} registers for the MX28 I2C block. This algorithm was derived by using a scope, but the result seems correct. The resulting values programmed into the registers do not correlate with the contents in datasheet. When using the values from the datasheet, the I2C clock were completely wrong. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Wolfgang Denk <wd@denx.de>
| | | * MIPS: constify address pointer in test_bit()Daniel Schwierzeck2012-12-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix several warnings when enabling UBIFS on MIPS: In file included from ubifs.h:2137:0, from ubifs.c:26: misc.h: In function 'ubifs_zn_dirty': misc.h:38:2: warning: passing argument 2 of 'test_bit' discards 'const' qualifier from pointer target type [enabled by default] ../include/asm/bitops.h:569:23: note: expected 'volatile void *' but argument is of type 'const long unsigned int *' Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| | | * MIPS: fix a latent bug on initialize $gpZhi-zhou Zhang2012-12-081-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If bal is 8 bytes aligned, the _gp will not be 8 bytes aligned. then the following ld insntrustion generates a Adel exception. So here make _gp be always aligned in 8 bytes. Signed-off-by: Zhi-zhou Zhang <zhizhou.zh@gmail.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| | * | Merge branch 'master' of git://git.denx.de/u-boot into masterStefano Babic2012-12-0897-419/+3662
| | |\ \ | | | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: drivers/power/power_fsl.c include/configs/mx35pdk.h include/configs/mx53loco.h include/configs/woodburn_common.h board/woodburn/woodburn.c These boards still use the old old PMIC framework, so they do not merge properly after the power framework was merged into mainline. Fix all conflicts and update woodburn to use Power Framework. Signed-off-by: Stefano Babic <sbabic@denx.de>
| | * | mxs: SPL: Generalize memory initializationOtavio Salvador2012-12-071-6/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use a generic 'dram_vals[]' array that has the full initialization sequence and rename the initialization method so it doesn't has a frequency on its name. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
| | * | mxs: Staticize SPL functionsMarek Vasut2012-12-043-34/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MXS SPL didn't mark local functions "static". Fix it. This also makes the SPL smaller by roughly 300 bytes. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
| | * | mxs: Properly setup VDDD in power supply setup codeMarek Vasut2012-12-042-14/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The memory setup code adjusted the VDDD voltage. Remove this adjustment and configure the VDDD voltage correctly in the power supply setup code. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
| | * | mxs: Implement common function to setup VDDxMarek Vasut2012-12-041-170/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement common function to setup the VDDIO, VDDD and VDDA voltage. Right now, there are two almost identical functions to setup VDDIO and VDDD, which is prone to breakage. Pull out the differences into constant structure and pass them as an argument to the common function. Moreover, the function has almost identical loops for setting higher and lower VDDx voltage. Merge these two loops. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
| | * | mx28: Rename regs-power.h to regs-power-mx28.hMarek Vasut2012-12-042-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i.MX23 has different register layout and bit placement in the power supply. Thus, in order to be able to add support for MX23, rename the MX28's regs-power.h to regs-power-mx28.h . Moreover, add ifdef around inclusion of regs-*-mx28.h in imx-regs.h so the MX23 boards will include proper set of registers. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
| | * | mx28: Remove SET, CLR, TOG ops from PLLxCTRL1 registersMarek Vasut2012-12-041-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These registers don't have _SET, _CLR and _TOG at the respective offsets available, these registers has to be toggled via R-M-W if needed. Thus do not export these offsets anymore. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Otavio Salvador <otavio@ossystems.com.br>
| * | | Merge branch 'master' of git://git.denx.de/u-boot into resolveMinkyu Kang2012-12-1097-419/+3662
| |\ \ \ |/ / / / | | | _ | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: README board/samsung/universal_c210/universal.c drivers/misc/Makefile drivers/power/power_fsl.c include/configs/mx35pdk.h include/configs/mx53loco.h include/configs/seaboard.h
| * | x86: Build vga video code only if CONFIG_VIDEO_VGA is definedSimon Glass2012-12-061-2/+2
| | | | | | | | | | | | | | | | | | | | | When running from coreboot we don't want this code, so make it optional. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Remove video_init() prototype from u-boot-x86.hSimon Glass2012-12-061-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | This function is not intended to be exported from the video drivers, so remove the prototype. This fixes an error: cfb_console.c:1793:12: error: static declaration of 'video_init' follows non-static declaration Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: drop unused code in coreboot.cStefan Reinauer2012-12-061-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function setup_pcat_compatibility() is weak and implemented as empty function in board.c hence we don't have to override that with another empty function. monitor_flash_len is unused, drop it. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Remove coreboot_ from file nameStefan Reinauer2012-12-062-2/+1
| | | | | | | | | | | | | | | | | | | | | ... because that information is already "encoded" in the directory name. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Provide a way to throttle port80 accessesVadim Bendebury2012-12-061-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some systems (like Google Link device) provide the ability to keep a history of the target CPU port80 accesses, which is extremely handy for debugging. The problem is that the EC handling port 80 access is orders of magnitude slower than the AP. This causes random loss of trace data. This change allows to throttle port 80 accesses such that in case the AP is trying to post faster than the EC can handle, a delay is introduced to make sure that the post rate is throttled. Experiments have shown that on Link the delay should be at least 350,000 of tsc clocks. Throttling is not being enabled by default: to enable it one would have to set MIN_PORT80_KCLOCKS_DELAY to something like 400 and rebuild the u-boot image. With upcoming EC code optimizations this number could be decreased (new new value should be established experimentally). Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Provide tick counter and frequency reference for Intel core architectureVadim Bendebury2012-12-061-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some u-boot modules rely on availability of get_ticks() and get_tbclk() functions, reporting a free running clock and its frequency respectively. Traditionally these functions return number and frequency of timer interrupts. Intel's core architecture processors however are known to run the rdtsc instruction at a constant rate of the so called 'Max Non Turbo ratio' times the external clock frequency which is 100MHz. This is just as good for the timer tick functions in question. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Issue SMI to finalize Coreboot in final stageDuncan Laurie2012-12-061-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | This will write magic value to APMC command port which will trigger an SMI and cause coreboot to lock down the ME, chipset, and CPU. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Fix MTRR clear to detect which MTRR to useDuncan Laurie2012-12-061-4/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Coreboot was always using MTRR 7 for the write-protect cache entry that covers the ROM and U-boot was removing it. However with 4GB configs we need more MTRRs for the BIOS and so the WP MTRR needs to move. Instead coreboot will always use the last available MTRR that is normally set aside for OS use and U-boot can clear it before the OS. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Emit port 80 post codes in show_boot_progress()Stefan Reinauer2012-12-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | This helps us monitor boot progress and determine where U-Boot dies if there are any problems. Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: fdt: Create basic .dtsi file for corebootSimon Glass2012-12-062-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | This contains just the minimum information for a coreboot-based board. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: coreboot: Set CONFIG_ARCH_DEVICE_TREE correctlyGabe Black2012-12-061-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | We will use coreboot.dtsi as our fdt include file. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Add support for CONFIG_OF_CONTROLGabe Black2012-12-062-0/+36
| | | | | | | | | | | | | | | | | | | | | Allow a device tree to be provided through the standard mechanisms. Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Add CONFIG_DELAY_ENVIRONMENT to delay environment loadingStefan Reinauer2012-12-061-1/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This option delays loading of the environment until later, so that only the default environment will be available to U-Boot. This can address the security risk of untrusted data being used during boot. When CONFIG_DELAY_ENVIRONMENT is defined, it is convenient to have a run-time way of enabling loadinlg of the environment. Add this to the fdt as /config/delay-environment. Note: This patch depends on http://patchwork.ozlabs.org/patch/194342/ Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
| * | x86: Add back cold- and warm-boot flagsGabe Black2012-12-063-1/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These were removed, but actually are useful. Cold means that we started from a reset/power on. Warm means that we started from another U-Boot. We determine whether u-boot on x86 was warm or cold booted (really if it started at the beginning of the text segment or at the ELF entry point). We plumb the result through to the global data structure. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Override calculate_relocation_address to use the e820 mapGabe Black2012-12-061-6/+55
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because calculate_relocation_address now uses the e820 map, it will be able to avoid addresses over 32 bits and regions that are at high addresses but not big enough for U-Boot. It also means we can remove the hack which limitted U-Boot's idea of the size of memory to less than 4GB. Also take into account the space needed for the heap and stack, so we avoid picking a very small region those areas might overlap with something it shouldn't. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Make calculate_relocation_address an overridable functionGabe Black2012-12-061-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Different systems may have different mechanisms for picking a suitable place to relocate U-Boot to. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Make the upper bound on relocated symbols closed instead of openGabe Black2012-12-061-1/+1
| | | | | | | | | | | | | | | | | | This seems to be a bug. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Reorder x86's post relocation memory layoutGabe Black2012-12-061-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This changes the layout in decreasing addresses from: 1. Stack 2. Sections in the image 3. Heap to 1. Sections in the image 2. Heap 3. Stack This allows the stack to grow significantly more since it isn't constrained by the other u-boot areas. More importantly, the generic memory wipe code assumes that the stack is the lowest addressed area used by the main part of u-boot. In the original layout, that means that u-boot tramples all over itself. In the new layout, it works. Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Initialise SPI if enabledGabe Black2012-12-063-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | If we have SPI support, make sure that we init it. Signed-off-by: Gabe Black <gabeblack@google.com> Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Vic Yang <victoryang@chromium.org>
| * | x86: Implement arch_phys_memset so that it can wipe memory above 4GBGabe Black2012-12-062-0/+229
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement arch_phys_memset so that it can set memory at physical addresses above 4GB using PAE paging. Because there are only 5 page tables in PAE mode, 1 PDPT and 4 PDTs, those tables are statically allocated in the BSS. The tables must be 4K page aligned and are declared that way, and because U-Boot starts as 4K aligned and the relocation code relocates it to a 4K aligned address, the tables work as intended. While paging is turned on, all 4GB are identity mapped except for one 2MB page which is used as the window into high memory. This way, U-Boot will continue to work as expected when running code that expects to access memory freely, but the code can still get at high memory through its window. The window is put at 2MB so that it's 2MB page aligned, low in memory to be out of the way of things U-Boot is likely to care about, and above the lowest 1MB where lots of random things live. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Increase the size of the phys_size_t and phys_addr_t typesGabe Black2012-12-062-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | These types should be 64 bits long to reflect the fact that physical addresses and the size of physical areas of memory are more than 32 bits long. Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Fix off-by-one error in do_elf_reloc_fixups()Duncan Laurie2012-12-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The use of post-increment with a do-while loop results in the loop going one step too far when handling relocation fixups. In about 1/100 cases this would cause it to hang. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Ignore memory >4GB when parsing Coreboot tablesDuncan Laurie2012-12-061-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | U-boot is unable to actually use that memory and it can cause problems with relocation if it tries to. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Fix indirect jmp warning in zimage.cSimon Glass2012-12-061-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes the following warning: zimage.c:312: Warning: indirect jmp without `*' Also fixed these warnings to keep checkpatch quiet: warning: arch/x86/lib/zimage.c,311: unnecessary whitespace before a quoted newline warning: arch/x86/lib/zimage.c,312: unnecessary whitespace before a quoted newline warning: arch/x86/lib/zimage.c,313: unnecessary whitespace before a quoted newline Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Clean up MTRR 7 right before jumping to the kernelStefan Reinauer2012-12-061-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | This cleans up the rom caching optimization implemented in coreboot (and needed throughout U-Boot runtime). Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Import MSR/MTRR code from LinuxGraeme Russ2012-12-063-0/+913
| | | | | | | | | | | | | | | | | | Imported from Linux 3.1 with a few modifications to suit U-Boot Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Provide a function to clean up just before booting a zimageStefan Reinauer2012-12-061-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | This function can be used by boards which want to do some clean-up before booting a zImage. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Add basic cache operationsStefan Reinauer2012-12-064-72/+155
| | | | | | | | | | | | | | | | | | | | | Add functions to enable/disable the data cache. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
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