summaryrefslogtreecommitdiffstats
path: root/arch
Commit message (Collapse)AuthorAgeFilesLines
...
| * | tegra: Boot in non-secure mode by defaultJan Kiszka2015-05-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Upstream Linux is broken with default configs when PSCI, thus non-secure mode is enabled. So the user should explicitly enable this mode, e.g. when she disabled CONFIG_CPU_IDLE in Linux (in which case it's safe to use). We can revert this workaround once Linux got fixed. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: tegra: Enable SMMU when going non-secureThierry Reding2015-05-132-0/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make sure to enable the SMMU when booting the kernel in non-secure mode. This is necessary because some of the SMMU registers are restricted to TrustZone-secured requestors, hence the kernel wouldn't be able to turn the SMMU on. At the same time, enable translation for all memory clients for the same reasons. The kernel will still be able to control SMMU IOVA translation using the per-SWGROUP enable bits. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra: Set CNTFRQ for secondary CPUsJan Kiszka2015-05-131-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We only set CNTFRQ in arch_timer_init for the boot CPU. But this has to happen for all cores. Fixing this resolves problems of KVM with emulating the generic timer/counter. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0Ian Campbell2015-05-133-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These registers can be used to prevent non-secure world from accessing a megabyte aligned region of RAM, use them to protect the u-boot secure monitor code. At first I tried to do this from s_init(), however this inexplicably causes u-boot's networking (e.g. DHCP) to fail, while networking under Linux was fine. So instead I have added a new weak arch function protect_secure_section() called from relocate_secure_section() and reserved the region there. This is better overall since it defers the reservation until after the sec vs. non-sec decision (which can be influenced by an envvar) has been made when booting the os. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> [Jan: tiny style adjustment] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra124: Add PSCI support for Tegra124Jan Kiszka2015-05-135-0/+174
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is based on Thierry Reding's work and uses Ian Campell's preparatory patches. It comes with full support for CPU_ON/OFF PSCI services. The algorithm used in this version for turning CPUs on and off was proposed by Peter De Schrijver and Thierry Reding in http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/210881. It consists of first enabling CPU1..3 via the PMC, just to powergate them again with the help of the Flow Controller. Once the Flow Controller is in place, we can leave the PMC alone while processing CPU_ON and CPU_OFF PSCI requests. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: Add board-specific initialization hook for PSCIJan Kiszka2015-05-132-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | Tegra boards will have to initialize power management for the PSCI support this way. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra: Make tegra_powergate_power_on publicJan Kiszka2015-05-132-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Will be used for unpowergating CPUs. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | virt-dt: Allow reservation of secure region when in a RAM carveoutJan Kiszka2015-05-133-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In this case the secure code lives in RAM, and hence the memory node in the device tree needs to be adjusted. This avoids that the OS will map and possibly access the reservation. Add support for setting CONFIG_ARMV7_SECURE_RESERVE_SIZE to carve out such a region. We only support cutting off memory from the beginning or the end of a RAM bank as we do not want to increase their number (which would happen if punching a hole) for simplicity reasons This will be used in a subsequent patch for Jetson-TK1. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra124: Add more registers to struct mc_ctlrIan Campbell2015-05-131-2/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I will need mc_security_cfg0/1 in a future patch and I added the rest while debugging, so thought I might as well commit them. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: Put target PC for PSCI CPU_ON on per-CPU stackJan Kiszka2015-05-132-9/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use a per-CPU variable for saving the target PC during CPU_ON operations. This allows us to run this service independently on targets that have more than 2 cores and also core-local power control. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: Factor out reusable psci_get_cpu_stack_topJan Kiszka2015-05-132-10/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This algorithm will be useful on Tegra as well, plus we will need it for making _psci_target_pc per-CPU. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: Factor out reusable psci_cpu_entryJan Kiszka2015-05-132-18/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | _sunxi_cpu_entry can be converted completely into a reusable psci_cpu_entry. Tegra124 will use it as well. As with psci_disable_smp, also the enabling is designed to be overloaded in cased SMP is not controlled via ACTLR. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: Factor out reusable psci_cpu_off_commonJan Kiszka2015-05-132-62/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move parts of sunxi's psci_cpu_off into psci_cpu_off_common, namely cache disabling and flushing, clrex and the disabling of SMP for the dying CPU. These steps are apparently generic for ARMv7 and will be reused for Tegra124 support. As the way of disabled SMP is not architectural, though commonly done via ACLTR, the related function can be overloaded. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: Factor out common psci_get_cpu_idJan Kiszka2015-05-132-5/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Will be required for obtaining the ID of the current CPU in shared PSCI functions. The default implementation requires a dense ID space and only supports a single cluster. Therefore, the functions can be overloaded in cases where these assumptions do not hold. CC: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Acked-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | ARM: Clean up CONFIG_ARMV7_NONSEC/VIRT/PSCI conditionsJan Kiszka2015-05-137-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_ARMV7_VIRT depends on CONFIG_ARMV7_NONSEC, thus doesn't need to be taken into account additionally. CONFIG_ARMV7_PSCI is only set on boards that support CONFIG_ARMV7_NONSEC, and it only works on those. CC: Tang Yuantian <Yuantian.Tang@freescale.com> CC: York Sun <yorksun@freescale.com> CC: Steve Rae <srae@broadcom.com> CC: Andre Przywara <andre.przywara@linaro.org> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Tested-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra124: video: Add full link training for eDPSimon Glass2015-05-131-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add full link training as a fallback in case the fast link training fails. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra: video: support eDP displays on Tegra124 devicesSimon Glass2015-05-131-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | Connect up the clocks and the eDP driver to make these displays work with Tegra124-based devices. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra: dts: nyan-big: Add definitions for eDP displaySimon Glass2015-05-131-0/+43
| | | | | | | | | | | | | | | | | | | | | Add the various host1x peripherals to allow an eDP display to be connected. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra: Move display controller header into commonSimon Glass2015-05-133-12/+55
| | | | | | | | | | | | | | | | | | | | | Allow this to be used by other Tegra SoCs. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra124: clock: Add display clocks and functionsSimon Glass2015-05-135-9/+173
| | | | | | | | | | | | | | | | | | | | | | | | Add functions to provide access to the display clocks on Tegra124 including setting the clock rate for an EDP display. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra: clock: Split the clock source code into a separate functionSimon Glass2015-05-132-22/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | Create a function which sets the source clock for a peripheral, given the number of mux bits to adjust. This can then be used more generally. For now, don't export it. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra: clock: Add checking for invalid clock IDsSimon Glass2015-05-132-4/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | The get_pll() function can do the wrong thing if passed values that are out of range. Add checks for this and add a function which can return a 'simple' PLL. This can be defined by SoCs with their own clocks. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra124: dts: Add host1x node to provide display informationSimon Glass2015-05-131-0/+84
| | | | | | | | | | | | | | | | | | | | | | | | This peripheral is required to get the LCD display running. Add it to tegra124 and also bring in the binding file from Linux 3.18 Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra: nyan-big: Add LCD PMIC init and board IDSimon Glass2015-05-131-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Add required setup for the LCD display, and a function to provide the board ID. This requires GPIOs to be available prior to relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra: Provide a function to allow LCD PMIC setupSimon Glass2015-05-131-0/+8
| | | | | | | | | | | | | | | | | | | | | Some LCDs require a PMIC to be set up - add a function for this. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra: Add a board ID functionSimon Glass2015-05-131-5/+6
| | | | | | | | | | | | | | | | | | | | | Add a way of displaying a numeric board ID on start-up. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra: Move checkboard() into the board codeSimon Glass2015-05-131-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | This is only used by Nvidia boards, so move it into nvidia/common to simplify things. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra: pwm: Allow the clock rate to be left as isSimon Glass2015-05-132-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | When enabling a PWM, allow the existing clock rate and source to stand unchanged. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
| * | tegra: Move the pwm into tegra-commonSimon Glass2015-05-136-52/+80
| | | | | | | | | | | | | | | | | | | | | | | | This is needed for tegra124 also, so make it common and add a header file for tegra124. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-arcTom Rini2015-05-142-10/+2
|\ \ \
| * | | arc: remove dummy targetAlexey Brodkin2015-05-131-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TARGET_DUMMY was introduced to resolve the same problem as commit "arch: Make board selection choices optional" http://git.denx.de/?p=u-boot.git;a=commit;h=a26cd04920dc069fd6e91abb785426cf6c29f45f Latter implementation is much cleaner and appropriate. And anyways TARGET_DUMMY is no longer required. Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | | arc: use more universal prefix for default CROSS_COMPILEMasahiro Yamada2015-05-131-2/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As doc/README.ARC says, pre-build ARC toolchains are available at the Synopsys GitHub page. The bin files are prefixed with arc(eb)-buildroot-linux- for earlier releases, but with arc(eb)-snps-linux- for the latest releases. The symbolic links prefixed with arc(eb)-linux- are also available for all the release, so those prefixes can be used as the default CROSS_COMPILE regardless of the toolchains version/variants. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | ARM: at91: remove non-generic boardsMasahiro Yamada2015-05-132-16/+1
|/ / | | | | | | | | | | | | | | | | | | | | | | Remove board support for afeb9260, tny_a9260, and sbc35_a9g20. They have not been converted into Generic Board yet. See doc/README.generic-board for details. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Sergey Lapin <slapin@ossfans.org> Cc: Albin Tonnerre <albin.tonnerre@free-electrons.com> Cc: Andreas Bießmann <andreas.devel@googlemail.com>
* | arch: Make board selection choices optionalJoe Hershberger2015-05-1246-0/+47
| | | | | | | | | | | | | | | | | | | | | | | | By making the board selections optional, every defconfig will include the board selection when running savedefconfig so if a new board is added to the top of the list of choices the former top's defconfig will still be correct. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Cc: Tom Rini <trini@konsulko.com>
* | ppc4xx: Remove sc3 boardStefan Roese2015-05-103-13/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As this board seems to be unmaintained for quite some time, and its not moved to the generic board ingrastructure, lets remove it. This will also enable us to remove the CONFIG_AUTOBOOT_DELAY_STR2 and CONFIG_AUTOBOOT_STOP_STR2 macros, as this sc3 board is the only one using one of this macros. A removal patch will follow soon. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Wolfgang Denk <wd@denx.de> Cc: Juergen Beisert <jbeisert@eurodsn.de> Acked-by: Heiko Schocher <hs@denx.de>
* | stv0991: fdt: add stv0991 device treeVikas Manocha2015-05-102-0/+24
| | | | | | | | | | | | | | | | | | This patch adds device tree for the ST Micro stv0991 board & enables device tree control. Progressively device tree support for the drivers being used will also be added. Signed-off-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | stm32f4: add serial print portkunhuahuang2015-05-101-0/+32
| | | | | | | | | | | | | | | | | | | | | | | | Add the stm32F4 board's serial ports support. User can use it easily. The user only need to edit the number of the usart. The patch also fix the serial print out. Last, this version of patch fix the first patch checkpatch.pl error. Thanks to Kamil Lulko. Signed-off-by: kunhuahuang <huangkunhua@gmail.com>
* | Merge git://git.denx.de/u-boot-dmTom Rini2015-05-088-9/+116
|\ \
| * | sandbox: Don't try distro_bootcmd by defaultSjoerd Simons2015-05-062-3/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the distro_bootcmds to succeed on the sandbox a bit of setup is required (e.g. network configured or host image bound), so running them by default isn't that useful. Add a -b/--boot command to the sandbox binary, which triggers the distro_bootcmds to run after the other command-line commands. Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk> Acked-by: Simon Glass <sjg@chromium.org>
| * | dm: sandbox: dts: Add a real-time clock attached to I2CSimon Glass2015-05-051-1/+11
| | | | | | | | | | | | | | | | | | | | | Add an emulated RTC device for sandbox, so that the 'date' command can be used. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: rtc: sandbox: Add an emulated I2C RTC deviceSimon Glass2015-05-052-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a sandbox I2C emulation device which emulates a real-time clock. The clock works off an offset from the current system time, and supports setting and getting the clock, as well as access to byte-width regisers in the RTC. It does not support changing the system time. This device can be used for testing the 'date' command on sandbox, as well as the RTC uclass. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: sandbox: Add os_localtime() to obtain the system timeSimon Glass2015-05-051-0/+18
| | | | | | | | | | | | | | | | | | Add a function to read the system time into U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: i2c: Add an explicit test mode to the sandbox I2C driverSimon Glass2015-05-051-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | At present this driver has a few test features. They are needed for running the driver model unit tests but are confusing and unnecessary if using sandbox at the command line. Add a flag to enable the test mode, and don't enable it by default. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | sandbox: eth: Add a function to skip ping timeoutsJoe Hershberger2015-05-051-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | When called, the next call to receive will trigger a 10-second leap forward in time to avoid waiting for time to pass when tests are evaluating timeout behavior. Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
| * | sandbox: Add test function to advance timeJoe Hershberger2015-05-052-5/+8
| |/ | | | | | | | | | | | | | | | | | | Add a function that maintains an offset to include in the system timer values returned from the lib/time.c APIs. This will allow timeouts to be skipped instantly in tests Signed-off-by: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Simon Glass <sjg@chromium.org>
* | ARM: socfpga: abolish CONFIG_SOCFPGAMasahiro Yamada2015-05-072-2/+2
| | | | | | | | | | | | Replace CONFIG_SOCFPGA with CONFIG_ARCH_SOCFPGA. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: socfpga: move SoC headers to mach-socfpga/include/machMasahiro Yamada2015-05-0713-0/+0
| | | | | | | | | | | | Move headers to mach-socfpga as well. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: socfpga: move SoC sources to mach-socfpgaMasahiro Yamada2015-05-0713-1/+1
| | | | | | | | | | | | Our recent trend is to collect SoC files into arch/arm/mach-(SOC). Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: socfpga: move board select into mach-socfpga/KconfigMasahiro Yamada2015-05-072-11/+31
| | | | | | | | | | | | | | | | | | | | Switch to a more standard way of board select; put the SoC select into arch/arm/Kconfig and move the board select menu under arch/arm/mach-socfpga/Kconfig. Also, consolidate SYS_BOARD, SYS_VENDOR, SYS_SOC, SYS_CONFIG_NAME. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ARM: socfpga: remove redundant config.mkMasahiro Yamada2015-05-071-8/+0
| | | | | | | | | | | | | | | | Because all the SOCFPGA boards define CONFIG_SPL_FRAMEWORK (see include/configs/socfpga_common.h), u-boot.img is automatically added to the target image list by the top Makefile. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
OpenPOWER on IntegriCloud