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* x86: Add some more common MSR indexesSimon Glass2016-03-173-20/+43
| | | | | | | | | Many of the model-specific indexes are common to several Intel CPUs. Add some more common ones, and remove them from the ivybridge-specific header file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: cpu: Make the vendor table constSimon Glass2016-03-171-1/+1
| | | | | | | This does not need to be modified at run-time, so make it const. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Support booting SeaBIOSBin Meng2016-03-173-0/+28
| | | | | | | | | | | | | | | SeaBIOS is an open source implementation of a 16-bit x86 BIOS. It can run in an emulator or natively on x86 hardware with the use of coreboot. With SeaBIOS's help, we can boot some OSes that require 16-bit BIOS services like Windows/DOS. As U-Boot, we have to manually create a table where SeaBIOS gets system information (eg: E820) from. The table unfortunately has to follow the coreboot table format as SeaBIOS currently supports booting as a coreboot payload. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Implement functions for writing coreboot tableBin Meng2016-03-173-0/+147
| | | | | | | | To prepare generating coreboot table from U-Boot, implement functions to handle the writing. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Support writing configuration tables in high areaBin Meng2016-03-171-0/+11
| | | | | | | | | | For those secondary bootloaders like SeaBIOS who want to live in the F segment, which conflicts the configuration table address, now we allow write_tables() to write the configuration tables in high area (malloc'ed memory). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Simplify codes in write_tables()Bin Meng2016-03-171-27/+34
| | | | | | | | Given all table write routines have the same signature, we can simplify the codes by using a function table. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Change write_acpi_tables() signature a little bitBin Meng2016-03-173-6/+5
| | | | | | | | Change the parameter and return value of write_acpi_tables() to u32 to conform with other table write routines. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Use a macro for ROM table alignmentBin Meng2016-03-172-5/+7
| | | | | | | Define ROM_TABLE_ALIGN instead of using 1024 directly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Change to use start/end address pair in write_tables()Bin Meng2016-03-171-6/+12
| | | | | | | | Add a new variable rom_table_start and pass it to ROM table write routines. This reads better than previous single rom_table_end. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Clean up coreboot_tables.hBin Meng2016-03-171-73/+80
| | | | | | | | | Clean up this file a little bit: - Remove inclusion of <linux/compiler.h> - Use tab in the macro definition Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Move sysinfo related to sysinfo.hBin Meng2016-03-172-4/+2
| | | | | | | | coreboot_tables.h should not include sysinfo related stuff. Move those to asm/arch-coreboot/sysinfo.h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: Move asm/arch-coreboot/tables.h to a common placeBin Meng2016-03-174-3/+1
| | | | | | | | Move asm/arch-coreboot/tables.h to asm/coreboot_tables.h so that coreboot table definitions can be used by other x86 builds. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* spl: arm: Make sure to include all of the u_boot_list entriesTom Rini2016-03-165-15/+9
| | | | | | | | | | | | | | Starting with 96e5b03 we use a linker list for partition table information. However since we use this in SPL we need to make sure that the SPL linker scripts include these as well. While doing this, it's best to simply include all linker lists to future proof ourselves. Cc: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reported-by: Nishanth Menon <nm@ti.com> Tested-by: Nishanth Menon <nm@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* arm: omap-common: Guard some parts of the code with CONFIG_OMAP44XX/OMAP54XXTom Rini2016-03-161-1/+7
| | | | | | | | | | On OMAP4 platforms that also need to calculate their DDR settings we are now getting very close to the linker limit size. Since OMAP44XX is only seen with LPDDR2, remove some run time tests for LPDDR2 or DDR3 as we will know that we don't have it for OMAP44XX. Cc: Nishanth Menon <nm@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* ARM: keystone2: Only link cmd_ddr3.o on non-SPL buildsTom Rini2016-03-161-1/+2
| | | | | | | | | | | | When we switch to including all linker lists in SPL it is important to not include commands as that may lead to link errors due to other things we have already discarded. In this case simply move cmd_ddr3.o over to the list with the rest. Cc: Vitaly Andrianov <vitalya@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* ARM: keystone2: Switch to using the poweroff commandTom Rini2016-03-164-29/+30
| | | | | | | | | | Now that we have a standard way to power off the hardware, switch to using that rather than our own command. Cc: Vitaly Andrianov <vitalya@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* ARM: keystone2: Split monitor code / command codeTom Rini2016-03-164-52/+71
| | | | | | | | | | | | When we switch to including all linker lists in SPL it is important to not include commands as that may lead to link errors due to other things we have already discarded. In this case, we split the code for supporting the monitor out from the code for loading it. Cc: Vitaly Andrianov <vitalya@ti.com> Cc: Nishanth Menon <nm@ti.com> Cc: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7: DDR: Enable SR in Power Management ControlNishanth Menon2016-03-151-3/+3
| | | | | | | | | | | | | | If EMIF is idle for certain amount of DDR cycles, EMIF will put the DDR in self refresh mode to save power if EMIF_PWR_MGMT_CTRL register is programmed. And also before entering suspend-resume ddr needs to be put in self-refresh. Linux kernel does not program this register before entering suspend and relies on u-boot setting. So configuring it in u-boot. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Tested-by: Tom Rini <trini@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: Allow EFI payload code to take exceptionsAlexander Graf2016-03-151-0/+8
| | | | | | | | | | | | | | | There are 2 ways an EFI payload could return into u-boot: - Callback function - Exception While in EFI payload mode, r9 is owned by the payload and may not contain a valid pointer to gd, so we need to fix it up. We do that properly for the payload to callback path already. This patch also adds gd pointer restoral for the exception path. Signed-off-by: Alexander Graf <agraf@suse.de>
* arm64: Allow EFI payload code to take exceptionsAlexander Graf2016-03-151-0/+9
| | | | | | | | | | | | | | | There are 2 ways an EFI payload could return into u-boot: - Callback function - Exception While in EFI payload mode, x18 is owned by the payload and may not contain a valid pointer to gd, so we need to fix it up. We do that properly for the payload to callback path already. This patch also adds gd pointer restoral for the exception path. Signed-off-by: Alexander Graf <agraf@suse.de>
* arm64: Allow exceptions to returnAlexander Graf2016-03-151-0/+34
| | | | | | | | | | | | | | Our current arm64 exception handlers all panic and never return to the exception triggering code. But if any handler wanted to continue execution after fixups, it would need help from the exception handling code to restore all registers. This patch implements that help. With this code, exception handlers on aarch64 can successfully return to the place the exception happened (or somewhere else if they modify elr). Signed-off-by: Alexander Graf <agraf@suse.de>
* efi_loader: Add runtime servicesAlexander Graf2016-03-154-0/+54
| | | | | | | | | | | | | | | | | After booting has finished, EFI allows firmware to still interact with the OS using the "runtime services". These callbacks live in a separate address space, since they are available long after U-Boot has been overwritten by the OS. This patch adds enough framework for arbitrary code inside of U-Boot to become a runtime service with the right section attributes set. For now, we don't make use of it yet though. We could maybe in the future map U-boot environment variables to EFI variables here. Signed-off-by: Alexander Graf <agraf@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
* arm64: Only allow dcache disabled in SPL buildsAlexander Graf2016-03-151-0/+9
| | | | | | | | | Now that we have an easy way to describe memory regions and enable the MMU, there really shouldn't be anything holding people back from running with caches enabled on AArch64. To make sure people catch early if they're missing on the caching fun, give them a compile error. Signed-off-by: Alexander Graf <agraf@suse.de>
* arm64: Remove non-full-va map codeAlexander Graf2016-03-156-216/+85
| | | | | | | | | | | By now the code to only have a single page table level with 64k page size and 42 bit address space is no longer used by any board in tree, so we can safely remove it. To clean up code, move the layerscape mmu code to the new defines, removing redundant field definitions. Signed-off-by: Alexander Graf <agraf@suse.de>
* tegra: Replace home grown mmu code with generic table approachAlexander Graf2016-03-151-115/+17
| | | | | | | Now that we have nice table driven page table creating code that gives us everything we need, move to that. Signed-off-by: Alexander Graf <agraf@suse.de>
* zymqmp: Replace home grown mmu code with generic table approachAlexander Graf2016-03-151-169/+48
| | | | | | | Now that we have nice table driven page table creating code that gives us everything we need, move to that. Signed-off-by: Alexander Graf <agraf@suse.de>
* thunderx: Move mmu table into board fileAlexander Graf2016-03-152-5/+5
| | | | | | | | | The MMU range table can vary depending on things we may only find out at runtime. While the very simple ThunderX variant does not change, other boards will, so move the definition from a static entry in a header file to the board file. Signed-off-by: Alexander Graf <agraf@suse.de>
* arm64: Make full va map code more dynamicAlexander Graf2016-03-155-100/+494
| | | | | | | | | | | | | | | | | | | The idea to generate our pages tables from an array of memory ranges is very sound. However, instead of hard coding the code to create up to 2 levels of 64k granule page tables, we really should just create normal 4k page tables that allow us to set caching attributes on 2M or 4k level later on. So this patch moves the full_va mapping code to 4k page size and makes it fully flexible to dynamically create as many levels as necessary for a map (including dynamic 1G/2M pages). It also adds support to dynamically split a large map into smaller ones when some code wants to set dcache attributes. With all this in place, there is very little reason to create your own page tables in board specific files. Signed-off-by: Alexander Graf <agraf@suse.de>
* arm64: Disable TTBR1 maps in EL1Alexander Graf2016-03-152-1/+2
| | | | | | | | | | | | When running in EL1, AArch64 knows two page table maps. One with addresses that start with all zeros (TTBR0) and one with addresses that start with all ones (TTBR1). In U-Boot we don't care about the high up maps, so just disable them to ensure we don't walk an invalid page table by accident. Reported-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
* thunderx: Calculate TCR dynamicallyAlexander Graf2016-03-152-6/+59
| | | | | | | | Based on the memory map we can determine a lot of hard coded fields of TCR, like the maximum VA and max PA we want to support. Calculate those dynamically to reduce the chance for pit falls. Signed-off-by: Alexander Graf <agraf@suse.de>
* omap4: Check warm reset for reboot mode validityPaul Kocialkowski2016-03-151-0/+4
| | | | | | | Since the SAR registers are filled with garbage on cold reset, this checks for a warm reset to assert the validity of reboot mode. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap4: Reboot mode supportPaul Kocialkowski2016-03-152-0/+49
| | | | | | | | | | Reboot mode is written to SAR memory before reboot in the form of a string. This mechanism is supported on OMAP4 by various TI kernels. It is up to each board to make use of this mechanism or not. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap4: Properly enable USB PHY clocksPaul Kocialkowski2016-03-153-1/+9
| | | | | | | This correctly enables the USB PHY clocks, by enabling CM_ALWON_USBPHY_CLKCTRL and correctly setting CM_L3INIT_USBPHY_CLKCTRL's value. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap-common: clocks-common: Setup USB DPLL when MUSB is in usePaul Kocialkowski2016-03-151-2/+4
| | | | | | | | On (at least) OMAP4, the USB DPLL is required to be setup for the internal PHY to work properly. The internal PHY is used by default with the MUSB USB OTG controller. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* Amazon Kindle Fire (first generation) codename kc1 supportPaul Kocialkowski2016-03-151-0/+4
| | | | | | | | | | The Amazon Kindle Fire (first generation) codename kc1 is a tablet that was released by Amazon back in 2011. It is using an OMAP4430 SoC GP version, which allows running U-Boot and the U-Boot SPL from the ground up. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap4: Move i2c clocks enable to enable_basic_clocksPaul Kocialkowski2016-03-151-4/+4
| | | | | | | I2C is often enabled withing the U-Boot SPL, thus those clocks are required to be enabled early (especially when the bootrom doesn't enable them for us). Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap4: Remove duplicate CM_L3INIT_USBPHY_CLKCTRL reference and whitespacePaul Kocialkowski2016-03-151-2/+1
| | | | | | | This removes a duplicate reference to CM_L3INIT_USBPHY_CLKCTRLin enable_basic_uboot_clocks. Also, a doubled whitespace is removed. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap-common: Remove deprecated arch_cpu_init codePaul Kocialkowski2016-03-151-13/+0
| | | | | | | save_omap_boot_params is called from spl_board_init in the SPL context. Thus, there is no reason to duplicate that call on arch_cpu_init. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap-common: Rename set_muxconf_regs_essential to set_muxconf_regsPaul Kocialkowski2016-03-153-4/+4
| | | | | | | There is no distinction between essential and non-essential mux configuration, so it doesn't make sense to have an "essential" prefix. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap4: Export jedec sdram timingsPaul Kocialkowski2016-03-152-2/+4
| | | | | | | Individual boards might provide their own emif_get_device_timings function and use the jedec timings in their own way, hence those have to be exported. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap4: Export elpidia sdram timingsPaul Kocialkowski2016-03-152-1/+6
| | | | | | | Individual boards might provide their own emif_get_device_timings function and use the elpidia timings in their own way, hence those have to be exported. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap4: Export elpidia sdram device detailsPaul Kocialkowski2016-03-152-2/+7
| | | | | | | | | Individual boards might provide their own emif_get_device_details function and use elpidia device details in their own way, hence those have to be exported. This also wraps existing definitions with the proper ifdef logic. Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
* omap3: Use a define for reboot reason offsetPaul Kocialkowski2016-03-152-3/+7
| | | | | | | | This introduces a define for the offset to the reboot reason, rather than hardcoding it. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* omap3: String-based reboot mode handlingPaul Kocialkowski2016-03-152-6/+12
| | | | | | | | This switches reboot mode handling to a string-based interface, that allows more flexibility to set a common interface with the next generations of OMAP devices. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://git.denx.de/u-boot-videoTom Rini2016-03-154-2/+156
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| * imx: mx6: hdmi: handle overflow conditionPeng Fan2016-03-141-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | If HDMI_IH_FC_STAT2_OVERFLOW_MASK is set, we need to do TMDS software reset and write to clear fc_invidconf register. We need minimum 3 times to write to clear the fc_invidconf register, so choose 5 loops here. Signed-off-by: Peng Fan <van.freenix@gmail.com> Signed-off-by: Sandor Yu <sandor.yu@nxp.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@nxp.com>
| * rockchip: video: Add LVDS support in vop driverJacob Chen2016-03-141-0/+1
| | | | | | | | | | | | | | | | | | | | LVDS have a different display out mode, add code to get right flag. The vop_ip decide display device and the remote_vop_id decide which vop was being used. So we should use the remote_vop_id to set DCLK_VOP. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: dts: Add LVDS supportJacob Chen2016-03-141-1/+46
| | | | | | | | | | | | | | Add these node to be used in rockchip LVDS and VOP driver. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Acked-by: Simon Glass <sjg@chromium.org>
| * rockchip: video: Add a display driver for rockchip LVDSJacob Chen2016-03-141-0/+97
| | | | | | | | | | | | | | | | Some Rockchip SoCs support LVDS output. Add a display driver for this so that these displays can be used on supported boards. Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge git://git.denx.de/u-boot-dmTom Rini2016-03-148-24/+14
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