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* x86: Move VGA option rom macros to KconfigBin Meng2015-07-141-0/+22
| | | | | | | | | | Move X86_OPTION_ROM_FILE & X86_OPTION_ROM_ADDR to arch/x86/Kconfig and rename them to VGA_BIOS_FILE & VGA_BIOS_ADDR which depend on HAVE_VGA_BIOS. The new names are consistent with other x86 binary blob options like HAVE_FSP/FSP_FILE/FSP_ADDR. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: cmd_mtrr: Improve MTRR list informationBin Meng2015-07-141-1/+2
| | | | | | | | Print the meaningful base address and mask of an MTRR range without showing the memory type encoding or valid bit. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: queensbay: Change CPU_ADDR_BITS to 32Bin Meng2015-07-141-0/+4
| | | | | | | | | Per CPUID:80000008h result, the maximum physical address bits of TunnelCreek processor is 32 instead of default 36. This will fix the incorrect decoding of MTRR range mask. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Setup fixed range MTRRs for legacy regionsBin Meng2015-07-142-11/+38
| | | | | | | | | We should setup fixed range MTRRs for some legacy regions like VGA RAM and PCI ROM areas as uncacheable. Note FSP may setup these to other cache settings, but we can override this in x86_cpu_init_f(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: bios: Allow pci config read/write to host bridge in int1a_handlerJian Luo2015-07-141-9/+1
| | | | | | | | | We should allow pci config read/write to host bridge (b.d.f = 0.0.0) in the int1a_handler() which is a valid pci device. Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: bios: Synchronize stack between real and protected modeJian Luo2015-07-141-0/+23
| | | | | | | | | PCI option rom may use different SS during its execution, so it is not safe to assume esp pointed to the same location in the protected mode. Signed-off-by: Jian Luo <jian.luo4@boschrexroth.de> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: queensbay: Change PCIe root ports' interrupt routingBin Meng2015-07-142-10/+23
| | | | | | | | | | | | | | | So far interrupt routing works pretty well for any on-chip devices on Intel Crown Bay. When inserting any PCIe card to any PCIe slot, Linux kernel is smart enough to do interrupt swizzling and figure out device's irq using its parent bridge's interrupt routing info all the way up to its root port. In U-Boot all PCIe root ports' interrupts were routed to PIRQ E/F/G/H before, while actually all PCIe downstream ports received INTx are routed to PIRQ A/B/C/D directly and not configurable. Now we change this mapping so that any external PCIe device can work correctly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Generate a valid MultiProcessor (MP) tableBin Meng2015-07-144-0/+181
| | | | | | | | | | | | | | | | | | | | Implement write_mp_table() to create a minimal working MP table. This includes an MP floating table, a configuration table header and all of the 5 base configuration table entries. The I/O interrupt assignment table entry is created based on the same information used in the creation of PIRQ routing table from device tree. A check duplicated entry logic is applied to prevent writing multiple I/O interrupt entries with the same information. Use a Kconfig option GENERATE_MP_TABLE to tell U-Boot whether we need actually write the MP table at the F seg, just like we did for PIRQ routing and SFI tables. With MP table existence, linux kernel will switch to I/O APIC and local APIC to process all the peripheral interrupts instead of 8259 PICs. This takes full advantage of the multicore hardware and the SMP kernel. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add MultiProcessor (MP) table APIsBin Meng2015-07-145-0/+688
| | | | | | | | | | | The MP table provides a way for the operating system to support for symmetric multiprocessing as well as symmetric I/O interrupt handling with the local APIC and I/O APIC. We provide a bunch of APIs for U-Boot to write the floating table, configuration table header as well as base and extended table entries. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Remove inline for lapic access routinesBin Meng2015-07-143-151/+153
| | | | | | | | | Remove inline for lapic access routines and expose lapic_read() & lapic_write() as APIs to read/write lapic registers. Also move stop_this_cpu() to mp_init.c as it has nothing to do with lapic. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add I/O APIC register access routinesBin Meng2015-07-143-1/+46
| | | | | | | | | I/O APIC registers are addressed indirectly. Add io_apic_read() and io_apic_write() routines to help register access. Two macros for I/O APIC ID and version register offset are also added. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Clean up ioapic header fileBin Meng2015-07-141-23/+3
| | | | | | | Remove all the dead/unused macros from asm/ioapic.h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Reduce PIRQ routing table sizeBin Meng2015-07-141-9/+56
| | | | | | | | | | There is no need to populate multiple irq info entries with the same bus number and device number, but with different interrupt pin. We can use the same entry to store all the 4 interrupt pin (INT A/B/C/D) routing information to reduce the whole PIRQ routing table size. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Ignore function number when writing PIRQ routing tableBin Meng2015-07-141-4/+3
| | | | | | | | | | | In fill_irq_info() pci device's function number is written into the table, however this is not really necessary. The function number can be anything as OS doesn't care about this field, neither does the PIRQ routing specification. Change to always writing 0 as the function number. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Write correct bus number for the irq routerBin Meng2015-07-141-1/+1
| | | | | | | | We should write correct bus number to the PIRQ routing table for the irq router from device tree, instead of hard-coded zero. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: queensbay: Correct Topcliff device irqsBin Meng2015-07-141-12/+12
| | | | | | | | | | | | | | | There are 4 usb ports on the Intel Crown Bay board, 2 of which are connected to Topcliff usb host 0 and the other 2 connected to usb host 1. USB devices inserted in the ports connected to usb host 1 cannot get detected due to wrong IRQ assigned to the controller. Actually we need apply the PCI interrupt pin swizzling logic to all devices on the Topcliff chipset when configuring the PIRQ routing. This was observed on usb ports, but device 6 and 10 irqs are also wrong. Correct them all together. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: crownbay: Enable DM RTC supportBin Meng2015-07-142-0/+7
| | | | | | | Add a RTC node in the device tree to enable DM RTC support. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: crownbay: Add MP initializationBin Meng2015-07-141-0/+20
| | | | | | | | | | | | Intel Crown Bay board has a TunnelCreek processor which supports hyper-threading. Add /cpus node in the crownbay.dts and enable the MP initialization. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> (modified to remove error: overriding the value of OF_CONTROL. Old value: "y", new value: "y")
* x86: Clean up lapic codesBin Meng2015-07-145-183/+103
| | | | | | | | | | | | | | | This commit cleans up the lapic codes: - Delete arch/x86/include/asm/lapic_def.h, and move register and bit defines into arch/x86/include/asm/lapic.h - Use MSR defines from msr-index.h in enable_lapic() and disable_lapic() - Remove unnecessary stuff like NEED_LAPIC, X86_GOOD_APIC and CONFIG_AP_IN_SIPI_WAIT - Move struct x86_cpu_priv defines to asm/arch-ivybridge/bd82x6x.h, as it is not apic related and only used by ivybridge - Fix coding convention issues Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Move lapic_setup() call into init_bsp()Bin Meng2015-07-142-3/+1
| | | | | | | | | | Currently lapic_setup() is called before calling mp_init(), which then calls init_bsp() where it calls enable_lapic(), which was already enabled in lapic_setup(). Hence move lapic_setup() call into init_bsp() to avoid the duplication. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Move MP initialization codes into a common placeBin Meng2015-07-145-73/+112
| | | | | | | | | | | Most of the MP initialization codes in arch/x86/cpu/baytrail/cpu.c is common to all x86 processors, except detect_num_cpus() which varies from cpu to cpu. Move these to arch/x86/cpu/cpu.c and implement the new 'get_count' method for baytrail and cpu_x86 drivers. Now we call cpu_get_count() in mp_init() to get the number of CPUs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Remove SMP from CPU_SPECIFIC_OPTIONSBin Meng2015-07-141-1/+0
| | | | | | | Ivybridge is not ready for U-Boot MP initialization yet. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: kconfig: Fix minor nits in MAX_CPUSBin Meng2015-07-141-12/+12
| | | | | | | | | Move MAX_CPUS definition after SMP so that it shows below SMP in the menuconfig. Also replace the leading spaces in the MAX_CPUS section with tabs to conform coding standard. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: kconfig: Make MAX_CPUS and AP_STACK_SIZE depend on SMPBin Meng2015-07-141-0/+2
| | | | | | | MAX_CPUS and AP_STACK_SIZE are only meaningful when SMP is on. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: dm: Clean up cpu driversBin Meng2015-07-146-55/+86
| | | | | | | | | | | | | | | This commit does the following to clean up x86 cpu dm drivers: - Move cpu_x86 driver codes from arch/x86/cpu/cpu.c to a dedicated file arch/x86/cpu/cpu_x86.c - Rename x86_cpu_get_desc() to cpu_x86_get_desc() to keep consistent naming with other dm drivers - Add a new cpu_x86_bind() in the cpu_x86 driver which does exactly the same as the one in the intel baytrail cpu driver - Update intel baytrail cpu driver to use cpu_x86_get_desc() and cpu_x86_bind() Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Move FspInitEntry call to board_init_f()Bin Meng2015-07-144-22/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | The call to FspInitEntry is done in arch/x86/lib/fsp/fsp_car.S so far. It worked pretty well but looks not that good. Apart from doing too much work than just enabling CAR, it cannot read the configuration data from device tree at that time. Now we want to move it a little bit later as part of init_sequence_f[] being called by board_init_f(). This way it looks and works better in the U-Boot initialization path. Due to FSP's design, after calling FspInitEntry it will not return to its caller, instead it jumps to a continuation function which is given by bootloader with a new stack in system memory. The original stack in the CAR is gone, but its content is perserved by FSP and described by a bootloader temporary memory HOB. Technically we can recover anything we had before in the previous stack, but that is way too complicated. To make life much easier, in the FSP continuation routine we just simply call fsp_init_done() and jump back to car_init_ret() to redo the whole board_init_f() initialization, but this time with a non-zero HOB list pointer saved in U-Boot's global data so that we can bypass the FspInitEntry for the second time. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com> Tested-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Load GDT before calling FspInitEntryBin Meng2015-07-144-2/+33
| | | | | | | | | | | | | | | | | | | | | Currently the FSP execution environment GDT is setup by U-Boot in arch/x86/cpu/start16.S, which works pretty well. But if we try to move the FspInitEntry call a little bit later to better fit into U-Boot's initialization sequence, FSP will fail to bring up the AP due to #GP fault as AP's GDT is duplicated from BSP whose GDT is now moved into CAR, and unfortunately FSP calls AP initialization after it disables the CAR. So basically the BSP's GDT still refers to the one in the CAR, whose content is no longer available, so when AP starts up and loads its segment register, it blows up. To resolve this, we load GDT before calling into FspInitEntry. The GDT is the same one used in arch/x86/cpu/start16.S, which is in the ROM and exists forever. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add Kconfig options to be used by arch/x86/cpu/config.mkBin Meng2015-07-142-3/+18
| | | | | | | | | | Add RESET_SEG_START, RESET_SEG_SIZE and RESET_VEC_LOC Kconfig options and make arch/x86/cpu/config.mk use these options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com> Tested-by: Simon Glass <sjg@chromium.org>
* Merge git://git.denx.de/u-boot-marvellTom Rini2015-07-104-0/+81
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| * usb: Add EHCI support for Armada 38x (mvebu)Stefan Roese2015-07-101-0/+1
| | | | | | | | | | | | | | | | | | | | | | This patch adds USB EHCI host support for the common mvebu platform. Including the Armada 38x. Tested on DB-88F6280-GP eval board. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * arm: mvebu: Add SATA/SCSI (AHCI) support for Armada A38xStefan Roese2015-07-102-0/+56
| | | | | | | | | | | | | | | | | | | | This patch adds support for the common AHCI controller on the Marvell Armada 38x. Tested on the Marvell DB-88F6820-GP eval board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * arm: mvebu: Add SDIO/SDHCI support for Armada A38xStefan Roese2015-07-104-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | Armada A38x implements an SDHCI compatible SDIO controller. This patch enables the Marvell driver to support this SoC. And enables the SDIO controller if selected by the board configuration. Tested on Marvell DB-88F6820-GP board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2015-07-083-10/+10
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| * MIPS: change 'extern inline' to 'static inline'Daniel Schwierzeck2015-07-022-9/+9
| | | | | | | | | | | | | | | | The kernel changed it a long time ago. Also this is now broken on gcc-5.x. Reported-by: Andy Kennedy <andy.kennedy@adtran.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: fix missing semicolon in cacheops.hTony Wu2015-07-021-1/+1
| | | | | | | | | | | | | | | | Fix missing semicolon in cacheops.h introduced in commit 2b8bcc5a2 (MIPS: avoid .set ISA for cache operations) Signed-off-by: Tony Wu <tung7970@gmail.com> Cc: Paul Burton <paul.burton@imgtec.com>
* | sunxi: Adjust Ippo_q8h_v1_2_a33_1024x600 dts filename to match the upstream ↵Hans de Goede2015-07-082-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | kernel sun8i-a33-ippo-q8h-v1.2-lcd1024x600.dts has been merged into the upstream Linux kernel as sun8i-a33-ippo-q8h-v1.2.dts, adjust u-boot to follow. Note we've never shipped a final u-boot version with the old name, so this is safe todo. Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2015-07-0710-26/+34
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| * | ARM: disable HAVE_PRIVATE_LIBGCC for ARM64Masahiro Yamada2015-07-071-1/+1
| | | | | | | | | | | | | | | | | | | | | We have not supported the private library for ARM 64bit. Prohibit ARM64 boards from enabling it until we make things ready. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | Revert "break build if it would produce broken binary"Simon Glass2015-07-071-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | The root cause of this problem should now be fixed. This reverts commit a6a4c542d316b3401f0840ac5378743191bca851. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Pavel Machek <pavel@denx.de> Tested-by: Pavel Machek <pavel@denx.de>
| * | arm: Add ENTRY/ENDPROC to private libgcc functionsSimon Glass2015-07-077-17/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_SYS_THUMB_BUILD is defined these functions may be called from Thumb code. Add the required ENTRY and ENDPROC bracketing so that BLX is used to call these ARM functions, instead of plain BL, which will fail. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Pavel Machek <pavel@denx.de>
| * | Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2015-07-07165-2307/+4135
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| * | | armv7: better comment in start.SPavel Machek2015-07-071-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix big/small letters in comment. Signed-off-by: Pavel Machek <pavel@denx.de> Tested-by: Marek Vasut <marex@denx.de>
* | | | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2015-07-057-7/+161
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| * | | | sunxi: Add Sinlinx SinA33 defconfigChen-Yu Tsai2015-07-051-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sinlinx SinA33 is a core/daughter board SDK kit from Sinlinx. It has the A33 SoC, USB host, USB OTG, audio input/output, LCD, camera, SDIO and GPIO headers. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | | sunxi: Sync sun8i dts files with the linux kernelChen-Yu Tsai2015-07-053-0/+147
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Copy over all the latest dts changes from mripard/sunxi/dt-for-4.2. This adds a dts file for Sinlinx SinA33 dev board, and the required changes in the .dtsi files. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | | sunxi: Add support for UART0 in PB pin group on A33Chen-Yu Tsai2015-07-052-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A33 adds a pinmux function for UART0 in the PB pin group. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | | sunxi: rsb: Enable R_PIO clock before configuring external pinsChen-Yu Tsai2015-07-051-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original code was configuring the external pins after enabling the R_PIO clock, which meant the configuration never made it to the pin controller the first time in SPL. Why this was working before is uncertain. Maybe the state was left from a previous boot sequence, or RSB just happened to be the default configuration. However with some A33 chips, SPL failed to configure the PMIC. This was seen by me and Maxime on the Sinlinx SinA33 dev board. Reordering the calls fixed this. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Cc: Maxime Ripard <maxime.ripard@free-electrons.com> Tested-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | | | sunxi: hardware-feature-specific function index defines for PORT F UART0Chen-Yu Tsai2015-07-051-4/+4
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 487b327 ("sunxi: GPIO pin mux hardware-feature-specific function index defines") renamed all GPIO index defines, but missed the PORT F UART0 setup functions. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-07-037-10/+19
|\ \ \ \ | |/ / / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: configs/tbs2910_defconfig configs/tqma6q_mba6_mmc_defconfig configs/tqma6q_mba6_spi_defconfig configs/tqma6s_mba6_mmc_defconfig configs/tqma6s_mba6_spi_defconfig include/configs/mx6_common.h Signed-off-by: Tom Rini <trini@konsulko.com>
| * | | imx: mx6 introuduce macro is_mx6dqpPeng Fan2015-06-272-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a new revision CHIP_REV_2_0. Introudce macro is_mx6dqp, dqp means Dual/Quad Plus. Since Dual/Quad Plus use same cpu type with Dual/Quad, but different revision(Major Lower), we use this macro for Dual/Quad Plus. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
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