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* omap-common: Common omap_die_id definitionPaul Kocialkowski2015-10-222-0/+7
| | | | | | | | This introduces a common definition for omap_die_id, that aims at providing a common interface for accessing omap platform's die id bits. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-x86Tom Rini2015-10-2138-352/+1191
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| * x86: Add support for Advantech SOM-6896George McCollister2015-10-212-1/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Advantech SOM-6896 is a Broadwell U based COM Express Compact Module Type 6. This patch adds support for it as a coreboot payload. On board SATA and SPI are functional. On board Ethernet isn't functional but since it's optional and ties up a PCIe x4 that is otherwise brought out, this isn't a concern at the moment. USB doesn't work since the xHCI driver appears to be broken. Signed-off-by: George McCollister <george.mccollister@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
| * x86: ivybridge: Enable the MRC cacheBin Meng2015-10-211-8/+2
| | | | | | | | | | | | | | | | | | This works correctly now, so enable it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Dropped malloc() and adjusted commit message: Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: ivybridge: Measure the MRC code execution timeSimon Glass2015-10-211-0/+3
| | | | | | | | | | | | | | | | This code takes about 450ms without the MRC cache and about 27ms with the cache. Add a debug timer so that this time can be displayed. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: ivybridge: Fix car_uninit() to correctly set run stateSimon Glass2015-10-211-1/+1
| | | | | | | | | | | | | | | | At present a missing $ causes this code to hang when using the MRC cache/ Fix it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: ivybridge: Check the RTC return valueSimon Glass2015-10-211-3/+10
| | | | | | | | | | | | | | The RTC can fail, so check the return value for reads. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: ivybridge: Use 'ret' instead of 'rcode'Simon Glass2015-10-211-8/+8
| | | | | | | | | | | | | | For consistency, use 'ret' to handle a return value. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: chromebook_link: Enable the debug UARTSimon Glass2015-10-211-0/+7
| | | | | | | | | | | | | | Add support for the debug UART on link. This is useful for early debugging. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Init the debug UART if enabledSimon Glass2015-10-211-8/+3
| | | | | | | | | | | | | | | | | | If the debug UART is enabled, get it ready for use at the earliest possible opportunity. This is not actually very early, but until we have a stack it is difficult to make it work. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Pass correct cpu_index to ap_init()Bin Meng2015-10-211-2/+2
| | | | | | | | | | | | | | | | In sipi_vector.S, cpu_index (passed as %eax) is wrongly overwritten by the ap_init() function address. Correct it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: galileo: Enable mrc cacheBin Meng2015-10-211-0/+4
| | | | | | | | | | | | | | | | Now that we have added MRC cache on quark support codes, enable it on Intel Galileo board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: quark: Implement mrc cacheBin Meng2015-10-212-7/+64
| | | | | | | | | | | | | | | | Using existing mrccache library to implement mrc cache support for Intel Quark. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: ivybridge: Correct two typos for MRCBin Meng2015-10-211-2/+2
| | | | | | | | | | | | | | It should be MRC, not MCR. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Remove unused rw-mrc-cache properties in the link and panther dts filesBin Meng2015-10-212-5/+0
| | | | | | | | | | | | | | | | | | "type" and "wipe-value" are never used by the mrccache codes. Remove them to avoid confusion. This also removes the alignment comment in the panther dts file. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: baytrail: Issue full system reset in reset_cpu()Bin Meng2015-10-211-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With MRC cache enabled, when typing 'reset' in the U-Boot shell, BayTrail FSP initialization hangs at "Configuring Memory Start": Setting BootMode to 0 Install PPI: 1F4C6F90-B06B-48D8-A201-BAE5F1CD7D56 Register PPI Notify: F894643D-C449-42D1-8EA8-85BDD8C65BDE About to call MrcInit(); BayleyBay Platform Type CurrentMrcData.BootMode = 4 Taking Fastboot path! Configuring Memory Start... Changing reset_cpu() to do a full system reset fixes this issue. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Enable mrc cache for bayleybay and minnowmaxBin Meng2015-10-212-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | Now that we have added MRC cache for Intel FSP and BayTrail codes, enable it for all BayTrail boards (Bayley Bay and Minnow Max). Note it turns out that FSP for Intel Atom E6xx does not produce the HOB for NV storage, so we don't have such functionality on Intel Crown Bay board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: baytrail: Save mrc cache to spi flashBin Meng2015-10-211-0/+19
| | | | | | | | | | | | | | Save MRC cache to SPI flash in arch_misc_init(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: fsp: Pass mrc cache to fsp_init() and save it to gd after fsp_init()Bin Meng2015-10-212-1/+35
| | | | | | | | | | | | | | | | | | | | fsp_init() call has a parameter nvs_buf which is used by FSP as the MRC cache but currently is blindly set to NULL. Retreive the MRC cache from SPI flash and pass it to fsp_init() call. After the call, save FSP produced MRC cache to SPI flash too. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Use struct mrc_region to describe a mrc regionBin Meng2015-10-213-15/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently struct fmap_entry is used to describe a mrc region. However this structure contains some other fields that are not related to mrc cache and causes confusion. Besides, it does not include a base address field to store SPI flash's base address. Instead in the mrccache.c it tries to use CONFIG_ROM_SIZE to calculate the SPI flash base address, which unfortunately is not 100% correct as CONFIG_ROM_SIZE may not match the whole SPI flash size. Define a new struct mrc_region and use it instead. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: ivybridge: Use APIs provided in the mrccache libBin Meng2015-10-211-108/+4
| | | | | | | | | | | | | | | | Remove the call to custom mrc cache APIs, and use the ones provided in the mrccache lib. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Add more common routines to manipulate mrc cacheBin Meng2015-10-212-0/+140
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds mrccache_reserve(), mrccache_get_region() and mrccache_save() APIs to the mrccache codes. They are ported from the ivybridge implementation, but with some changes. For example, in the mrccache_reserve(), ivybridge version only reserves the pure MRC data, which causes additional malloc() when saving the cache as the save API needs some meta data. Now we change it to save the whole MRC date plus the meta data to elinimate the need for the malloc() later. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Add various minor tidy-ups in mrccache codesBin Meng2015-10-212-18/+16
| | | | | | | | | | | | | | | | Fix some nits, improve some comments and reorder some codes a little bit. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Do sanity test on the cache record in mrccache_update()Bin Meng2015-10-212-1/+4
| | | | | | | | | | | | | | | | For the cache record to write in mrccache_update(), we should perform a sanity test to see if it is a valid one. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Move mrccache.[c|h] to a common placeBin Meng2015-10-215-4/+3
| | | | | | | | | | | | | | | | mrccache implementation can be common for all boards. Move it from ivybridge cpu directory to the common lib directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Add ENABLE_MRC_CACHE Kconfig optionBin Meng2015-10-211-0/+8
| | | | | | | | | | | | | | Create a Kconfig option for enabling MRC cache. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: fsp: Add a hdr sub-command to show header informationBin Meng2015-10-211-1/+31
| | | | | | | | | | | | | | | | It would be helpful to have a command to show FSP header. So far it only supports FSP header which conforms to FSP spec 1.0. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: fsp: Make hob command a sub-command to fspBin Meng2015-10-213-7/+28
| | | | | | | | | | | | | | | | | | Introduce a new fsp command and make the existing hob command a sub-command to fsp for future extension. Also move cmd_hob.c to the dedicated fsp sub-directory in arch/x86/lib. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: fsp: Print GUID whenever applicable in the hob command outputBin Meng2015-10-211-3/+19
| | | | | | | | | | | | | | | | When examining a HOB, it's useful to see which GUID this HOB belongs to. Add GUID output in the hob command to aid this. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: fsp: Compact the output of hob commandBin Meng2015-10-211-14/+14
| | | | | | | | | | | | | | | | Compact hob command output, especially by making hob type string a little bit shorter so that we can leave room for future extension. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Add SMBIOS table supportBin Meng2015-10-215-0/+522
| | | | | | | | | | | | | | | | | | | | | | | | System Management BIOS (SMBIOS) is a specification for how motherboard and system vendors present management information about their products in a standard format by extending the BIOS interface on Intel architecture systems. As of today the latest spec is 3.0 and can be downloaded from DMTF website. This commit adds a simple and minimum required implementation. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Move install_e820_map() out of zimage.cBin Meng2015-10-215-29/+41
| | | | | | | | | | | | | | | | install_e820_map() has nothing to do with zimage related codes. Move it to a dedicated place. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: Initialize GDT entry 1 to be the 32-bit CS as wellBin Meng2015-10-211-1/+6
| | | | | | | | | | | | | | | | Some OS (like VxWorks) requires GDT entry 1 to be the 32-bit CS. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Jian Luo <jian.luo4@boschrexroth.de>
| * x86: Allow disabling IGD on Intel QueensbayBin Meng2015-10-213-0/+32
| | | | | | | | | | | | | | | | | | | | Add a Kconfig option to disable the Integrated Graphics Device (IGD) so that it does not show in the PCI configuration space as a VGA disaplay controller. This gives a chance for U-Boot to run PCI/PCIe based graphics card's VGA BIOS and use that for the graphics console. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: ivybridge: Remove the dead codes that programs pci bridgeBin Meng2015-10-211-32/+0
| | | | | | | | | | | | | | Remove bd82x6x_pci_bus_enable_resources() that is not called anywhere. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* | Merge git://git.denx.de/u-boot-marvellTom Rini2015-10-2019-28/+3357
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| * | arm: mvebu: Enable DM_SERIAL on AXP / A38x boardsStefan Roese2015-10-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | This patch enables DM_SERIAL for all ARCH_MVEBU boards (AXP & A38x). Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu: Add DM (driver model) supportStefan Roese2015-10-212-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds driver model support for some Marvell MVEBU SoC's. Including Armada XP and 38x. All 3 currently mainlined boards are converted. DM is now selected automatically for MVEBU platforms. With this DM support now available for MVEBU, hardcoding the base addresses and other information is not necessary any more. Probing should be done by using the values provided via the device tree now instead. For this the driver also need to be converted to DM. Patches for some of the drivers will follow. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu: Add basic Armada XP / 38x dtsi/dts filesStefan Roese2015-10-2112-0/+3257
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These will be needed by the upcoming DM (driver model) support for the Armada XP / 38x SoC's. This will provide DT based probing. The dts files are copied 1:1 from the Linux kernel release v4.2. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu: Do not call board_init_r() from board_init_f()Stefan Roese2015-10-211-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of calling board_init_r() directly from board_init_f(), just return from board_init_f(). This will make the code continue executing in crt0.S _main(), from which the board_init_r() is called. This patch aligns the MVEBU SPL with the correct SPL design as well as reduces the stack utilisation slightly. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu: Only set CONFIG_SKIP_LOWLEVEL_INIT for SPLStefan Roese2015-10-211-12/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | When running on the AXP I sometimes noticed a strange behavior. As some characters are not echoed on the U-Boot prompt. Not disabling the lowlevel_init code, especially calling cpu_init_cp15() in the main U-Boot seems to solve this issue. Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm: mvebu: Add option to use UART xmodem protocol via kwbootStefan Roese2015-10-215-1/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables the use of the kwboot tool, to boot mainline U-Boot on the Marvell Armada XP/38x SoC's. This is done by returning to the SoC's BootROM after SPL has initialized the SDRAM. We need to make sure to not reconfigure the internal register space and MBARs. Otherwise the BootROM will not be able to continue after SPL jumps back to it. To use this feature, please don't forget to change the BOOT_FROM line in your board specfic kwbimage.cfg file this way: BOOT_FROM uart Tested on these Marvell eval boards: DB-MV784MP-GP - Armada XP DB-88F6820-GP - Armada 38x Signed-off-by: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <eibach@gdsys.de> Cc: Kevin Smith <kevin.smith@elecsyscorp.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu: Move Armada XP/38x Kconfig to mach specific Kconfig fileStefan Roese2015-10-202-12/+25
| |/ | | | | | | | | | | Introduce a mach-mvebu/Kconfig for all Armada based SoC's. Signed-off-by: Stefan Roese <sr@denx.de>
* | sunxi: Add CHIP supportMaxime Ripard2015-10-202-1/+216
| | | | | | | | | | | | | | | | | | | | | | | | | | The C.H.I.P. is a small SBC with an Allwinner R8, 8GB of NAND, 512MB of RAM, USB host and OTG, a wifi / bluetooth combo chip, an audio/video jack and two connectors to plug additional boards on top of it. The DT is identical to the DT submitted to the upstream kernel. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | axp209: Sync the DTSI with the kernelMaxime Ripard2015-10-201-0/+5
| | | | | | | | | | | | | | | | Linux had a number of changes to the AXP209 DTSI. Sync ours. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sun5i: Sync the DTSI with the kernelMaxime Ripard2015-10-204-10/+146
| | | | | | | | | | | | | | | | Add the latest kernel changes to the sun5i family DTSI. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi: board: Only try to use the MMC related functions if enabledMaxime Ripard2015-10-201-1/+5
| | | | | | | | | | | | | | | | | | | | | | So far, even if CONFIG_MMC was not enabled the board code was trying to use the MMC-related functions, resulting in linker errors. Protect those calls by an ifdef. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | sunxi: Add defconfig for the Sinovoip BPI-M2 boardHans de Goede2015-10-203-1/+214
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Sinovoip BPI-M2 is a SBC board based on the A31s SoC it features 1G RAM, a microsd slot, Gbit ethernet, 4 usb-a USB-2 ports, ir receiver, stereo headphone jack and hdmi video output. The dts changes are identical to the dts files submitted upstream. A few notes on the use if dldo and aldo regulators. DLDO1 is used for Vdd for the ethernet phy, ALDO2 is used for AVdd for the ethernet phy. ALDO1 is used to power the sdio wifi module. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: power: Unify axp pmic function namesHans de Goede2015-10-202-11/+2
| | | | | | | | | | | | | | | | | | Stop prefixing the axp functions for setting voltages, etc. with the model number, there ever is only one pmic driver built into u-boot, this allows simplifying the callers. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Remove board defconfig-s for specific Q8 tablet PCB-sHans de Goede2015-10-207-475/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We now have generic q8_a?3_defconfig files for Q8 formfactor tablets with an A13 / A23 / A33 SoC, there is no need for these PCB variant specific defconfig-s and they only serve to confuse the user. Note that in case of the forfun_q88db_defconfig and TZX-Q8-713B7_defconfig for A13 based Q8 tablets there is not even a dts file for these in the upstream kernel, which is all the more reason to remove them. The generic q8_a?3_defconfig files have been tested on an Et_q8_v1_6, Ippo_q8h_v1_2_a33_1024x600, Ippo_q8h_v1_2 and TZX-Q8-713B7 tablet, and the forfun_q88db_defconfig is identical to q8_a13_tablet_defconfig. This leaves only the Ippo_q8h_v5 untested with the new generic defconfigs but there is no reason to assume that it will not work. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
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