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* ARM: uniphier: rename function names ph1_* to uniphier_*Masahiro Yamada2016-04-0151-193/+197
| | | | | | | Eliminate the "ph1"_ prefixes from function names because "uniphier_" describes the SoC familiy better. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: add pin-mux settings for NAND, eMMC, SD of PH1-sLD3Masahiro Yamada2016-04-011-0/+23
| | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: enable eMMC on PH1-sLD3 reference boardMasahiro Yamada2016-04-011-0/+4
| | | | | | | On PH1-sLD3, eMMC and NAND are assigned to different I/O pins. Both devices can be enabled at the same time. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: uniphier: adjust dram_init() and dram_init_banksize() for ARM64Masahiro Yamada2016-04-011-10/+35
| | | | | | | | | | | Currently, these functions assume #address-cells and #size-cells are both one. Fix them to support 64bit DTB. Also, I am fixing a buffer overrun bug while I am here. The array size of gd->bd->bd_dram is CONFIG_NR_DRAM_BANKS. The number of iteration in the loop should be limited by that CONFIG. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: dts: uniphier: add NAND pinmux nodeMasahiro Yamada2016-04-011-0/+5
| | | | | | This will be used to set up pin-muxing for the NAND controller. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* ARM: dts: uniphier: add clock-frequency to serial nodes of LD11/LD20Masahiro Yamada2016-04-012-0/+8
| | | | | | | | Since no clock driver is implemented for peripherals in U-Boot yet, this property is needed for the serial driver to set up the divisor register. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2016-03-291-0/+2
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| * ARM: tegra210: set PLLE_PTS bit when enabling PLLEStephen Warren2016-03-291-0/+2
| | | | | | | | | | | | | | | | This bit needs to be set for system suspend/resume to work. This setting will be documented in an updated TRM at some time in the future. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-03-297-8/+124
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| * | armv8/ls2080ardb: Enable VID supportRai Harninder2016-03-291-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | This patch enable VID support for ls2080ardb platform. It uses the common VID driver. Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8/ls1043aqds: dts: Set SPI mode for DSPIQianyu Gong2016-03-291-1/+7
| | | | | | | | | | | | | | | | | | | | | Clock phase and polarity for DSPI flash need to be set. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-layerscape: Add LS1023A SVRMingkai Hu2016-03-292-0/+2
| | | | | | | | | | | | | | | | | | Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-layerscape: Fix LS1043A SVR registerMingkai Hu2016-03-291-1/+1
| | | | | | | | | | | | | | | | | | Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-lsch3: Disable SMMU during secure bootSaksham Jain2016-03-292-1/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During secure boot, SMMU is enabled on POR by SP bootrom. SMMU needs to be put in bypass mode in uboot to enable CAAM transcations to pass through. For non-secure boot, SP BootROM doesn't enable SMMU, which is in bypass mode out of reset. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls2080: Add config for endianess of CCSR GURSaksham Jain2016-03-291-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GUR (DCFG) registers in CCSR space are in little endian format. Define a config CONFIG_SYS_FSL_CCSR_GUR_LE in arch/arm/include/asm/arch-fsl-layerscape/config.h Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls2080: Change env variable "fdt_high"Saksham Jain2016-03-291-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "fdt_high" env variable was set to 0xcfffffff for secure boot. Change it to 0xa0000000 for LS2080 to be consistent with non-secure boot targets. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-lsch3: Copy Bootscript and header from NOR to DDRSaksham Jain2016-03-291-3/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To unify steps for secure boot for xip (eg. NOR) and non-xip memories (eg. NAND, SD), bootscipts and its header are copied to main memory. Validation and execution are performed from there. For other ARM Platforms (ls1043 and ls1020), to avoid disruption of existing users, this copy step is not used for NOR boot. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls2080: Add bootscript header addr for secure bootSaksham Jain2016-03-291-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During secure boot, Linux image along with other images are validated using bootscript. This bootscript also needs to be validated before it executes. This requires a header for bootscript. When secure boot is enabled, default bootcmd is changed to first validate bootscript using the header and then execute the script. For ls2080, NOR memory map is different from other ARM SoCs. So a new address on NOR is used for this bootscript header (0x583920000). The Bootscript address is mentioned in this header along with addresses of other images. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls2080rdb: ls2080qds: Add secure boot supportSaksham Jain2016-03-291-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sec_init has been called at the beginning to initialize SEC Block (CAAM) which is used by secure boot validation later for both ls2080a qds and rdb. 64-bit address in ESBC Header has been enabled. Secure boot defconfigs are created for boards (NOR boot). Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-lsch3: Add new header for secure bootSaksham Jain2016-03-292-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For secure boot, a header is used to identify key table, signature and image address. A new header structure is added for lsch3. Currently key extension (IE) feature is not supported. Single key feature is not supported. Keys must be in table format. Hence, SRK (key table) must be present. Max key number has increase from 4 to 8. The 8th key is irrevocable. A new barker Code is used. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls2080: Add configs for SEC, SecMon, SRK and DCFGSaksham Jain2016-03-292-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add configs for various IPs used during secure boot. Add address and endianness for SEC and Security Monitor. SRK are fuses in SFP (fuses for public key's hash). These are stored in little endian format. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls2080: Add SFP Configs for LS2080Saksham Jain2016-03-292-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | In LS2080, SFP has version 3.4. It is in little endian. The base address is 0x01e80200. SFP is used in Secure Boot to read fuses. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Signed-off-by: Saksham Jain <saksham.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-layerscape: Skip reconfigure QSPI clock when booting from QSPIQianyu Gong2016-03-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The qspi_cfg register is set by PBI when booting from QSPI. No need to changing it again. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | | dm: i2c: mxc_i2c: implement i2c_idle_busPeng Fan2016-03-281-0/+10
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement i2c_idle_bus in driver, then setup_i2c can be dropped for boards which enable DM_I2C/DM_GPIO/PINCTRL. The i2c_idle_bus force bus idle flow follows setup_i2c in arch/arm/imx-common/i2c-mxv7.c This patch is an implementation following linux kernel patch: " commit 1c4b6c3bcf30d0804db0d0647d8ebeb862c6f7e5 Author: Gao Pan <b54642@freescale.com> Date: Fri Oct 23 20:28:54 2015 +0800 i2c: imx: implement bus recovery Implement bus recovery methods for i2c-imx so we can recover from situations where SCL/SDA are stuck low. Once i2c bus SCL/SDA are stuck low during transfer, config the i2c pinctrl to gpio mode by calling pinctrl sleep set function, and then use GPIO to emulate the i2c protocol to send nine dummy clock to recover i2c device. After recovery, set i2c pinctrl to default group setting. " See Documentation/devicetree/bindings/i2c/i2c-imx.txt for detailed description. 1. Introuduce scl_gpio/sda_gpio/bus in mxc_i2c_bus. 2. Discard the __weak attribute for i2c_idle_bus and implement it, since we have pinctrl driver/driver model gpio driver. We can use device tree, but not let board code to do this. 3. gpio state for mxc_i2c is not a must, but it is recommended. If there is no gpio state, driver will give tips, but not fail. 4. The i2c controller was first probed, default pinctrl state will be used, so when need to use gpio function, need to do "pinctrl_select_state(dev, "gpio")" and after force bus idle, need to switch back "pinctrl_select_state(dev, "default")". This is example about how to use the gpio force bus idle function: " &i2c1 { clock-frequency = <100000>; pinctrl-names = "default", "gpio"; pinctrl-0 = <&pinctrl_i2c1>; pinctrl-1 = <&pinctrl_i2c1_gpio>; scl-gpios = <&gpio1 28 GPIO_ACTIVE_HIGH>; sda-gpios = <&gpio1 29 GPIO_ACTIVE_HIGH>; status = "okay"; [....] }; [.....] pinctrl_i2c1_gpio: i2c1grp_gpio { fsl,pins = < MX6UL_PAD_UART4_TX_DATA__GPIO1_IO28 0x1b8b0 MX6UL_PAD_UART4_RX_DATA__GPIO1_IO29 0x1b8b0 >; }; " Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: York Sun <york.sun@nxp.com>
* | ARM: asm: types: Introduce DMA_ADDR_T_64BITLokesh Vutla2016-03-272-2/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dma_addr_t holds any valid DMA address. If the DMA API only uses 32-bit addresses, dma_addr_t need only be 32 bits wide. Bus addresses, e.g., PCI BARs, may be wider than 32 bits, but drivers do memory-mapped I/O to ioremapped kernel virtual addresses, so they don't care about the size of the actual bus addresses. Also 32 bit ARM systems with LPAE enabled can use 64bit address space, but DMA still use 32bit address like in case of DRA7 and Keystone platforms. This is inspired from the Linux kernel types implementation[1] [1] https://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/include/linux/types.h#n142 Acked-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | pxa: add support for D- and I- cachesVasily Khoruzhick2016-03-273-0/+73
| | | | | | | | | | | | Tested with OHCI and pxafb drivers - no issues found Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
* | pxa: start.S: enable SRAM clockVasily Khoruzhick2016-03-271-1/+9
| | | | | | | | | | | | | | SRAM is used for early stack, but kernel disables its clock on suspend. Re-enable SRAM clock on startup, otherwise u-boot crashes on resume from suspend. Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
* | zipitz2: restore board supportVasily Khoruzhick2016-03-271-0/+5
| | | | | | | | | | | | zipitz2 was dropped in 49d8899ba9c26335e4a12e01c18028fc5e40c796 Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
* | Fix typo in chosen parameter of pcm052.dtsAlexander Merkle2016-03-271-1/+1
| | | | | | | | | | | | | | | | Fix typo "choosen" instead of "chosen" in pcm052.dts. Not tested but should fix boot process and terminal output. Signed-off-by: Alexander Merkle <alexander.merkle@lauterbach.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | Fix typo in chosen parameter in vf610-twr.dtsAlexander Merkle2016-03-271-1/+1
| | | | | | | | | | | | | | | | Fix typo "choosen" instead of "chosen" in vf610-twr.dts. Fixes boot process and terminal output for Vybrid series. Signed-off-by: Alexander Merkle <alexander.merkle@lauterbach.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | ARM: bcm2835: fix 64-bit build warning in mboxStephen Warren2016-03-271-2/+4
| | | | | | | | | | | | | | | | | | | | Fixes: arch/arm/mach-bcm283x/mbox.c: In function ‘bcm2835_mbox_call_prop’: arch/arm/mach-bcm283x/mbox.c:118:48: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] arch/arm/mach-bcm283x/mbox.c:126:29: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: bcm283x: don't always define CONFIG_BCM2835Stephen Warren2016-03-276-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently, CONFIG_BCM2835 is defined for all BCM283x builds and _BCM2836 is defined when building for that SoC. That means there isn't a single define that means "exactly BCM2835". This will complicate future patches where BCM2835-vs-anything-else needs to be determined simply. Modify the code to define one or the other of CONFIG_BCM2835/BCM2836 so future patches are simpler. Signed-off-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | RPi: Enable caches for rpi2Alexander Graf2016-03-272-0/+8
| | | | | | | | | | | | | | | | Now that we have support for running with caches enabled in HYP mode, opt in to that on the Raspberry Pi 2. This brings a significant performance boost. Signed-off-by: Alexander Graf <agraf@suse.de>
* | arm: Add support for HYP mode and LPAE page tablesAlexander Graf2016-03-273-12/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We currently always modify the SVC versions of registers and only support the short descriptor PTE format. Some boards however (like the RPi2) run in HYP mode. There, we need to modify the HYP version of system registers and HYP mode only supports the long descriptor PTE format. So this patch introduces support for both long descriptor PTEs and HYP mode registers. Signed-off-by: Alexander Graf <agraf@suse.de>
* | arm64: Add 32bit arm compatible dcache definitionsAlexander Graf2016-03-271-1/+5
| | | | | | | | | | | | | | | | | | | | | | We want to be able to reuse device drivers from 32bit code, so let's add definitions for all the dcache options that 32bit code has. While at it, fix up the DCACHE_OFF configuration. That was setting the bits to declare a PTE a PTE and left the MAIR index bit at 0. Drop the useless bits and make the index explicit. Signed-off-by: Alexander Graf <agraf@suse.de>
* | ARM: OMAP5/DRA7: Expose do_set_iodelayNishanth Menon2016-03-272-2/+4
| | | | | | | | | | | | | | | | do_set_iodelay can now be used from board files based on needs of the platforms variation they have. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: OMAP5/DRA7: Split iodelay functionality into sub stepsNishanth Menon2016-03-272-14/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since many platforms may need different pad configuration required depending on variation of the platform with minor deltas, it is easier to maintain a sub step based approach to allow for pin mux and iodelay configuration which may depend on the platform variations and need to be done in IO isolation. While we retain the older __recalibrate_iodelay function which provides a ready sequencing, __recalibrate_iodelay_start and __recalibrate_iodelay_end may be alternatively used now and the callers will be responsible for the correct sequencing of operations. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: DRA72: sdram: Update sdram ext phy configuration for SR2.0Nishanth Menon2016-03-271-1/+43
| | | | | | | | | | | | | | Based on data from EMIF configuration tool 1.1.1. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: DRA7: hwdata: Update ioreg data for DRA72 SR2.0Nishanth Menon2016-03-271-1/+15
| | | | | | | | | | | | | | | | | | Based on data from EMIF configuration tool 1.1.1. Expected update for CTRL_WKUP_EMIF1_SDRAM_CONFIG_EXT in the next revision of the tool has been incorporated as well. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: DRA72x: Add support for detection of SR2.0Ravi Babu2016-03-275-0/+9
| | | | | | | | | | | | | | | | | | Add support for detection of SR2.0 version of DRA72x family of processors. Signed-off-by: Ravi Babu <ravibabu@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: keystone2: Convert BOOT_SET_BITFIELD into static inline functionNishanth Menon2016-03-271-7/+11
| | | | | | | | | | | | | | | | | | Fix up BOOT_SET_BITFIELD to be a static inline function to be readable with the same functionality. Reported-by: Tom Rini <trini@konsulko.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: keystone2: Convert BOOT_READ_BITFIELD into static inline functionNishanth Menon2016-03-271-10/+15
| | | | | | | | | | | | | | | | | | BOOT_READ_BITFIELD can easily be a static inline function and be a little more readable with the same functionality. Reported-by: Tom Rini <trini@konsulko.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | ARM: keystone2: Convert BOOTBITMASK to static inline functionNishanth Menon2016-03-271-5/+9
| | | | | | | | | | | | | | | | | | BOOTBITMASK is almost impossible to decode, so convert it into a simpler static line functions of equivalent solution. Reported-by: Tom Rini <trini@konsulko.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | stm32f746-disco: enable flash supportVikas Manocha2016-03-261-0/+6
| | | | | | | | | | | | This patch enables embedded flash for stm32f746 discovery board. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* | stm32: stm32f4: move flash driver to mtd driver locationVikas Manocha2016-03-264-178/+11
| | | | | | | | | | | | | | Same flash driver can be used by other stm32 families like stm32f7. Better place for this driver would be mtd driver location. Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
* | Merge git://www.denx.de/git/u-boot-marvellTom Rini2016-03-253-0/+27
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| * | arm: mvebu: theadorable: Add StratixV FPGA programming supportStefan Roese2016-03-241-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for Altera StratixV bitstream programming. 2 FPGAs are connected to the SPI busses. This patch uses board specific write code to program the bitstream via SPI direct write mode. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm: mvebu: spi.h: Add registers for direct write accessStefan Roese2016-03-241-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | The direct write config register is needed for SPI direct write mode configuration. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Signed-off-by: Stefan Roese <sr@denx.de>
| * | arm: mvebu: Add some SPI CS attributesStefan Roese2016-03-241-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These attribute defines may be used to map an area of memory for direct access to the specific SPI devices. See SPI Direct Access Mode for further information. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Signed-off-by: Stefan Roese <sr@denx.de>
* | | Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2016-03-2381-557/+5572
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