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| * | | arm: dts: zynq: Add digilent ZYBO board dtsPeter Crosthwaite2014-11-112-0/+24
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | It's a Zynq board similar in design to the currently supported ones. 512MB of RAM and UART1 is used. Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Acked-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | kconfig: arm: move "armv8" define to arch/arm/KconfigMasahiro Yamada2014-11-132-8/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 2e07c249a67e (kconfig: arm: introduce symbol for ARM CPUs) collected the default values of CONFIG_SYS_CPU into arch/arm/Kconfig. This commit moves "armv8" to there for consistency. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Georges Savoundararadj <savoundg@gmail.com>
* | | kconfig: arm: select CPU_V7 for some new boardsMasahiro Yamada2014-11-132-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds "select CPU_V7" for some new boards that were not covered by commit 2e07c249a67e (kconfig: arm: introduce symbol for ARM CPUs). Redundant "SYS_CPU" defines and "string" directives should be removed. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Georges Savoundararadj <savoundg@gmail.com>
* | | powerpc: remove orphaned boards mcc200 and prs200Nikita Kiryanov2014-11-121-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mcc200 and prs200 are old and have no maintainer. Remove the boards. This also removes the mcc200 specific 1bpp BMP support from common/lcd.c Cc: Wolfgang Denk <wd@denx.de> Cc: Anatolij Gustschin <agust@denx.de> Cc: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: York Sun <yorksun@freescale.com> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* | | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2014-11-119-0/+900
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| * | arm: socfpga: Add socfpga_spim_enable() to reset_manager.cStefan Roese2014-11-073-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function will be needed by the upcoming Designware master SPI driver. As the SPI master controller is held in reset by the current Preloader implementation. So we need to release the reset for the driver to communicate with the controller. This function is called from arch_early_init_r() if the SPI driver is enabled. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de>
| * | arm: socfpga: Add DW master SPI clock to clock_manager.cStefan Roese2014-11-071-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function will be needed by the upcoming Designware master SPI driver. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de>
| * | arm: socfpga: Add DT support for SoCFPGA and add socfpga_socrates targetStefan Roese2014-11-075-0/+868
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch includes the latest DT sources for socfpga from the current Linux kernel. And enables CONFIG_OF_CONTROL for the new build target "socfpga_socrates" (the EBV SoCrates board) to make use of this new DT support. Until this patch, the only SoCFPGA U-Boot target in mainline is "socfpga_cyclone5". This build target is not (yet) changed to support DT. So nothing changes for this target. Even though the long-term goal should be to move all SoCFPGA targets over to DT. One of the reasons to enable DT support in SoCFPGA is, that I need to support multiple different SPI controllers for this platform. This is the QSPI Cadence controller and the Designware SPI master controller. Both are implemented in the SoCFPGA. And enabling both controllers is only possible by using the new driver model (DM). The DM SPI code only supports DT based probing. So it was easier to move SoCFPGA to DT than to add the (deprecated) platform-data based probing to the DM SPI suport. Note that the image with the dtb embedded is u-boot-dtb.img. This needs to be used now for those DT enabled boards instead of u-boot.img. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Pavel Machek <pavel@denx.de> Cc: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2014-11-1121-72/+158
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| * | | ARM: UniPhier: call pin_init() also in the normal bootMasahiro Yamada2014-11-125-7/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_UNIPHIER_SERIAL has been moved to Kconfig and it is defined in ./.config but not in spl/.config, so pin_init() should be called from the normal image so that UART works correctly. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | ARM: UniPhier: consolidate board_postclk_init() functionMasahiro Yamada2014-11-127-50/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit merges arch/arm/cpu/armv7/uniphier/ph1-*/board_postclk_init.c to arch/arm/cpu/armv7/uniphier/board_postclk_init.c Because PH1-Pro4 does not have the BCU block, add __weak to bcu_init(). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | ARM: UniPhier: add set_pinsel macro for use in assembly codeMasahiro Yamada2014-11-121-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function sg_set_pinsel is useful for switching I/O pins but it can be only used in C code. This commit adds a simple macro that is available in asm code. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | usb: UniPhier: add UniPhier on-chip EHCI host driver supportMasahiro Yamada2014-11-125-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support EHCI host driver used on Panasonic UniPhier platform. Since Device Tree is not supported on UniPhier yet, the base address of USB cores are passed from board files (platdevice.c). TODO for me: Move the base address to device trees. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Marek Vasut <marex@denx.de>
| * | | ARM: UniPhier: add MIO register fileMasahiro Yamada2014-11-121-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds register defines of MIO (Media I/O) block of UniPhier platform. This file is necessary to control the reset signals of the USB cores. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | ARM: UniPhier: add EHCI host pin settings for PH1-Pro4Masahiro Yamada2014-11-121-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | These IO pins are necessary for port power control and over current detect. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | ARM: UniPhier: move DDR related configuration to KconfigMasahiro Yamada2014-11-128-19/+27
| | | | | | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | ARM: UniPhier: reset on-board devices on start-upMasahiro Yamada2014-11-123-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a support card is attached to the main board, the on-board SMSC9118 LAN controller is available. It must be kept in reset state for a while on start-up. When the board is kicked via a debbuger rather than pushing the hardware reset button, on-board chips are not reset; in this case the reset signals should be asserted by software. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | | Revert "lib: bootm: add missing include"Michal Simek2014-11-111-1/+0
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a MIME GnuPG-signed message. If you see this text, it means that your E-mail or Usenet software does not support MIME signed messages. The Internet standard for MIME PGP messages, RFC 2015, was published in 1996. To open this message correctly you will need to install E-mail or Usenet software that supports modern Internet standards. This reverts commit 1e96220a5687efae2aed45ce56e143336c40d0a7. Remove duplicated vxworks.h header. The same change was done by "ARM: prevent compiler warnings from bootm.c" (sha1: 8d196e52b58d1e50a80c2f5067b201cda521c75c) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-i2cTom Rini2014-11-101-0/+2
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| * | | ppc4xx: Handle i2c stuck on combined xferDirk Eibach2014-11-101-0/+2
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ppc4xx i2c master gets stuck on errors while repeated start is active. Can be easily reproduced by "i2c md" on an unpopulated i2c address. There is not stop condition given, scl remains pulled low. The only way out seems to be doing a stop manually and then a soft reset. Signed-off-by: Dirk Eibach <dirk.eibach@gdsys.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* | | Merge branch 'master' of git://git.denx.de/u-boot-blackfinTom Rini2014-11-101-0/+2
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| * | | bfin: make the CPU macro of LDR target more genenricSonic Zhang2014-11-101-0/+2
| |/ / | | | | | | | | | | | | | | | Remove BFIN from the CPU macro in Makefile. Signed-off-by: Sonic Zhang <sonic.zhang@analog.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2014-11-106-1/+257
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| * | | gic: fixed compilation error in GICv2 wait for interrupt macroYehuda Yitschak2014-10-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | a hexadicemal value was missing the "0x" prefix which caused assembler error Signed-off-by: Yehuda Yitschak <yehuday@marvell.com>
| * | | arm: debug: adjust for U-BootMasahiro Yamada2014-10-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because CONFIG_MMU is never defined in U-Boot, the non-MMU code in debug.S is always used. Unfortunately, the number of arguments of the addruart macro in Linux is different between MMU and non-MMU. This causes a build error when importing some debug macros using the third argument. (For ex. arch/arm/include/debug/exynos.S) Pass the third argument to the non-MMU addruart to avoid such a problem. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Tested-by: Przemyslaw Marczak <p.marczak@samsung.com>
| * | | arm: debug: add Kconfig entries for lowlevel debugMasahiro Yamada2014-10-263-0/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have not had a good method to debug the early boot stage such as lowlevel_init function. I guess developers generally use dedicated debuggers for that, but it is difficult in some cases. (For example, my debugger cannot connect to the ARM processor when it is in the secure state. It sometimes happens when I need to debug the early boot stage on ARM SoCs with secure extension.) The low level debug feature in Linux would be also helpful for U-boot when we are stucking in nasty problems where the console is not available yet. You have to enable CONFIG_DEBUG_LL to use this feature. For now, only 8250-compatible UART devices are supported. You can add a header file under arch/arm/include/debug/ directory to support your UART device if necessary. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | arm: debug: replace license blocks with SPDXMasahiro Yamada2014-10-262-6/+2
| | | | | | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | arm: debug: import debug files from Linux 3.16Masahiro Yamada2014-10-262-0/+192
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot does not have arch/arm/kernel, include/uapi directories, This commit copies files as follows: Location in Linux -> Location in U-Boot arch/arm/kernel/debug.S -> arch/arm/lib/debug.S arch/arm/include/debug/8250.S -> arch/arm/include/debug/8250.S include/uapi/linux/serial_reg.h -> include/linux/serial_reg.h Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | | ARM: MXS: fix Uninitialized variable errorWolfgang Denk2014-11-101-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cppcheck reports: [arch/arm/cpu/arm926ejs/mxs/timer.c:96]: (error) Uninitialized variable: now Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de>
* | | | cppcheck cleanup: fix nullPointer errorsWolfgang Denk2014-11-076-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are a number of places where U-Boot intentionally and legally accesses physical address 0x0000, for example when installing exception vectors on systems where these are located in low memory. Add "cppcheck-suppress nullPointer" comments to silence cppcheck where this is intentional and legal. Signed-off-by: Wolfgang Denk <wd@denx.de>
* | | | sandbox: init cli for -cRabin Vincent2014-11-071-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sandbox crashes if a variable is set in the -c command, because hush's top_vars is not allocated. Call cli_init() from sandbox to ensure this is done before we execute the -c command. $ ./u-boot -c 'a=1' ... Segmentation fault (core dumped) Signed-off-by: Rabin Vincent <rabin@rab.in> Acked-by: Simon Glass <sjg@chromium.org) Tested-by: Simon Glass <sjg@chromium.org)
* | | | Merge git://git.denx.de/u-boot-tiTom Rini2014-11-077-9/+19
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| * | | omap3: cm-t3517: add basic board supportIgor Grinberg2014-11-061-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CompuLab cm-t3517 is Computer on Module (CoM) based on AM3517 SoC. Features: up to 256MB DDR2, up to 512MB NAND, USB hub, mUSB, WiFi, BT, Analog audio codec, touch screen controller, LED. Add basic support including: LED, Serial console, NAND, MMC, GPIO, I2C, 256MB DRAM. Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
| * | | am335x: make get_board_rev() function weakIgor Grinberg2014-11-062-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current get_board_rev() function returns a hard coded value which is obviously incorrect for the majority of boards. Allow boards to provide a correct implementation by making this function weak. In addition open code the trivial and useless BOARD_REV_ID define and adjust the comment. Signed-off-by: Igor Grinberg <grinberg@compulab.co.il> Cc: Tom Rini <trini@ti.com>
| * | | net: keystone_net: add Keystone2 K2L SoC supportKhoronzhuk, Ivan2014-11-051-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Keystone2 Lamar SoC uses the same keystone net driver. This patch adds opportunity to use it by K2L SoCs. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | net: keystone_serdes: add keystone K2L SoC supportKhoronzhuk, Ivan2014-11-051-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Keystone2 Lamar SoC uses the same keystone SerDes driver. All Keystone2 EVM boards currently use SerDes driver, so move CONFIG_TI_KEYSTONE_SERDES to common configuration file. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
| * | | ARM: keystone2: keysonte_nav: add support for K2L SoCKhoronzhuk, Ivan2014-11-053-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Keystone2 Lamar SoC uses the same keystone navigator. Move queue numbers to common hardware file, as all Keystone2 SoCs have the same ones. Acked-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
* | | | Merge branch 'rmobile' of git://www.denx.de/git/u-boot-shTom Rini2014-11-053-9/+9
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| * | | | arm: rmobile: alt: Add external RAM bootNobuhiro Iwamatsu2014-11-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_RMOBILE_EXTRAM_BOOT is enabled, U-Boot is booted from External RAM. The default boot address is 0x70000000. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | arm: rmobile: koelsch: Add external RAM bootNobuhiro Iwamatsu2014-11-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_RMOBILE_EXTRAM_BOOT is enabled, U-Boot is booted from External RAM. The default boot address is 0x70000000. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | arm: rmobile: lager: Add external RAM bootNobuhiro Iwamatsu2014-11-041-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_RMOBILE_EXTRAM_BOOT is enabled, U-Boot is booted from External RAM. The default boot address is 0xB0000000. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | arm: rmobile: lager: Fix change of the CPU frequencyNobuhiro Iwamatsu2014-11-041-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The change of the CPU frequency is waited for until PLL0ST of the PLLECR is set to 1. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | | | arm: rmobile: r8a7790: Update initialize L2 cacheNobuhiro Iwamatsu2014-11-041-9/+2
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initialization of L2CTLR[5] was set only as R8A7790 by commit 237faf095fb43abbed6e40266ef7efccc8b9308b. However, initialization of cash needs to be performed continuously. This changes into the processing which continues initialization of L2CTLR[5] into L2CTLR cash and performs it. Signed-off-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2014-11-058-14/+137
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| * | | imx: mx6 sabreauto: Add board support for USB EHCIYe.Li2014-11-032-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On mx6 sabreauto board, there are two USB ports: 0: OTG 1: HOST The EHCI driver is enabled for this board, but the IOMUX and VBUS power control is not implemented, which cause both USB port failed to work. This patch fix the problem by adding the board support codes. Since the power control uses the GPIO pin from port expander MAX7310, the PCA953X driver is enabled for accessing the MAX7310. The ID pin of OTG Port needs to configure the GPR1 bit 13 for selecting its daisy chain. Add a new function "imx_iomux_set_gpr_register" to handle GPR register setting. Signed-off-by: Ye.Li <B37916@freescale.com>
| * | | imx: mx6sl: Add IOMUX setting for USDHC1-3Ye.Li2014-11-031-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | Set the USDHC1-3 IOMUX settings which are used for mx6slevk board. Signed-off-by: Ye.Li <B37916@freescale.com>
| * | | imx: mx6sl: Set the preclk clock source to OSC 24MhzYe.Li2014-11-031-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For MX6SL, uses the OSC 24Mhz as the preclk source in CCM. Align the preclk setting with kernel. Signed-off-by: Ye.Li <B37916@freescale.com>
| * | | imx: mx6: Change the get_ipg_per_clk for OSC 24Mhz sourceYe.Li2014-11-031-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For MX6SL and MX6SX, the perclk can come from OSC 24Mhz source. Fix the get_ipg_per_clk function to support it. Signed-off-by: Ye.Li <B37916@freescale.com>
| * | | imx: mx6sl: Add perclk_clk_sel bit define in CCMYe.Li2014-11-031-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The MX6SL has the perclk_clk_sel to select the perclk source. Add its define in CCM Signed-off-by: Ye.Li <B37916@freescale.com>
| * | | imx: gpt: Add High frequency clock source support for GPTYe.Li2014-11-031-9/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce a new configuration "CONFIG_MXC_GPT_HCLK". When it is set, the GPT will select a high frequency clock as clock source. Otherwise, the GPT will stay to use 32Khz OSC as clock source. In the implementation, since only the GPT on i.MX6 series provide the clock source option for 24Mhz OSC. For others (only i.MX5 and i.MX6 compile the driver), if the configuration is set, the perclk will be selected as clock source. MX6Q/D Rev 1.0 and MX6SL are special in the implementation, because they don't have the 24Mhz OSC clock source option, so also select the perclk for them. For MX6SL, we will set the OSC 24Mhz to perclk in CCM, so eventually the clock comes from OSC 24Mhz. Signed-off-by: Ye.Li <B37916@freescale.com>
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