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* dm: x86: quark: Add an interrupt driverSimon Glass2016-01-244-27/+51
| | | | | | | | | Add a driver for interrupts on quark and move the code currently in cpu_irq_init() into its probe() method. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Use the IRQ device when setting up the mptableSimon Glass2016-01-242-19/+11
| | | | | | | | | Instead of searching for the device tree node, use the IRQ device which has a record of it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* dm: x86: Add a common PIRQ init functionSimon Glass2016-01-242-1/+13
| | | | | | | | | Most x86 interrupt drivers will want to use the standard PIRQ routing and table setup. Put this code in a common function so it can be used by those drivers that want it. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: x86: Set up interrupt routing from interrupt_init()Simon Glass2016-01-247-25/+12
| | | | | | | | | | | | | | | At present interrupt routing is set up from arch_misc_init(). We can do it a little later instead, in interrupt_init(). This removes the manual pirq_init() call. Where the platform does not have an interrupt router defined in its device tree, no error is generated. Some platforms do not have this. Drop pirq_init() since it is no-longer used. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* dm: x86: Create a driver for x86 interruptsSimon Glass2016-01-241-0/+25
| | | | | | | | | | | | | | | | It seems likely that at some point we will want a generic interrupt uclass. But this is a big undertaking as it involves unifying code across multiple architectures. As a first step, create a simple IRQ uclass and a driver for x86. This can be generalised later as required. Adjust pirq_init() to probe this driver, which has the effect of creating routing tables and setting up the interrupt routing. This is a start towards making interrupts fit better with driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: x86: spi: Convert ICH SPI driver to driver model PCI APISimon Glass2016-01-2412-326/+425
| | | | | | | | | | | | | | | | | | | | | | | | | At present this SPI driver works by searching the PCI buses for its peripheral. It also uses the legacy PCI API. In addition the driver has code to determine the type of Intel PCH that is used (version 7 or version 9). Now that we have proper PCH drivers we can use those to obtain the information we need. While the device tree has a node for the SPI peripheral it is not in the right place. It should be on the PCI bus as a sub-peripheral of the LPC device. Update the device tree files to show the SPI controller within the PCH, so that PCI access works as expected. This patch includes Bin's fix-up patch from here: https://patchwork.ozlabs.org/patch/569478/ Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* dm: Expand the uclass for Platform Controller Hubs (PCH)Simon Glass2016-01-242-31/+0
| | | | | | | | | | | | | | A Platform Controller Hub is an Intel concept - it is like the peripherals on an SoC and is often in a separate chip from the CPU. The chip is typically found on the first PCI bus and integrates multiple devices. We have a very simple uclass to support PCHs. Add a few operations, such as setting up the devices on the PCH and finding the SPI controller base address. Also move it into drivers/pch/ since we will be adding a few PCH drivers. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* rockchip: Add support for Raxda Rock 2Simon Glass2016-01-213-0/+13
| | | | | | | | | | | | This board includes an RK3288 SoC on a SOM. It can be mounted on a base-board which provides a wide range of peripherals. So far this is verified to boot to a prompt from a microSD card. The serial console works as well as HDMI. Thanks to Tom Cubie for sending me a board. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: rock2: dts: Make changes for U-BootSimon Glass2016-01-211-0/+21
| | | | | | Add the required pre-relocation tags and SDRAM init information for U-Boot. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: rock2: Bring in device tree files from LinuxSimon Glass2016-01-212-0/+458
| | | | | | | Bring in the current device tree files for rock2 from linux/next commit 719d6c1. Hopefully this is the latest one. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: dts: Sync up SPDIF node with LinuxSimon Glass2016-01-211-0/+21
| | | | | | | This has been added and we have references to it in the rock2 board. Add this node. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: jerry: Enable EDP and HDMI video outputSimon Glass2016-01-212-0/+6
| | | | | | | | | | | Enable these devices using the VOPL video output device. We explicitly disable VOPB in the device tree to avoid it taking over. Since this device has an LCD display this comes up by default. If the display fails for some reason then it will attempt to use HDMI. It is possible to force it to fail (and thus fall back to HDMI) by puting 'return -EPERM' at the top of rk_edp_probe(). For now there is no easy way to select between the two. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: spl: Support full-speed CPU in SPLSimon Glass2016-01-215-0/+64
| | | | | | | | Add a feature which speeds up the CPU to full speed in SPL to minimise boot time. This is only supported for certain boards (at present only jerry). Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: jerry: Fix the SDRAM timingSimon Glass2016-01-211-1/+1
| | | | | | | There is a minor error in the SDRAM timing. It does not seem to affect anything so far. Fix it just in case. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: spl: Drop MMC support code when not neededSimon Glass2016-01-211-2/+4
| | | | | | When the board does not use MMC SPL this code is a waste of space. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Tidy up the register-access macrosSimon Glass2016-01-211-3/+4
| | | | | | | | | These work reasonable well, but there are a few errors: - Brackets should be used to avoid unexpected side-effects - When setting bits, the corresponding upper 16 bits should be set also Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: sdram: Use syscon_get_first_range() where possibleSimon Glass2016-01-211-14/+3
| | | | | | | This is a shortcut to obtaining a register address. Use it where possible, to simplify the code. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: sdram: Tidy up a few commentsSimon Glass2016-01-211-2/+2
| | | | | | Fix spaces in two comments in this file. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Add a simple 'clock' commandSimon Glass2016-01-211-0/+24
| | | | | | Add a command that displays the PLLs and their current rate. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Don't skip low-level initSimon Glass2016-01-212-0/+8
| | | | | | | At present the low-level init is skipped on rockchip. Among other things this means that the instruction cache is left disabled. Fix this. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: video: Add a video-output driverSimon Glass2016-01-211-0/+349
| | | | | | | | Some rockchip SoCs include video output (VOP). Add a driver to support this. It can output via a display driver (UCLASS_DISPLAY) and currently HDMI and eDP are supported. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: video: Add a display driver for rockchip eDPSimon Glass2016-01-211-0/+636
| | | | | | | Some Rockchip SoCs support embedded DisplayPort output. Add a display driver for this so that these displays can be used on supported boards. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: video: Add a display driver for rockchip HDMISimon Glass2016-01-211-0/+456
| | | | | | | | | | | | Some Rockchip SoCs support HDMI output. Add a display driver for this so that these displays can be used on supported boards. Unfortunately this driver is not fully functional. It cannot reliably read EDID information over HDMI. This seems to be due to the clocks being incorrect - the I2C bus speed appears to be up to 100x slower than the clock settings indicate. The root cause may be in the clock logic. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Rename the CRU_MODE_CON fieldsSimon Glass2016-01-211-29/+29
| | | | | | These should match the datasheet naming. Adjust them. Signed-off-by: Simon Glass <sjg@chromium.org>
* pwm: rockchip: Add a PWM driver for Rockchip SoCsSimon Glass2016-01-211-0/+41
| | | | | | Add a simple driver which implements the standard PWM uclass interface. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: jerry: Enable the Chrome OS ECSimon Glass2016-01-211-0/+4
| | | | | | Turn on the EC and enable the keyboard. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: clk: Make rkclk_get_clk() SoC-specificSimon Glass2016-01-212-29/+0
| | | | | | | | | | | | The current method assumes that clocks are numbered from 0 and we can determine a clock by its number. It is safer to use an ID in the clock's platform data to avoid the situation where another clock is bound before the one we expect. Move the existing code into rk3036 since it still works there. Add a new implementation for rk3288. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: reset: Use the rk_clr/setreg() interfaceSimon Glass2016-01-211-2/+2
| | | | | | Use this function in preference to the macro. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: sdram: Use the rk_clr/setreg() interfaceSimon Glass2016-01-211-4/+3
| | | | | | Use this function in preference to the macro. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: clock: Add a function to find a clock by IDSimon Glass2016-01-211-0/+12
| | | | | | | | The current approach of using uclass_get_device() is error-prone. Another clock (for example a fixed-clock) may cause it to break. Add a function that does a proper search. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: jerry: Disable pmic-int-1 setup to avoid a hangSimon Glass2016-01-211-1/+4
| | | | | | | This hangs when activated (by probing the PMIC). Disable it for now until we understand the root cause. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Use pwrseq for MMC start-up on jerrySimon Glass2016-01-211-4/+11
| | | | | | | This is defined in the device tree in Linux. Copy over the settings so that this can be used instead of hard-coding the reset line. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Convert the PMU IOMUX registers into an arraySimon Glass2016-01-211-4/+8
| | | | | | | | | This is easier to deal with when using generic code since it allows us to use a register index instead of naming each register. Adjust it, adding an enum to improve readability. Signed-off-by: Simon Glass <sjg@chromium.org>
* rockchip: Avoid using MMC code when not booting from MMCSimon Glass2016-01-211-0/+2
| | | | | | This saves some code space in SPL which is useful on jerry. Signed-off-by: Simon Glass <sjg@chromium.org>
* ARM: bootm: Try to use relocated ramdiskJeffy Chen2016-01-211-1/+11
| | | | | | | | | After boot_ramdisk_high(), ramdisk would be relocated to initrd_start & initrd_end, so use them instead of rd_start & rd_end. Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-dmTom Rini2016-01-2114-7/+58
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| * dm: video: test: Add tests for the video uclassSimon Glass2016-01-201-0/+7
| | | | | | | | | | | | | | | | | | Add tests that check that the video console is working correcty. Also check that text output produces the expected result. Test coverage includes character output, wrapping and scrolling. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
| * dm: video: sandbox: Convert sandbox to use driver model for videoSimon Glass2016-01-201-0/+1
| | | | | | | | | | | | | | | | Now that driver model support is available, convert sandbox over to use it. We can remove a few of the special hooks that sandbox currently has. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de>
| * arm: ls1021atwr: Enable driver model lpuart serial driverBin Meng2016-01-202-1/+17
| | | | | | | | | | | | | | | | | | | | | | Convert ls1021atwr_nor_lpuart to driver model support. As a start, enable lpuart serial port driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Alison Wang <alison.wang@nxp.com> Tested-by: Alison Wang <alison.wang@nxp.com> Acked-by: Simon Glass <sjg@chromium.org>
| * arm: ls1021atwr: Split off board device treeBin Meng2016-01-203-3/+18
| | | | | | | | | | | | | | Move /chosen node out of the board device tree. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * arm: ls1021atwr: Convert to driver model and enable serial supportBin Meng2016-01-202-4/+4
| | | | | | | | | | | | | | | | Convert ls1021atwr_nor to driver model support. As a start, enable ns16550 serial port driver. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * arm: dts: dra7-evm: add tick-timer to chosen nodeMugunthan V N2016-01-201-0/+1
| | | | | | | | | | | | | | Specify timer2 to be used as tick-timer in chosen node. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * arm: dts: dra72-evm: add tick-timer to chosen nodeMugunthan V N2016-01-201-0/+1
| | | | | | | | | | | | | | Specify timer2 to be used as tick-timer in chosen node. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * arm: dts: am335x-evm: add tick-timer to chosen nodeMugunthan V N2016-01-201-0/+1
| | | | | | | | | | | | | | Specify timer2 to be used as tick-timer in chosen node. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * arm: dts: am335x-boneblack: add tick-timer to chosen nodeMugunthan V N2016-01-201-0/+1
| | | | | | | | | | | | | | Specify which timer to be used as tick-timer in chosen node. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * arm: dts: am437x-gp-evm: add tick-timer to chosen nodeMugunthan V N2016-01-201-0/+1
| | | | | | | | | | | | | | Specify which timer to be used as tick-timer in chosen node. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * arm: dts: am437x-sk-evm: add tick-timer to chosen nodeMugunthan V N2016-01-201-0/+1
| | | | | | | | | | | | | | Specify which timer to be used as tick-timer in chosen node. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
| * arm: omap-common: do not build timer when CONFIG_TIMER definedMugunthan V N2016-01-201-0/+6
| | | | | | | | | | | | | | | | | | | | To prepare timer driver to DM/DT conversion do not build the exiting timer driver when CONFIG_TIMER is defined. But since omap's SPL doesn't support DM yet so built timer driver only for SPL build when CONFIG_TIMER is defined. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2c; branch 'master' of ↵Tom Rini2016-01-213-12/+16
|\ \ | | | | | | | | | git://git.denx.de/u-boot-nds32
| * | nds32: Fix compile error.rick2016-01-213-12/+16
| | | | | | | | | | | | | | | | | | | | | Fix compile error with gcc 4.9.3 Signed-off-by: rick <rick@andestech.com> Cc: Andes <uboot@andestech.com>
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