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path: root/arch/x86/cpu/ivybridge/sdram.c
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* x86: ivybridge: Enable the MRC cacheBin Meng2015-10-211-8/+2
* x86: ivybridge: Measure the MRC code execution timeSimon Glass2015-10-211-0/+3
* x86: ivybridge: Check the RTC return valueSimon Glass2015-10-211-3/+10
* x86: ivybridge: Use 'ret' instead of 'rcode'Simon Glass2015-10-211-8/+8
* x86: ivybridge: Correct two typos for MRCBin Meng2015-10-211-2/+2
* x86: Use struct mrc_region to describe a mrc regionBin Meng2015-10-211-1/+1
* x86: ivybridge: Use APIs provided in the mrccache libBin Meng2015-10-211-108/+4
* x86: Move mrccache.[c|h] to a common placeBin Meng2015-10-211-1/+1
* x86: Enable DM RTC support for all x86 boardsBin Meng2015-07-281-8/+24
* x86: ivybridge: Use reset_cpu()Simon Glass2015-04-291-2/+1
* dm: x86: spi: Convert ICH SPI driver to driver modelSimon Glass2015-04-181-7/+10
* x86: Add a x86_ prefix to the x86-specific PCI functionsSimon Glass2015-04-161-10/+10
* x86: Rename MMCONF_BASE_ADDRESS and make it common across x86Simon Glass2015-02-051-1/+1
* x86: Implement a cache for Memory Reference Code parametersSimon Glass2015-01-241-0/+253
* x86: ivybridge: Request MTRRs for DRAM regionsSimon Glass2015-01-131-0/+10
* x86: Use consistent name XXX_ADDR for binary blob flash addressBin Meng2014-12-181-1/+1
* x86: ivybridge: Implement SDRAM initSimon Glass2014-11-211-1/+552
* x86: Add chromebook_link boardSimon Glass2014-11-211-0/+20
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