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* | | sunxi: Match sun4i, sun6i, sun9i CCI definitions for NAND and DMARoy Spliet2015-05-293-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Make sure definitions for NAND clock and DMA gate bits are the same across boards. Signed-off-by: Roy Spliet <r.spliet@ultimaker.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | sunxi: Add DMA definitionsRoy Spliet2015-05-292-0/+84
| | | | | | | | | | | | | | | | | | Signed-off-by: Roy Spliet <r.spliet@ultimaker.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | | sun9i: Basic sun9i (A80) supportHans de Goede2015-05-291-0/+1
|/ / | | | | | | | | | | | | Add initial sun9i (A80) support, only uart + mmc are supported for now. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | ARMv7M: add STM32F1 supportMatt Porter2015-05-282-0/+234
|/ | | | | | Add ARMv7M STM32F1 support including clocks, timer, gpio, and flash. Signed-off-by: Matt Porter <mporter@konsulko.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-05-269-28/+52
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| * i2c, mxc: rework i2c base address names for different SoCsHeiko Schocher2015-05-264-7/+7
| | | | | | | | | | | | | | rework and unify i2c address names for different SoCs, which use the mxc_i2c driver. Signed-off-by: Heiko Schocher <hs@denx.de>
| * arm, imx6, i2c: add I2C4 for MX6DLHeiko Schocher2015-05-262-0/+3
| | | | | | | | | | | | add I2C4 modul for MX6DL based boards. Signed-off-by: Heiko Schocher <hs@denx.de>
| * imx: dma: correct MXS_DMA_ALIGNMENTPeng Fan2015-05-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We should not hardcode MXS_DMA_ALIGNMENT to 32, since we can not guarantee that socs' cache line size is 32 bytes. If on chips whose cache line size is 64 bytes, error occurs: " NAND: ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 ERROR: v7_dcache_inval_range - stop address is not aligned - 0xbdf1f4a0 ERROR: v7_dcache_inval_range - start address is not aligned - 0xbdf1d1a0 " Align MXS_DMA_ALIGNMENT with ARCH_DMA_MINALIGN whose value is same to CONFIG_SYS_CACHELINE_SIZE if CONFIG_SYS_CACHELINE_SIZE defined. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Marek Vasut <marex@denx.de>
| * imx: mx6: add get_cpu_temp_grade to obtain cpu temperature grade from OTPTim Harvey2015-05-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MX6 has a temperature grade defined by OCOTP_MEM0[7:6] which is at 0x480 in the Fusemap Description Table in the reference manual. Return this value as well as min/max temperature based on the value. Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the their Fusemap Description Table however Freescale has confirmed that these eFUSE bits match the description within the IMX6DQRM and that they will be added to the next revision of the respective reference manuals. This has been tested with IMX6 Automative and Industrial parts. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * imx: mx6: add get_cpu_speed_grade_hz func to return MHz speed grade from OTPTim Harvey2015-05-191-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The IMX6 has four different speed grades determined by eFUSE SPEED_GRADING indicated by OCOTP_CFG3[17:16] which is at 0x440 in the Fusemap Description Table. Return this frequency so that it can be used elsewhere. Note that the IMX6SDLRM and the IMX6SXRM do not indicate this in the their Fusemap Description Table however Freescale has confirmed that these eFUSE bits match the description within the IMX6DQRM and that they will be added to the next revision of the respective reference manuals. These have been tested with IMX6 Quad/Solo/Dual-light 800Mhz and 1GHz grades. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * mx6: add OTP bank1 registersTim Harvey2015-05-191-0/+19
| | | | | | | | Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * imx: mx6sx enable SION for i2c pin muxPeng Fan2015-05-191-20/+20
| | | | | | | | | | | | | | | | | | | | | | | | Enable IOMUX_CONFIG_SION for all I2C pin mux settings, otherwise we will get erros when doing i2c operations. error log like the following: " wait_for_sr_state: failed sr=81 cr=a0 state=2020 i2c_init_transfer: failed for chip 0xb retry=1 " Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2015-05-221-146/+0
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| * | arm/ls1021a: Remove ccsr_ddr from immap_ls102xa.hYork Sun2015-05-201-146/+0
| |/ | | | | | | | | | | | | | | | | ccsr_ddr structure is already defined in fsl_immap.h. Remove this duplicated define. Move fixed timing into ls1021atwr.h. Signed-off-by: York Sun <yorksun@freescale.com> CC: Alison Wang <alison.wang@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com>
* | sunxi: video: Fix lvds panel support for sun6i+Hans de Goede2015-05-192-0/+15
| | | | | | | | | | | | | | | | | | We've never tested the lvds panel support on sun6i+ SoCs until now, and unsurprisingly the lvds code needed some fixes to work on my ga10h A33 tablet with lvds panel. This makes the panel on that tablet actually work. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | sunxi: Make DRAM_ODT_EN Kconfig setting a boolHans de Goede2015-05-192-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make DRAM_ODT_EN Kconfig setting a bool, add a separate DRAM_ODT_CORRECTION setting for A23 SoCs and use DRAM_ODT_EN Kconfig everywhere instead of only in dram_sun4i.c and hardcoding odt_en elsewhere. Note this commit makes no functional changes for existing boards, its purpose is to allow changing the odt_en value on future A33 boards. For sun4i/sun5i/sun7i boards which set DRAM_ODT_EN=y (which no defconfigs currently do) this patch turns on odt for both the DQ and the DQS lines, whereas previously it was possibly (but not desirable) to turn odt on only for one of them by setting the in DRAM_ODT_EN option to 1 or 2 instead of 3. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
* | sunxi: add support for UART2 on A23/A33Laurent Itti2015-05-191-0/+1
|/ | | | | | | | | | Add support for UART2 (2-pin version but note that RTS/CTS pins are available pn that port for possible future use), can be selected in config by using CONFIG_CONS_INDEX=3 Signed-off-by: Laurent Itti <laurentitti@gmail.com> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* mx6: Set shared override bit in PL310 AUX_CTRL registerFabio Estevam2015-05-151-0/+2
| | | | | | | | | | | | | | | | | | | | | | Having bit 22 cleared in the PL310 Auxiliary Control register (shared attribute override enable) has the side effect of transforming Normal Shared Non-cacheable reads into Cacheable no-allocate reads. Coherent DMA buffers in Linux always have a Cacheable alias via the kernel linear mapping and the processor can speculatively load cache lines into the PL310 controller. With bit 22 cleared, Non-cacheable reads would unexpectedly hit such cache lines leading to buffer corruption. This was inspired by a patch from Catalin Marinas [1] and also from recent discussions in the linux-arm-kernel list [2] where Russell King and Rob Herring suggested that bootloaders should initialize the cache. [1] http://lists.infradead.org/pipermail/linux-arm-kernel/2010-November/031810.html [2] https://lkml.org/lkml/2015/2/20/199 Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com>
* i2c: mxc: refactor i2c driver and support dmPeng Fan2015-05-141-5/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Introduce a new structure `struct mxc_i2c_bus`, this structure will used for non-DM and DM. 2. Remove `struct mxc_i2c_regs` structure, but use register offset to access registers based on `base` entry of `struct mxc_i2c_bus`. 3. Remove most `#ifdef I2C_QUIRK_REG`. Using driver_data to contain platform flags. A new flag is introduced, I2C_QUIRK_FLAG. 4. Most functions use `struct mxc_i2c_bus` as one of the parameters. Make most functions common to DM and non-DM, try to avoid duplicated code. 5. Support DM, but pinctrl is not included. Pinmux setting is still set by setup_i2c, but we do not need bus_i2c_init for DM. 6. struct i2c_parms and struct sram_data are removed. 7. Remove bus_i2c_read bus_i2c_write prototype in header file. The frist paramter of bus_i2c_init is modified to i2c index. Add new prototype i2c_idle_bus and force_bus_idle. Since bus_i2c_init is not good for DM I2C and pinctrl is missed, we use a weak function for i2c_idle_bus. Board file take the responsibility to implement this function, like this: " int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus) { if (i2c_bus->index == 0) force_bus_idle(i2c_pads_info0); else if (i2c_bus->index == 1) force_bus_idle(i2c_pads_info1); else xxxxxx } " 8. Introduce a weak function, enable_i2c_clk 9. Tested on an i.MX7 platform. Log info: => dm tree Class Probed Name ---------------------------------------- root [ + ] root_driver simple_bus [ ] |-- soc simple_bus [ ] | |-- aips-bus@30000000 simple_bus [ ] | | |-- anatop@30360000 simple_bus [ ] | | `-- snvs@30370000 simple_bus [ ] | |-- aips-bus@30400000 simple_bus [ ] | `-- aips-bus@30800000 i2c [ ] | |-- i2c@30a20000 i2c [ ] | `-- i2c@30a40000 simple_bus [ ] `-- regulators => i2c dev 0 Setting bus to 0 => i2c probe Valid chip addresses: 08 50 => i2c md 8 31 0031: 08 08 08 08 08 08 08 08 08 08 08 08 08 08 08 08 Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Simon Glass <sjg@chromium.org>
* imx: mx27 move GPIO_PORTx to gpio.hPeng Fan2015-05-142-22/+20
| | | | | | | | | | | | | | These GPIO_PORTx macros should be in gpio.h, but not in imx-regs.h. Also, imx-regs.h and iomux-v3.h has same macro defintion for GPIO_PORTx, and both of them are included in mxc_i2c.c(include mxc_i2c.h). This will incur build warnings with macro redefinition. Since iomux-v3.h is not compatible with mx27, we can not simply include iomux-v3.h for mx27, so move the GPIO_PORTx to gpio.h to fix the build warning. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* arm: Add a prototype for save_boot_params_ret()Simon Glass2015-05-141-0/+16
| | | | | | | | It is convenient for some boards to implement save_boot_params() in C rather than assembler. Provide a way to return in this case. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
* sunxi: ohci: Add ohci usb host controller supportHans de Goede2015-05-142-0/+4
| | | | | | | | | | | | | This commit adds support for the OHCI companion controller, which makes usb-1 devices directly plugged into to usb root port work. Note for now this switches usb-keyboard support for sunxi back from int-queue support to the old interrupt polling method. Adding int-queue support to the ohci code and switching back to int-queue support is in the works. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* ARM: tegra: Enable SMMU when going non-secureThierry Reding2015-05-131-0/+2
| | | | | | | | | | | | | Make sure to enable the SMMU when booting the kernel in non-secure mode. This is necessary because some of the SMMU registers are restricted to TrustZone-secured requestors, hence the kernel wouldn't be able to turn the SMMU on. At the same time, enable translation for all memory clients for the same reasons. The kernel will still be able to control SMMU IOVA translation using the per-SWGROUP enable bits. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra124: Reserve secure RAM using MC_SECURITY_CFG{0, 1}_0Ian Campbell2015-05-131-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | These registers can be used to prevent non-secure world from accessing a megabyte aligned region of RAM, use them to protect the u-boot secure monitor code. At first I tried to do this from s_init(), however this inexplicably causes u-boot's networking (e.g. DHCP) to fail, while networking under Linux was fine. So instead I have added a new weak arch function protect_secure_section() called from relocate_secure_section() and reserved the region there. This is better overall since it defers the reservation until after the sec vs. non-sec decision (which can be influenced by an envvar) has been made when booting the os. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> [Jan: tiny style adjustment] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra124: Add PSCI support for Tegra124Jan Kiszka2015-05-131-0/+6
| | | | | | | | | | | | | | | This is based on Thierry Reding's work and uses Ian Campell's preparatory patches. It comes with full support for CPU_ON/OFF PSCI services. The algorithm used in this version for turning CPUs on and off was proposed by Peter De Schrijver and Thierry Reding in http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/210881. It consists of first enabling CPU1..3 via the PMC, just to powergate them again with the help of the Flow Controller. Once the Flow Controller is in place, we can leave the PMC alone while processing CPU_ON and CPU_OFF PSCI requests. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: Add board-specific initialization hook for PSCIJan Kiszka2015-05-131-0/+1
| | | | | | | | Tegra boards will have to initialize power management for the PSCI support this way. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Make tegra_powergate_power_on publicJan Kiszka2015-05-131-0/+1
| | | | | | | | | | | Will be used for unpowergating CPUs. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
* virt-dt: Allow reservation of secure region when in a RAM carveoutJan Kiszka2015-05-131-0/+1
| | | | | | | | | | | | | | | | In this case the secure code lives in RAM, and hence the memory node in the device tree needs to be adjusted. This avoids that the OS will map and possibly access the reservation. Add support for setting CONFIG_ARMV7_SECURE_RESERVE_SIZE to carve out such a region. We only support cutting off memory from the beginning or the end of a RAM bank as we do not want to increase their number (which would happen if punching a hole) for simplicity reasons This will be used in a subsequent patch for Jetson-TK1. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra124: Add more registers to struct mc_ctlrIan Campbell2015-05-131-2/+33
| | | | | | | | | | | | | I will need mc_security_cfg0/1 in a future patch and I added the rest while debugging, so thought I might as well commit them. Signed-off-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Thierry Reding <treding@nvidia.com> Tested-by: Thierry Reding <treding@nvidia.com> Tested-by: Ian Campbell <ijc@hellion.org.uk> Signed-off-by: Tom Warren <twarren@nvidia.com>
* ARM: Clean up CONFIG_ARMV7_NONSEC/VIRT/PSCI conditionsJan Kiszka2015-05-131-2/+2
| | | | | | | | | | | | | | CONFIG_ARMV7_VIRT depends on CONFIG_ARMV7_NONSEC, thus doesn't need to be taken into account additionally. CONFIG_ARMV7_PSCI is only set on boards that support CONFIG_ARMV7_NONSEC, and it only works on those. CC: Tang Yuantian <Yuantian.Tang@freescale.com> CC: York Sun <yorksun@freescale.com> CC: Steve Rae <srae@broadcom.com> CC: Andre Przywara <andre.przywara@linaro.org> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Tested-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra124: video: Add full link training for eDPSimon Glass2015-05-131-0/+4
| | | | | | | | | Add full link training as a fallback in case the fast link training fails. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: video: support eDP displays on Tegra124 devicesSimon Glass2015-05-131-0/+58
| | | | | | | | | Connect up the clocks and the eDP driver to make these displays work with Tegra124-based devices. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Move display controller header into commonSimon Glass2015-05-132-11/+54
| | | | | | | Allow this to be used by other Tegra SoCs. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra124: clock: Add display clocks and functionsSimon Glass2015-05-133-4/+35
| | | | | | | | Add functions to provide access to the display clocks on Tegra124 including setting the clock rate for an EDP display. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: clock: Split the clock source code into a separate functionSimon Glass2015-05-131-0/+11
| | | | | | | | | Create a function which sets the source clock for a peripheral, given the number of mux bits to adjust. This can then be used more generally. For now, don't export it. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: clock: Add checking for invalid clock IDsSimon Glass2015-05-131-0/+3
| | | | | | | | | The get_pll() function can do the wrong thing if passed values that are out of range. Add checks for this and add a function which can return a 'simple' PLL. This can be defined by SoCs with their own clocks. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Provide a function to allow LCD PMIC setupSimon Glass2015-05-131-0/+8
| | | | | | | Some LCDs require a PMIC to be set up - add a function for this. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Add a board ID functionSimon Glass2015-05-131-5/+6
| | | | | | | Add a way of displaying a numeric board ID on start-up. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: pwm: Allow the clock rate to be left as isSimon Glass2015-05-131-1/+1
| | | | | | | | When enabling a PWM, allow the existing clock rate and source to stand unchanged. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* tegra: Move the pwm into tegra-commonSimon Glass2015-05-133-50/+78
| | | | | | | | This is needed for tegra124 also, so make it common and add a header file for tegra124. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* stm32f4: add serial print portkunhuahuang2015-05-101-0/+32
| | | | | | | | | | | | Add the stm32F4 board's serial ports support. User can use it easily. The user only need to edit the number of the usart. The patch also fix the serial print out. Last, this version of patch fix the first patch checkpatch.pl error. Thanks to Kamil Lulko. Signed-off-by: kunhuahuang <huangkunhua@gmail.com>
* ARM: socfpga: move SoC headers to mach-socfpga/include/machMasahiro Yamada2015-05-0713-1061/+0
| | | | | | Move headers to mach-socfpga as well. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Merge git://git.denx.de/u-boot-marvellTom Rini2015-05-053-266/+0
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| * arm: armada-xp: Move SoC headers to mach-mvebu/include/machStefan Roese2015-05-053-266/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Move arch/arm/include/asm/arch-armada-xp/* -> arch/arm/mach-mvebu/include/mach/* Additionally the SYS_SOC is renamed from "armada-xp" to "mvebu". With this change all these files can better be shared with other, newer Mavell MVEBU SoC's. Like the upcoming Armada 38x support. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com> Tested-by: Dirk Eibach <dirk.eibach@gdsys.cc>
* | Merge branch 'master' of git://git.denx.de/u-boot-armTom Rini2015-05-054-3/+90
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| * \ Merge branch 'u-boot/master' into 'u-boot-arm/master'Albert ARIBAUD2015-05-0539-412/+922
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| * | ARMv7 TLB: Fixed TTBR0 and Table Descriptors to allow cachingBryan Brinsko2015-04-161-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | The TTBR0 register and Table Descriptors of the ARMv7 TLB weren't being properly set to allow for the configuration specified caching modes to be active over DRAM. This commit fixes those issues. Signed-off-by: Bryan Brinsko <bryan.brinsko@rockwellcollins.com>
| * | ARM: cpu: Add ARMv7 barrier operations supportValentine Barshak2015-04-161-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This enables ARMv7 barrier operations support when march=armv7-a is enabled. Using CP15 barriers causes U-Boot bootm command crash when transferring control to the loaded image on Renesas R8A7794 Cortex A7 CPU. Using ARMv7 barrier operations instead of the deprecated CP15 barriers helps to avoid these issues. Signed-off-by: Valentine Barshak <valentine.barshak+renesas@cogentembedded.com> Signed-off-by: Vladimir Barinov <vladimir.barinov+renesas@cogentembedded.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
| * | Armv8: Initializing CNTVOFF_EL2David Feng2015-04-161-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Linux-arm64 require that CNTVOFF_EL2 should be programmed with a consistent value on all cpus. Initializing CNTVOFF_EL2 at state transition instead of start.S could prevent potential different value on cpus if ATF exist and u-boot runs at only one cpu. Signed-off-by: David Feng <fenghua@phytium.com.cn>
| * | arm: implement find_next_zero_bit functionVitaly Andrianov2015-04-161-3/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | This commit copies implementation of the find_next_zero_bit() from git://git.denx.de/u-boot.git/arch/mips/include/asm/bitops.h. v2014.07 The function is required to enable MCAST_TFTP support for ARM platforms. Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
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