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* | bitops: introduce BIT() definitionHeiko Schocher2015-09-114-7/+0
| | | | | | | | | | | | | | | | | | | | | | introduce BIT() definition, used in at91_udc gadget driver. Signed-off-by: Heiko Schocher <hs@denx.de> [remove all other occurrences of BIT(x) definition] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Anatolij Gustschin <agust@denx.de>
* | arm: spear: Add command to switch between 1-bit HW ECC and SW BCH4Stefan Roese2015-09-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | This patch adds the "nandecc" command to switch between the SPEAr600 internal 1-bit HW ECC and the 4-bit SW BCH4 ECC. This can be needed to support NAND chips with a stronger ECC than 1-bit, as on the x600. And to dynamically switch between both ECC schemes for backwards compatibility. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Viresh Kumar <viresh.kumar@linaro.org> Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
* | arm: Remove snowball and u8500_href boardsSimon Glass2015-09-111-26/+0
| | | | | | | | | | | | | | These boards have not been converted to generic board by the deadline. Remove them. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Remove eukrea boardsSimon Glass2015-09-111-37/+0
| | | | | | | | | | | | | | These boards have not been converted to generic board by the deadline. Remove all cpu9260 and cpuat91 boards. Signed-off-by: Simon Glass <sjg@chromium.org>
* | arm: Remove balloon3 boardSimon Glass2015-09-111-13/+0
| | | | | | | | | | | | | | This board has not been converted to generic board by the deadline. Remove it. Signed-off-by: Simon Glass <sjg@chromium.org>
* | lpc32xx: remove duplicated DMA_CLK_ENABLE bit definitionVladimir Zapolskiy2015-09-111-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | Because there is an originally defined CLK_DMA_ENABLE macro in clk.h, no reason to add another DMA_CLK_ENABLE macro with the same value. Remove DMA_CLK_ENABLE, since it does not follow naming convention from the code, this implies renaming of DMA_CLK_ENABLE to CLK_DMA_ENABLE in lpc32xx/devices.c file. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Tested-by: Sylvain Lemieux <slemieux@tycoint.com>
* | Merge git://git.denx.de/u-boot-rockchipTom Rini2015-09-0310-0/+1855
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| * | rockchip: Add SPI driverSimon Glass2015-09-021-0/+20
| | | | | | | | | | | | | | | | | | | | | Add a SPI driver for the Rockchip RK3288, using driver model. It should work for other Rockchip SoCs also. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: Add I2C driverSimon Glass2015-09-021-0/+70
| | | | | | | | | | | | | | | | | | | | | Add an I2C driver for the Rockchip RK3288, using driver model. It should work for other Rockchip SoCs also. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: rk3288: Add SDRAM initSimon Glass2015-09-022-0/+576
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add code to set up the SDRAM in SPL, ready for loading U-Boot. This uses device tree for configuration so should be able to support other RAM configurations. It may be possible to generalise the code to support other SoCs at some point. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: rk3288: Add header files for PMU and GRFSimon Glass2015-09-022-0/+857
| | | | | | | | | | | | | | | | | | | | | PMU is the power management unit and GRF is the general register file. Both are heavily used in U-Boot. Add header files with register definitions. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: rk3288: Add clock driverSimon Glass2015-09-021-0/+185
| | | | | | | | | | | | | | | | | | | | | Add a driver for setting up and modifying the various PLLs and peripheral clocks on the RK3288. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: Add basic peripheral and clock definitionsSimon Glass2015-09-023-0/+119
| | | | | | | | | | | | | | | | | | | | | | | | Add header files for the peripherals and clocks supported on Rockchip platforms. The particular implementation (and register set) for each is SoC-specific, but it seems that the naming can be generic. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rockchip: gpio: Add rockchip GPIO driverSimon Glass2015-09-021-0/+28
| | | | | | | | | | | | | | | | | | | | | This supports RK3288 at present. It does not implement functions or support for pull up/down. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-09-0217-97/+1634
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| * | | imx: vf610 add get_cpu_revPeng Fan2015-09-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we need to support runtime check for different drivers, we need to add get_cpu_rev for vf610, otherwise there will be build errors. This patch introduces a dummy CPU id which is not read from chip silicon. Later when we can get the real id from chip, can fix the value of MXC_CPU_VF610 then. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Suggested-by: Stefano Babic <sbabic@denx.de> Cc: Stefano Babic <sbabic@denx.de> Acked-by: Stefano Babic <sbabic@denx.de>
| * | | mxc: ocotp fix hole in shadow registersPeng Fan2015-09-021-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a hole in shadow registers address map of size 0x100 between bank 5 and bank 6 on iMX6QP, iMX6DQ, iMX6SDL, iMX6SX and iMX6UL. Bank 5 ends at 0x6F0 and Bank 6 starts at 0x800. When reading the fuses, we should account for this hole in address space. Similar hole exists between bank 14 and bank 15 of size 0x80 on iMX6QP, iMX6DQ, iMX6SDL and iMX6SX. Note: iMX6SL has only 0-7 banks and there is no hole. Note: iMX6UL doesn't have this one. When reading, we use register offset, so need to account for holes to get the correct address. When writing, we use bank/word index, there is no need to account for holes, always use bank/word index from fuse map. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
| * | | imx: mx6: ddr: add LPDDR2 supportPeng Fan2015-09-021-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add LPDDR2 support: 1. Implement a function mx6_lpddr2_cfg to initialize MMDC for LPDDR2. 2. Introduce a structure mx6_lpddr2_cfg, most entrys are same to mx6_ddr3_cfg, but still keep it a single one for easy to choose parameters for LPDDR2. 3. If ddr_type is LPDDR2, use mx6_lpddr2_cfg to init MMDC. 4. Update comments. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com>
| * | | imx: mx6: ddr init MMDC according to ddr_typePeng Fan2015-09-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To i.MX6, DDR3 and LPDDR2 is supported, so rename function mx6_dram_cfg to mx6_ddr3_cfg and the original mx6_dram_cfg function only is a wrapper. The new reimplemented function mx6_dram_cfg only invokes mx6_ddr3_cfg when ddr_type is for DDR3. Later we can use ddr_type to initialize MMDC for LPDDR2. Initialize ddr_type for different boards which enable SPL. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Cc: Stefan Roese <sr@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * | | imx: mx6: ddr add an entry ddr_type for mx6_ddr_sysinfoPeng Fan2015-09-021-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add ddr_type entry for mx6_ddr_sysinfo. It will be used for differenrate DDR3 and LPDDR2. Introduce an enum type for ddr_type. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com>
| * | | imx: mx6: ddr add mpzqlp2ctl entryPeng Fan2015-09-021-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add mpzqlp2ctl entry for mx6_mmdc_calibration. MMDC_MPZQLP2CTL register is for init tZQINIT, tZQCL, tZQCS for LPDDR2 chips. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com>
| * | | imx: mx6: ddr add dram io configuration and header file for i.MX6SLPeng Fan2015-09-022-0/+95
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define two structure mx6sl_iomux_ddr_regs and mx6sl_iomux_grp_regs. Add a new function mx6sl_dram_iocfg to configure dram io. Add header file to define macros for register address. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de>
| * | | imx: mx6: ddr add more register entry for mmdc_p_regsPeng Fan2015-09-021-9/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add more register entry for MMDC structure. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * | | imx: mxc_gpio: add support for imx7d SoCAdrian Alonso2015-09-021-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Add mxc_gpio support for imx7d SoC * Use CONFIG_MX7 to extend mxc gpio driver support for imx7d Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Adrian Alonso <aalonso@freescale.com>
| * | | imx: iomux-v3: add imx7d support for iomuxcAdrian Alonso2015-09-023-0/+1359
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Add imx7d support for iomux controller * imx7d has two iomux controllers iomuxc (0x3033000) and iomuxc-lpsr (0x302C0000) each conroller provides control and mux mode pad registers but shares iomuxc input select register with iomuxc-lpsr IOMUX_CONFIG_LPSR flag is used to properly set daisy chain settings for iomuxc-lpsr pads. * Since mx7d introduces LPSR IOMUX pins, add new base to IOMUX v3 driver for these LPSR pins. Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Fugang Duan <B38611@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
| * | | imx: clock support enet2 anatop clock supportPeng Fan2015-09-022-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To i.MX6SX/UL, two ethernet interfaces are supported. Add ENET2 clock support: 1. Introduce a new input parameter "fec_id", only 0 and 1 are allowed. To value 1, only i.MX6SX/UL can pass the check. 2. Modify board code who use this api to follow new api prototype. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Heiko Schocher <hs@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com> Cc: Stefan Roese <sr@denx.de> Cc: Nikolaos Pasaloukos <Nikolaos.Pasaloukos@imgtec.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefan Roese <sr@denx.de>
| * | | imx-common: consolidate macros and prototypes into sys_proto.hPeng Fan2015-09-026-87/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move most macro definitions and prototypes into "arch/arm/include/asm/imx-common/sys_proto.h" to avoid duplicated function prototypes and marco definitions for different i.MX SoCs. This patch do not remove the sys_proto.h for different i.MX SoCs, because we need to modify lots of driver code and others. This patch remove duplicated macros and prototypes and incude "sys_proto.h" of imx-common for each sys_proto.h of different i.MX platforms. Then later we should avoid add stuff in sys_proto.h of each platform, and modify driver to include common sys_proto.h. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * | | imx: mxs: reimplement get_cpu_revPeng Fan2015-09-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rewrite get_cpu_rev, from "static const char *get_cpu_rev(void)" to "u32 get_cpu_rev(void)". To align with get_cpu_rev of other i.MXes. Also write get_imx_type to replace get_cpu_type, since we have macro named get_cpu_type. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * | | imx: mx31 use new formula for get_cpu_revPeng Fan2015-09-021-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use new formula for get_cpu_rev, since we need to use this formula to do runtime check for all i.MXes. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * | | imx: add cpu type for i.MX2 and i.MX3Peng Fan2015-09-021-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add cpu types for i.MX2/3. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Stefano Babic <sbabic@denx.de>
| * | | ARM: ts4800: add ethernet supportDamien Riegel2015-09-021-0/+11
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit adds ethernet support to the TS4800. Note that the MAC address is not fused on this board and have to be read from FEC PALR PAUR registers (this is how the kernel provided by Technologic Systems does it). signed-off-by: Damien Riegel <damien.riegel@savoirfairelinux.com> Cc: Stefano Babic <sbabic@denx.de>
* | | armv8: fsl-lsch3: Rewrite MMU translation table entriesAlison Wang2015-09-012-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch rewrites MMU translation table entries. To start, all table entries are written as "invalid", then "device-ngnrnr" and "normal" are written to the entries to enable access to specific addresses. Signed-off-by: Alison Wang <alison.wang@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* | | arm/ls102xa:add hwconfig setting to support disable unused devicesZhuoyu Zhang2015-09-011-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DEVDISRn registers provides a mechanism for gating clocks of IP blocks that are not used. Here we implement hwconfig option to allow users to disable unused peripherals on the board. For ex. If eSDHC/qDMA/eDMA are unused and with disabled status in dts, User can enable CONFIG_FSL_DEVICE_DISABLE and set "devdis:esdhc,qdma,edma" in hwconfig, thus ESDHC controller & eDMA/qDMA will be clock gated to save more power. Signed-off-by: Zhuoyu Zhang <Zhuoyu.Zhang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | ls102xa: etsec: Use proper settings for BE BDsClaudiu Manoil2015-09-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the DMACTRL[LE] hack with recommended settings for ETSECDMAMCR to get the same end effect - obtaining big-endian buffer descriptors and frame data for eTSEC. The reset / default value for ETSECDMAMCR is preserved, excepting the BD and FR bits which are cleared to enable the BE mode in accordance with the H/W specifications. Fixes: 52d00a8 "ls102xa: etsec: Add etsec support for LS102xA" Signed-off-by: Claudiu Manoil <claudiu.manoil@freescale.com> Acked-by: Alison Wang <alison.wang@freescale.com> Tested-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | SECURE_BOOT: Disable IE Key feature for RAMBOOTAneesh Bansal2015-09-012-14/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ISBC Key Extension feature is not applicable for RAMBOOT as there is no way to retrieve the CSF Header and validated IE Key table from SRAM once CPC has been disabled. The feature is only applicable in case of NOR SECURE BOOT. Code Cleanup: The SECURE_BOOT specific defines have been moved from arch-ls102xa/config.h to arm/include/asm/fsl_secure_boot.h Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | armv8: Add framework for CCN-504 interconnect configurationBhupesh Sharma2015-09-011-0/+11
|/ / | | | | | | | | | | | | | | | | | | | | | | This patch adds a minimal framework for Dickens CCN-504 interconnect configuration - mainly related to adding Clusters/cores to snoop/DVM domain and setting QoS of the RN-I ports. LS2085A platform makes use of these configurations to support better network data performance and to boot a SMP Linux. Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | sunxi: Enable non-secure access to RTC on sun6i (A31s)Chen-Yu Tsai2015-08-311-0/+23
|/ | | | | | | | | | | | | | On the A31s the RTC is by default secured. Thus when u-boot loads the kernel in non-secure world, the RTC is unavailable. The SoC has a TrustZone Protection Controller, which can be used to enable non-secure access to the RTC. On the A31 the TZPC doesn't seem to do anything, i.e. changes to its register contents do not affect access to the RTC. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* ARM: AM43xx: Add functions to enable and disable USB clocksKishon Vijay Abraham I2015-08-281-0/+3
| | | | | | | | | | | Added functions to enable and disable USB clocks which can be invoked during USB init and USB exit respectively. Cc: Roger Quadros <rogerq@ti.com> Cc: Tero Kristo <t-kristo@ti.com> Cc: Nishanth Menon <nm@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: OMAP5: Add functions to enable and disable USB clocksKishon Vijay Abraham I2015-08-281-0/+4
| | | | | | | | | | | Added functions to enable and disable USB clocks which can be invoked during USB init and USB exit respectively. Cc: Roger Quadros <rogerq@ti.com> Cc: Tero Kristo <t-kristo@ti.com> Cc: Nishanth Menon <nm@ti.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* board: ti: OMAP5: added USB initializtion codeKishon Vijay Abraham I2015-08-281-0/+6
| | | | | | | | | Implemented board_usb_init(), board_usb_cleanup() and usb_gadget_handle_interrupts() in omap5 board file that can be invoked by various gadget drivers. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* board: ti: beagle_x15: added USB initializtion codeKishon Vijay Abraham I2015-08-281-1/+1
| | | | | | | | | Implemented board_usb_init(), board_usb_cleanup() and usb_gadget_handle_interrupts() in beagle_x15 board file that can be invoked by various gadget drivers. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7: Enable clocks for USB OTGSS2 and USB PHY2Kishon Vijay Abraham I2015-08-282-0/+5
| | | | | | | | Enabled clocks for the second dwc3 controller and second USB PHY present in DRA7. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm: spear: Move to common SPL infrastructureStefan Roese2015-08-281-2/+0
| | | | | | | | | | | | | The SPL implementation for SPEAr600 is older than the common SPL infrastructure. This patch now moves the SPEAr600 SPL over to the common SPL code. Tested on the only SPEAr board that currently uses SPL in mainline U-Boot, the x600. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Cc: Vipin Kumar <vk.vipin@gmail.com>
* ARM: DRA74-evm: Use SMA_1 spare register to workaround DP83865 phy on SR2.0Nishanth Menon2015-08-283-0/+7
| | | | | | | | | | | | | | | | | | | DP83865 ethernet phy used on DRA74x-evm is quirky and the datasheet provided IODELAY values for standard RGMII phys do not work. Silicon Revision(SR) 2.0 provides an alternative bit configuration that allows us to do a "gross adjustment" to launch the data off a different internal clock edge. Manual IO Delay overrides are still necessary to fine tune the clock-to-data delays. This is a necessary workaround for the quirky ethernet Phy we have on the platform. NOTE: SMA registers are spare "kitchen sink" registers that does contain bits for other workaround as necessary as well. Hence the control for the same is introduced in a generic SoC specific, board generic location. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* ARM: DRA7: Add detection of ES2.0Nishanth Menon2015-08-282-0/+2
| | | | | | | | | | | | | | | | | Add support for detection of ES2.0 version of DRA7 family of processors. ES2.0 is an incremental revision with various fixes including the following: - reset logic fixes - few assymetric aging logic fixes - MMC clock rate fixes - Ethernet speed fixes - edma fixes for mcasp [ravibabu@ti.com: posted internal for an older bootloader] Signed-off-by: Ravi Babu <ravibabu@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Acked-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* Merge git://git.denx.de/u-boot-nand-flashTom Rini2015-08-261-0/+2
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| * mtd: nand: mxs support oobsize bigger than 512Peng Fan2015-08-251-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If ecc chunk data size is 512 and oobsize is bigger than 512, there is a chance that block_mark_bit_offset conflicts with bch ecc area. The following graph is modified from kernel gpmi-nand.c driver with each data block 512 bytes. We can see that Block Mark conflicts with ecc area from bch view. We can enlarge the ecc chunk size to avoid this problem to those oobsize which is larger than 512. | P | |<----------------------------------------------------------------->| | | | (Block Mark) | | P' | | | | |<--------------------------------------------------->| D | | O'| | |<--------->| |<->| V V V V V +---+--------------+-+--------------+-+--------------+-+----------+-+---+ | M | data |E| data |E| data |E| data |E| | +---+--------------+-+--------------+-+--------------+-+----------+-+---+ ^ ^ | O | |<---------------->| P : the page size for BCH module. E : The ECC strength. G : the length of Galois Field. N : The chunk count of per page. M : the metasize of per page. C : the ecc chunk size, aka the "data" above. P': the nand chip's page size. O : the nand chip's oob size. O': the free oob. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Marek Vasut <marex@denx.de> Tested-By: Tim Harvey <tharvey@gateworks.com>
* | arm: pxa: use common timer functionsAndrew Ruder2015-08-242-1/+29
|/ | | | | | | | | | | | | | | | | This patch moves pxa to the common timer functions added in commit 8dfafdd - Introduce common timer functions <Rob Herring> The (removed) pxa timer code (specifically __udelay()) could deadlock at the 32-bit boundary of get_ticks(). get_ticks() returned a 32-bit value cast up to a 64-bit value. If get_ticks() + tmo in __udelay() crossed the 32-bit boundary, the while condition became unconditionally true and locked the processor. Rather than patch the specific pxa issues, simply move everything over to the common code. Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsuiko.com>
* arm: at91: add support for mini-box picosam9g45 boardErik van Luijk2015-08-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Bootlog: U-Boot SPL 2015.10-rc1-00452-g96a7ed1 (Aug 17 2015 - 10:32:21) mci: setting clock 258000 Hz, block size 512 mci: setting clock 258000 Hz, block size 512 mci: setting clock 258000 Hz, block size 512 mci: setting clock 33024000 Hz, block size 512 reading u-boot.img reading u-boot.img U-Boot 2015.10-rc1-00452-g96a7ed1 (Aug 17 2015 - 10:32:21 +0000) CPU: AT91SAM9G45 Crystal frequency: 12 MHz CPU clock : 400 MHz Master clock : 133.333 MHz Watchdog enabled DRAM: 256 MiB WARNING: Caches not enabled MMC: mci: 0 mci: setting clock 260416 Hz, block size 512 mci: setting clock 260416 Hz, block size 512 mci: setting clock 260416 Hz, block size 512 mci: setting clock 33333333 Hz, block size 512 reading uboot.env In: serial Out: serial Err: serial Net: macb0 Error: macb0 address not set. Hit any key to stop autoboot: 0 U-Boot> Signed-off-by: Erik van Luijk <evanluijk@interact.nl> [add 'picosam9g45_defconfig' to MAINTAINERS] Signed-off-by: Andreas Bießmann <andreas.devel@googlemail.com>
* Merge git://git.denx.de/u-boot-usbTom Rini2015-08-191-0/+2
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