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* driver/ifc: Add 64KB page supportJaiprakash Singh2015-04-231-2/+2
| | | | | | | | | | | | | | | | IFC has two register pages.Till IFC version 1.4 each register page is 4KB each.But IFC ver 2.0 register page size is 64KB each.IFC regiters structure is break into two viz FCM and RUNTIME.FCM(Flash control machine) registers are defined in PAGE0 and controls IFC generic functionality. RUNTIME registers are defined in PAGE1 and controls NAND and GPCM funcinality. FCM and RUNTIME structures defination is common for IFC version 1.4 and 2.0. Signed-off-by: Jaiprakash Singh <b44839@freescale.com> Signed-off-by: York Sun <yorksun@freescale.com>
* ahci: mmio_base is a virtual addressScott Wood2015-04-182-4/+4
| | | | | | | | | | | | | | Don't store it in a u32. Don't dereference the bus address as if it were a virtual address (fixes 284231e49a2b4 ("ahci: Support splitting of read transactions into multiple chunks")). Fixes crash on boot in MPC8641HPCN_36BIT target. Signed-off-by: Scott Wood <scottwood@freescale.com> Cc: Vadim Bendebury <vbendeb@chromium.org> Acked-by: York Sun <yorksun@freescale.com>
* Kconfig: Move CONFIG_DESIGNWARE_ETH to KconfigSimon Glass2015-04-181-1/+1
| | | | | | | | | | Move this to Kconfig and clean up board config files that use it. Also rename it to CONFIG_ETH_DESIGNWARE to fit with the naming that exists in drivers/net/Kconfig. Signed-off-by: Simon Glass <sjg@chromium.org> Version 1: Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* ARM: rmobile: use "select" instead of default value in defconfigMasahiro Yamada2015-04-181-0/+12
| | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: select CONFIG_DM* optionsMasahiro Yamada2015-04-182-24/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As mentioned in the previous commit, adding default values in each Kconfig causes problems because it does not co-exist with the "depends on" syntax. (Please note this is not a bug of Kconfig.) We should not do so unless we have a special reason. Actually, for CONFIG_DM*, we have no good reason to do so. Generally, CONFIG_DM is not a user-configurable option. Once we convert a driver into Driver Model, the board only works with Driver Model, i.e. CONFIG_DM must be always enabled for that board. So, using "select DM" is more suitable rather than allowing users to modify it. Another good thing is, Kconfig warns unmet dependencies for "select" syntax, so we easily notice bugs. Actually, CONFIG_DM and other related options have been added without consistency: some into arch/*/Kconfig, some into board/*/Kconfig, and some into configs/*_defconfig. This commit prefers "select" and cleans up the following issues. [1] Never use "CONFIG_DM=n" in defconfig files It is really rare to add "CONFIG_FOO=n" to disable CONFIG options. It is more common to use "# CONFIG_FOO is not set". But here, we do not even have to do it. Less than half of OMAP3 boards have been converted to Driver Model. Adding the default values to arch/arm/cpu/armv7/omap3/Kconfig is weird. Instead, add "select DM" only to appropriate boards, which eventually eliminates "CONFIG_DM=n", etc. [2] Delete redundant CONFIGs Sandbox sets CONFIG_DM in arch/sandbox/Kconfig and defines it again in configs/sandbox_defconfig. Likewise, OMAP3 sets CONFIG_DM arch/arm/cpu/armv7/omap3/Kconfig and defines it also in omap3_beagle_defconfig and devkit8000_defconfig. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* dm: usb: exynos: Use driver model for USBSimon Glass2015-04-181-0/+3
| | | | | | | | Convert Exynos boards over to use driver model for USB. This does not remove any unnecessary code so far. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Marek Vasut <marex@denx.de>
* ti: dwc3: Enable clocks in enable_basic_clocks() in hw_data.cKishon Vijay Abraham I2015-04-161-2/+2
| | | | | | | | | | | | | | | | Commit d3cfcb3 (ARM: DRA7: Enable clocks for USB OTGSS and USB PHY) changed the member names of prcm_regs from cm_l3init_usb_otg_ss_clkctrl to cm_l3init_usb_otg_ss1_clkctrl and from cm_coreaon_usb_phy_core_clkctrl to cm_coreaon_usb_phy1_core_clkctrl in order to differentiate between the two dwc3 controllers present in dra7xx/am43xx and enabled these clocks in enable_basic_clocks() in hw_data.c. However these clocks continued to be enabled in board files/driver files for dwc3 host mode functionality causing compilation break with few configs. Fixed it here by making all the clocks enabled in enable_basic_clocks() and removing it from board files/driver files here. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
* Merge branch 'master' of http://git.denx.de/u-boot-sunxiTom Rini2015-04-163-40/+74
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| * sunxi: usbc: Wait for vbus to fall after disabling itHans de Goede2015-04-151-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When u-boot boots the board may be powering vbus, we turn off vbus in sunxi_usbc_request_resources, if we are too quick with reading vusb-detect after this we may see a residual charge and assume we've an external vusb connected even though we do not. So when we see an external vusb wait a bit and try again. Without this when dealing with a pmic controller vbus and doing "reset" on the u-boot console the musb host will only init once every other boot, because the other boot it thinks an external vbus is present, this commit fixes this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: usbc: Initialize vusb value on request_resourcesHans de Goede2015-04-151-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | On boards which use the pmic to enable/disable vbus on the otg port, the vbus value is not reset to 0 on reset, as reset only resets the SoC and not the pmic, so explicitly set vbus to 0 on init (request_resources) by moving the gpio_direction_output call into request_resources. For consistency also move the gpio_direction_input call for vbus-detect into request_resources. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: GPIO pin mux hardware-feature-specific function index definesPaul Kocialkowski2015-04-152-16/+21
| | | | | | | | | | | | | | | | | | | | | | Each hardware feature exposed through the GPIO pin mux is usually using the same function index (for a given port), so there is no need to define one value per pin: one value per hardware feature per port is sufficient, avoids duplication and makes everything easier to understand. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: common VBUS detection logic in usbcPaul Kocialkowski2015-04-151-4/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | VBUS detection could be needed not only by the musb code (to prevent host mode), but also by e.g. gadget drivers to start only when a cable is connected. In addition, this allows more flexibility in vbus detection, as it could easily be extended to other USBC indexes. Eventually, this would help making musb support independent from a hardcoded USB controller index (0). Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * sunxi: usb: Drop AXP-sepcific VBUS detection and drive logicPaul Kocialkowski2015-04-151-17/+0
| | | | | | | | | | | | | | | | | | VBUS detection and enable is now be used with virtual AXP GPIOs, so all the USB code has to use GPIO in every case and let sunxi_gpio do the heavy lifting. Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | ARM: AM43xx: Enable clocks for USB OTGSS and USB PHYKishon Vijay Abraham I2015-04-141-0/+12
| | | | | | | | | | | | | | Enabled clocks for dwc3 controller and USB PHY present in AM43xx. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
* | ARM: DRA7: Enable clocks for USB OTGSS and USB PHYKishon Vijay Abraham I2015-04-142-5/+19
|/ | | | | | | Enabled clocks for dwc3 controller and USB PHY present in DRA7. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Reviewed-by: Lukasz Majewski <l.majewski@samsung.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-04-131-0/+27
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| * ARM: mx5: add support for USB armory boardAndrej Rosano2015-04-091-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Inverse Path USB armory board, an open source flash-drive sized computer based on Freescale i.MX53 SoC. http://inversepath.com/usbarmory Signed-off-by: Andrej Rosano <andrej@inversepath.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Chris Kuethe <chris.kuethe@gmail.com> Cc: Fabio Estevam <festevam@gmail.com> Cc: Vagrant Cascadian <vagrant@debian.org> Tested-By: Vagrant Cascadian <vagrant@debian.org> Tested-by: Chris Kuethe <chris.kuethe@gmail.com>
| * ARM: mx5: move to a standard arch/board approachAndrej Rosano2015-04-091-0/+16
| | | | | | | | | | | | | | | | | | | | Move the MX5 based boards to arch/arm/cpu/armv7/mx5, following the commit: 89ebc82137bebb11a8191f8b9cbf08f2533ae8bc Signed-off-by: Andrej Rosano <andrej@inversepath.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Vagrant Cascadian <vagrant@debian.org> Tested-by: Chris Kuethe <chris.kuethe@gmail.com>
* | arm: armada-xp: Fix SPL for AXP by using save_boot_params_retStefan Roese2015-04-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | Patch e11c6c27 (arm: Allow lr to be saved by board code) introduced a different method to return from save_boot_params(). The SPL support for AXP has been pulled and changing to this new method is now required for SPL to work correctly. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Luka Perkov <luka.perkov@sartura.hr>
* | Merge branch 'u-boot/master'Albert ARIBAUD2015-04-1011-51/+136
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| * | am33xx/ddr.c: Fix regression on DDR2 platformsTom Rini2015-04-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Back in fc46bae a "clean up" was introduced that intended to reconcile some of the AM335x codepaths based on how AM43xx operates. Unfortunately this introduced a regression on the DDR2 platforms. This was un-noticed on DDR3 (everything except for Beaglebone White) as we had already populated sdram_config correctly in sequence. This change brings us back to the older behavior and is fine on all platforms. Tested on Beaglebone White, Beaglebone Black and AM335x GP EVM Reported-by: Matt Ranostay <mranostay@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
| * | Exynos5: Fix rpll_sdiv to support both peach-pit and peach-pi panelsAjay Kumar2015-04-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The existing setting for rpll_sdiv generates 70.5Mhz RPLL video clock to drive 1366x768 panel on peach_pit. This clock rate is not sufficient to drive 1920x1080 panel on peach-pi. So, we adjust rpll_sdiv to 3 so that it generates 141Mhz pixel clock which can drive peach-pi LCD. This change doesn't break peach-pit LCD since 141/2=70.5Mhz, i.e FIMD divider at IP level will get set to 1(the required divider setting will be calculated and set by exynos_fimd_set_clock()) and hence peach-pit LCD still works fine. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | arm: exynos: add display clocks for Exynos5800Ajay Kumar2015-04-061-3/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add get_lcd_clk and set_lcd_clk callbacks for Exynos5800 needed by exynos video driver. Signed-off-by: Ajay Kumar <ajaykumar.rs@samsung.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Exynos: Clock: Fix exynos5_get_periph_rate for I2C.Guillaume GARDET2015-04-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 2e82e9252695a612ab0cbf40fa0c7368515f6506 'Exynos: Clock: Cleanup soc_get_periph_rate' introduced a bug in I2C config. This patch makes cros_ec keyboard working again on Samsung Chromebook (snow). Changes in V2: reorder lines as requested by Joonyoung Shim. Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr> Cc: Akshay Saraswat <akshay.s@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Joonyoung Shim <jy0922.shim@samsung.com> Reviewed-by: Simon Glass <sjg@chroimum.org> Tested-by: Simon Glass <sjg@chroimum.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-imxTom Rini2015-03-311-0/+42
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| | * board/seco: Add mx6q-uq7 basic board supportBoris BREZILLON2015-03-231-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | Add basic SECO MX6Q/uQ7 board support (Ethernet, UART, SD are supported). It also adds a Kconfig skeleton to later add more SECO board (supporting SoC and board variants). Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * ARM: mx6: move to a standard arch/board approachBoris BREZILLON2015-03-231-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale boards are currently all defined in arch/arm/Kconfig, which makes them hard to detect. Moreover the MX6 SoC variant (Q, D, DL, S, SL) selection is currently done via the SYS_EXTRA_OPTIONS option which marked as deprecated. Move to a more standard way to select sub-architecture and board by creating a Kconfig under arch/arm/cpu/armv7/mx6 and a new ARCH_MX6 option. Existing MX6 board definitions should be moved in this new Kconfig in choice menu, and new boards should be directly declared in this menu. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| * | sunxi: use CONFIG_SYS_CLK_FREQ to set cpu clockIain Paton2015-03-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | make the CPU clock selectable via Kconfig this removes the sunxi specific CONFIG_CLK_FULL_SPEED defined in each soc header and replaces it's use in board/sunxi/board.c with CONFIG_SYS_CLK_FREQ from Kconfig which allows us to configure board specific frequency on boot Signed-off-by: Iain Paton <ipaton0@gmail.com> [hdegoede@redhat.com s/CONFIG_SYS_CLK_FREQ/CONFIG_TIMER_CLK_FREQ/ for the arch-timer clk speed on sun7i to fix mis-compile on sun7i] Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: sun4i: improve cpu clock selection methodIain Paton2015-03-291-16/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clock_set_pll1 would pick the next highest available cpu clock speed if a value not in the pre defined table was selected. this potentially results in overclocking the soc. reverse the selection method so that we select the next lowest speed and add the missing 912Mhz setting that's requested by sun7i which also uses the sun4i clock code. Signed-off-by: Iain Paton <ipaton0@gmail.com> Acked-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: musb: Fix some lo speed devices not working with musb hostHans de Goede2015-03-291-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The usb0 / otg phy on sunxi boards has a bug where it wrongly detects a high speed squelch on usb reset deassert when a lo speed device is plugged in. The android kernel has a work around for this in the form of temporary disabling the phy's squelch detection on reset deassert, this commit adds the same workaround to the u-boot sunxi musb code, thereby fixing various usb lo speed devices not working. Tested with a (before non working) usb keyboard and a usb 2.4 GHz wireless keyboard/mouse combo receiver. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * | ARM: bcm283x: merge BCM2835/BCM2836 directories into mach-bcm283xMasahiro Yamada2015-03-282-14/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BCM2835 (used on Raspberry Pi) and BCM2836 (used on Raspberry Pi 2) are similar enough. One of the biggest differences is the ARM processor. It is reasonable to collect the source files into a single place, arch/arm/mach-bcm283x/. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org>
| * | malloc_f: enable SYS_MALLOC_F by default if DM is onMasahiro Yamada2015-03-282-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This option has a bool type, not hex. Fix it and enable it if CONFIG_DM is on because Driver Model always requires malloc memory. Devices are scanned twice, before/after relocation. CONFIG_SYS_MALLOC_F should be enabled to use malloc memory before relocation. As it is board-independent, handle it globally. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Robert Baldyga <r.baldyga@samsung.com>
| * | malloc_f: remove redundant defalut values of CONFIG_SYS_MALLOC_F_LENMasahiro Yamada2015-03-282-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The default value of CONFIG_SYS_MALLOC_F_LEN is defined by ./Kconfig as 0x400. Each defconfig or Kconfig need not repeat the same value. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Robert Baldyga <r.baldyga@samsung.com>
* | | ARM: move -march=* and -mtune= options to arch/arm/MakefileMasahiro Yamada2015-03-271-5/+0
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | My main motivations for this commit are: [1] Follow the arch/arm/Makefile style of Linux Kernel [2] Maintain compiler options systematically Currently, we give -march=* and -mtune=* options inconsistently: Only some of the CPUs pass -march=* and -mtune=* options. By collecting such options into the single place arch/arm/Makefile we can tell which options are missing at a glance. [3] Prepare for deprecating arch/*/cpu/*/config.mk Note: This commit just moves the compiler options so as not to change the behavior at all. It does not care about the correctness of the given options. Fox example, "-march=armv5te" might be better than "-march=armv4" for ARM946EJS, but it is beyond the scope this commit. Also, filling the missing -march=* and -tune=* is left to follow-up patches. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Stefan Roese <sr@denx.de>
* | remove unnecessary version.h includesRob Herring2015-03-247-7/+0
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Various files are needlessly rebuilt every time due to the version and build time changing. As version.h is not actually needed, remove the include. Signed-off-by: Rob Herring <robh@kernel.org> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Marek Vasut <marex@denx.de> Cc: Tom Warren <twarren@nvidia.com> Cc: Michal Simek <monstr@monstr.eu> Cc: Macpaul Lin <macpaul@andestech.com> Cc: Wolfgang Denk <wd@denx.de> Cc: York Sun <yorksun@freescale.com> Cc: Stefan Roese <sr@denx.de> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Philippe Reynes <tremyfr@yahoo.fr> Cc: Eric Jarrige <eric.jarrige@armadeus.org> Cc: "David Müller" <d.mueller@elsoft.ch> Cc: Phil Edworthy <phil.edworthy@renesas.com> Cc: Robert Baldyga <r.baldyga@samsung.com> Cc: Torsten Koschorrek <koschorrek@synertronixx.de> Cc: Anatolij Gustschin <agust@denx.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Łukasz Majewski <l.majewski@samsung.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-imxTom Rini2015-03-181-1/+18
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| * mx6: soc: Switch to cold resetDirk Behme2015-03-131-0/+18
| | | | | | | | | | | | | | | | Disable the warm reset and enable the cold reset for a more reliable restart ('reset'). This is taken from the Linux kernel, see imx_src_init() in arch/arm/mach-imx/src.c. Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
| * imx:mx6 remove duplicated includesPeng Fan2015-03-131-1/+0
| | | | | | | | | | | | There is no need to include asm/bootm.h twice, so remove one. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
| * Merge branch 'master' of git://git.denx.de/u-bootStefano Babic2015-03-0572-3648/+1523
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* | | ARM: OMAP3: rx51: Enable workaround for ARM errata 454179, 430973, 621766Nishanth Menon2015-03-131-25/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RX51 has a secure logic which uses different parameters compared to traditional implementation. So, make the generic secure acr write over-ride-able by board file and refactor rx51 code to use this. While at it, enable the OMAP3 specific errata code for 454179, 430973, 621766. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: OMAP3: Enable workaround for ARM errata 454179, 430973, 621766Nishanth Menon2015-03-131-21/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the OMAP3 specific errata code for 454179, 430973, 621766 and while at it, remove legacy non-revision checked errata logic. Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: OMAP5 / DRA7: Setup L2 Aux Control Register with recommended configurationNishanth Menon2015-03-131-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update to existing recommendation for L2ACTLR configuration to prevent system instability and optimize performance. These apply to both OMAP5 and DRA7. Reported-by: Vivek Chengalvala <vchengalvala@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: DRA7 / OMAP5: Add workaround for ARM errata 798870Praveen Rao2015-03-131-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables the workaround for ARM errata 798870 for OMAP5 / DRA7 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock." An l2auxctlr accessor implementation for OMAP5 and DRA7 is introduced here as well. Signed-off-by: Praveen Rao <prao@ti.com> Signed-off-by: Angela Stegmaier <angelabaker@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: OMAP3: Get rid of omap3_gp_romcode_call and replace with omap_smc1Nishanth Menon2015-03-134-16/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | omap_smc1 is now generic enough to remove duplicate omap3_gp_romcode_call logic that omap3 introduced. As part of this change, move to using the generic lowlevel_init.S for omap3 as well. Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: OMAP: Change set_pl310_ctrl_reg to be genericNishanth Menon2015-03-132-9/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | set_pl310_ctrl_reg does use the Secure Monitor Call (SMC) to setup PL310 control register, however, that is something that is generic enough to be used for OMAP5 generation of processors as well. The only difference being the service being invoked for the function. So, convert the service to a macro and use a generic name (same as that used in Linux for some consistency). While at that, also add a data barrier which is necessary as per recommendation. While at this, smc #0 is maintained as handcoded assembly thanks to various gcc version eccentricities, discussion thread: http://marc.info/?t=142542166800001&r=1&w=2 Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: Introduce erratum workaround for 621766Nishanth Menon2015-03-131-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 621766: Under a specific set of conditions, executing a sequence of NEON or vfp load instructions can cause processor deadlock Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set L1NEON to 1 Based on ARM errata Document revision 20.0 (13 Nov 2010) Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: Introduce erratum workaround for 430973Nishanth Menon2015-03-131-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 430973: Stale prediction on replaced inter working branch causes Cortex-A8 to execute in the wrong ARM/Thumb state Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set IBE to 1 Based on ARM errata Document revision 20.0 (13 Nov 2010) Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: Introduce erratum workaround for 454179Nishanth Menon2015-03-132-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 454179: Stale prediction may inhibit target address misprediction on next predicted taken branch Impacts: Every Cortex-A8 processors with revision lower than r2p1 Work around: Set IBE and disable branch size mispredict to 1 Also provide a hook for SoC specific handling to take place if needed. Based on ARM errata Document revision 20.0 (13 Nov 2010) Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | ARM: Introduce erratum workaround for 798870Nishanth Menon2015-03-133-2/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add workaround for Cortex-A15 ARM erratum 798870 which says "If back-to-back speculative cache line fills (fill A and fill B) are issued from the L1 data cache of a CPU to the L2 cache, the second request (fill B) is then cancelled, and the second request would have detected a hazard against a recent write or eviction (write B) to the same cache line as fill B then the L2 logic might deadlock." Implementations for SoC families such as Exynos, OMAP5/DRA7 etc will be widely different. Every SoC has slightly different manner of setting up access to L2ACLR and similar registers since the Secure Monitor handling of Secure Monitor Call(smc) is diverse. Hence an weak function is introduced which may be overriden to implement SoC specific accessor implementation. Based on ARM errata Document revision 18.0 (22 Nov 2013) Signed-off-by: Nishanth Menon <nm@ti.com> Tested-by: Matt Porter <mporter@konsulko.com> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-tegraTom Rini2015-03-101-1/+8
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: README Signed-off-by: Tom Rini <trini@konsulko.com>
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