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* dm: rtc: Support mc146818 driver in driver modelBin Meng2015-07-141-108/+204
| | | | | | | | Add driver model support to the mc146818 rtc driver. Also clean up the driver a little bit for coding convention issues. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: crownbay: Add MP initializationBin Meng2015-07-142-0/+24
| | | | | | | | | | | | Intel Crown Bay board has a TunnelCreek processor which supports hyper-threading. Add /cpus node in the crownbay.dts and enable the MP initialization. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org> (modified to remove error: overriding the value of OF_CONTROL. Old value: "y", new value: "y")
* x86: Clean up lapic codesBin Meng2015-07-145-183/+103
| | | | | | | | | | | | | | | This commit cleans up the lapic codes: - Delete arch/x86/include/asm/lapic_def.h, and move register and bit defines into arch/x86/include/asm/lapic.h - Use MSR defines from msr-index.h in enable_lapic() and disable_lapic() - Remove unnecessary stuff like NEED_LAPIC, X86_GOOD_APIC and CONFIG_AP_IN_SIPI_WAIT - Move struct x86_cpu_priv defines to asm/arch-ivybridge/bd82x6x.h, as it is not apic related and only used by ivybridge - Fix coding convention issues Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Move lapic_setup() call into init_bsp()Bin Meng2015-07-142-3/+1
| | | | | | | | | | Currently lapic_setup() is called before calling mp_init(), which then calls init_bsp() where it calls enable_lapic(), which was already enabled in lapic_setup(). Hence move lapic_setup() call into init_bsp() to avoid the duplication. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Move MP initialization codes into a common placeBin Meng2015-07-146-73/+114
| | | | | | | | | | | Most of the MP initialization codes in arch/x86/cpu/baytrail/cpu.c is common to all x86 processors, except detect_num_cpus() which varies from cpu to cpu. Move these to arch/x86/cpu/cpu.c and implement the new 'get_count' method for baytrail and cpu_x86 drivers. Now we call cpu_get_count() in mp_init() to get the number of CPUs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: ivybridge: Remove SMP from CPU_SPECIFIC_OPTIONSBin Meng2015-07-141-1/+0
| | | | | | | Ivybridge is not ready for U-Boot MP initialization yet. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: cpu: Add a new get_count method to cpu uclassBin Meng2015-07-142-0/+26
| | | | | | | | Introduce a new method 'get_count' in the UCLASS_CPU ops to get the number of CPUs in the system. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: kconfig: Fix minor nits in MAX_CPUSBin Meng2015-07-141-12/+12
| | | | | | | | | Move MAX_CPUS definition after SMP so that it shows below SMP in the menuconfig. Also replace the leading spaces in the MAX_CPUS section with tabs to conform coding standard. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: kconfig: Make MAX_CPUS and AP_STACK_SIZE depend on SMPBin Meng2015-07-141-0/+2
| | | | | | | MAX_CPUS and AP_STACK_SIZE are only meaningful when SMP is on. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: dm: Clean up cpu driversBin Meng2015-07-146-55/+86
| | | | | | | | | | | | | | | This commit does the following to clean up x86 cpu dm drivers: - Move cpu_x86 driver codes from arch/x86/cpu/cpu.c to a dedicated file arch/x86/cpu/cpu_x86.c - Rename x86_cpu_get_desc() to cpu_x86_get_desc() to keep consistent naming with other dm drivers - Add a new cpu_x86_bind() in the cpu_x86 driver which does exactly the same as the one in the intel baytrail cpu driver - Update intel baytrail cpu driver to use cpu_x86_get_desc() and cpu_x86_bind() Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: cpu: Test against cpu_ops->get_info in cpu_get_info()Bin Meng2015-07-141-1/+1
| | | | | | | In cpu_get_info() it wrongly tests against cpu_ops->get_desc to see if it is NULL. It should test against cpu_ops->get_info. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* dm: cpu: Fix undefined ENOSYS build errorBin Meng2015-07-142-0/+2
| | | | | | | Include <errno.h> otherwise ENOSYS is undefined. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: spi: Correct minor nits in ICH driverSimon Glass2015-07-141-3/+2
| | | | | | | | Tidy up three minor problems in this file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jteki@openedev.com>
* spi: sf: Print the error code on failureSimon Glass2015-07-141-2/+6
| | | | | | | | | | Rather than just 'ERROR', display the error code, which may be useful, at least with driver model. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jteki@openedev.com>
* x86: fsp: Move FspInitEntry call to board_init_f()Bin Meng2015-07-145-22/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | The call to FspInitEntry is done in arch/x86/lib/fsp/fsp_car.S so far. It worked pretty well but looks not that good. Apart from doing too much work than just enabling CAR, it cannot read the configuration data from device tree at that time. Now we want to move it a little bit later as part of init_sequence_f[] being called by board_init_f(). This way it looks and works better in the U-Boot initialization path. Due to FSP's design, after calling FspInitEntry it will not return to its caller, instead it jumps to a continuation function which is given by bootloader with a new stack in system memory. The original stack in the CAR is gone, but its content is perserved by FSP and described by a bootloader temporary memory HOB. Technically we can recover anything we had before in the previous stack, but that is way too complicated. To make life much easier, in the FSP continuation routine we just simply call fsp_init_done() and jump back to car_init_ret() to redo the whole board_init_f() initialization, but this time with a non-zero HOB list pointer saved in U-Boot's global data so that we can bypass the FspInitEntry for the second time. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com> Tested-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Load GDT before calling FspInitEntryBin Meng2015-07-144-2/+33
| | | | | | | | | | | | | | | | | | | | | Currently the FSP execution environment GDT is setup by U-Boot in arch/x86/cpu/start16.S, which works pretty well. But if we try to move the FspInitEntry call a little bit later to better fit into U-Boot's initialization sequence, FSP will fail to bring up the AP due to #GP fault as AP's GDT is duplicated from BSP whose GDT is now moved into CAR, and unfortunately FSP calls AP initialization after it disables the CAR. So basically the BSP's GDT still refers to the one in the CAR, whose content is no longer available, so when AP starts up and loads its segment register, it blows up. To resolve this, we load GDT before calling into FspInitEntry. The GDT is the same one used in arch/x86/cpu/start16.S, which is in the ROM and exists forever. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com> Tested-by: Simon Glass <sjg@chromium.org> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Add Kconfig options to be used by arch/x86/cpu/config.mkBin Meng2015-07-142-3/+18
| | | | | | | | | | Add RESET_SEG_START, RESET_SEG_SIZE and RESET_VEC_LOC Kconfig options and make arch/x86/cpu/config.mk use these options. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Andrew Bradford <andrew.bradford@kodakalaris.com> Tested-by: Simon Glass <sjg@chromium.org>
* builderthread.py: Keep 'SPL'Tom Rini2015-07-141-1/+1
| | | | | | | | | On i.MX platforms the SPL binary is called "SPL" so make sure we keep that. Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Simon Glass <sjg@chromium.org>
* RFC: Deprecate MAKEALLSimon Glass2015-07-141-0/+10
| | | | | | | | | Since buildman now includes most of the features of MAKEALL it is probably time to talk about deprecating MAKEALL. Comments welcome. Signed-off-by: Simon Glass <sjg@chromium.org>
* Prepare v2015.07Tom Rini2015-07-141-1/+1
| | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* scsi: fix compiler warning with DEBUG and 48bit LBAsAndre Przywara2015-07-111-2/+2
| | | | | | | | | | | | | | | | | | Commit 2b42c9317db ("ahci: support LBA48 data reads for 2+TB drives") introduced conditional code which triggers a warning when compiled with DEBUG enabled: In file included from common/cmd_scsi.c:12:0: common/cmd_scsi.c: In function 'scsi_read': include/common.h:109:4: warning: 'smallblks' may be used uninitialized in this function [-Wmaybe-uninitialized] ... Since this is for debug only, take the easy way and initialize the variable explicitly on declaration to avoid the warning. (Fix a nearby whitespace error on the way.) Tested-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Andre Przywara <osp@andrep.de>
* Merge git://git.denx.de/u-boot-samsungTom Rini2015-07-102-1/+2
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| * exynos: i2c: Correct bug in pinmux selectionSimon Glass2015-07-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | When driver model is not used the current code does not correctly select the pinmux for the I2C bus. This bug was introduced by this commit: 8dfcbaa dm: i2c: s3c24x0: adjust to dm-i2c api Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de> Reviewed-by: Przemyslaw Marczak <p.marczak@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * arm: adds the status info for odroid-xu3Minkyu Kang2015-07-101-0/+1
| | | | | | | | | | | | Adds the 'F:' entry for the board's defconfig Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | Merge git://git.denx.de/u-boot-marvellTom Rini2015-07-109-8/+184
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| * | arm: mvebu: db-88f6820-gp: Add USB/EHCI supportStefan Roese2015-07-101-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enabled the USB/EHCI support for the Marvell DB-88F6820-GP eval board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Vasut <marex@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | usb: Add EHCI support for Armada 38x (mvebu)Stefan Roese2015-07-102-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds USB EHCI host support for the common mvebu platform. Including the Armada 38x. Tested on DB-88F6280-GP eval board. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Marek Vasut <marex@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu: db-88f6820-gp.h: Add SATA/SCSI (AHCI) supportStefan Roese2015-07-101-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | Configure and enable the SATA/SCSI (AHCI) support for the Marvell DB-88F6820-GP eval board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu: Add SATA/SCSI (AHCI) support for Armada A38xStefan Roese2015-07-103-0/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the common AHCI controller on the Marvell Armada 38x. Tested on the Marvell DB-88F6820-GP eval board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | block: ahci: Don't enable port interruptsStefan Roese2015-07-101-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the initialization of the AHCI controller to not enable the default interrupts (DEF_PORT_IRQ). As interrupts are not used in U-Boot in general, this should not break the common AHCI driver operation. This change is needed to support the Marvell Armada 38x AHCI controller. With interrupts enabled, this results in timeouts in ahci_device_data_io(). Not enabling these interrupts fixes this problem and the common AHCI driver works fine. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu: db-88f6820-gp: Add MMC/SDIO supportStefan Roese2015-07-101-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds MMC/SDIO support to the Marvell DB-88F6820-GP board configuration. Including support for the common partitions and filesystems. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu: Add SDIO/SDHCI support for Armada A38xStefan Roese2015-07-104-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Armada A38x implements an SDHCI compatible SDIO controller. This patch enables the Marvell driver to support this SoC. And enables the SDIO controller if selected by the board configuration. Tested on Marvell DB-88F6820-GP board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | mmc: sdhci.c: Add config option to use a fixed buffer for transfersStefan Roese2015-07-101-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While implementing SDIO/MMC SPL booting for the Marvell Armada 38x, the following problem occured. The SPL runs in internal SRAM which is the L2 cache locked to memory. When the MMC buffers now are located on the stack (or bss), the SDIO controller (SDHCI) can't write into this L2 cache memory. This patch introduces a method to use a fixed buffer that will be used for all transfers by defining CONFIG_FIXED_SDHCI_ALIGNED_BUFFER. This way, the board can use this buffer address located in SDRAM for all transfers. This solves this SPL problem on the A38x and should only be used in the SPL U-Boot version. Tested for SPL booting on Marvell Armada 38x DB-88F6820-GP board. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | mmc: sdhci: Use timer based timeout detection in sdhci_send_command()Stefan Roese2015-07-101-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The loop counter based timeout detection does not work on the Armada 38x based board (DB-88F6820-GP). At least with dcache enabled a timeout is detected. Without dcache enabled, the timeout does not occur. Increasing the loop counter solves this issue. But a better solution is to use a timer based timeout detection instead. This patch now implements this timer based detection. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Pantelis Antoniou <panto@antoniou-consulting.com> Cc: Luka Perkov <luka.perkov@sartura.hr>
| * | arm: mvebu: db-88f6820-gp: Add MAINTAINERS fileStefan Roese2015-07-101-0/+6
| |/ | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Cc: Luka Perkov <luka.perkov@sartura.hr> Cc: Albert Aribaud <albert.u.boot@aribaud.net>
* | mtd: fix false positive "Offset exceeds device limit" errorMasahiro Yamada2015-07-102-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 09c3280754f8 (mtd, nand: Move common functions from cmd_nand.c to common place), NAND commands would not work at all on large devices. => nand read 80000000 10000 10000 NAND read: Offset exceeds device limit => nand erase 100000 100000 NAND erase: Offset exceeds device limit The type of the "size" of "struct mtd_info" is uint64_t, while mtd_arg_off_size() and mtd_arg_off() treat chipsize as int type. The chipsize is wrapped around if the argument is given with 2GB or larger. Acked-by: Heiko Schocher <hs@denx.de> Acked-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | ahci: Fix compiling warnings under 64bit platformsTang Yuantian2015-07-093-38/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When compling under 64bit platforms, there are lots of warnings, like: drivers/block/ahci.c:114:18: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio; ^ drivers/block/ahci.c: In function ?.hci_host_init?. drivers/block/ahci.c:218:49: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i); ...... Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
* | arm: baltos: change USB ports functionsYegor Yefremov2015-07-091-2/+2
| | | | | | | | | | | | | | Baltos has USB0 connected to a USB hub and thus is host-only. USB1 is connected to microUSB connector and thus should use OTG mode. Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
* | keystone2: config: update default mtdMichael Scherban2015-07-083-3/+3
| | | | | | | | | | | | | | | | Because it is possible for the MTD number to change, causing a filesystem mount failure, we should use the volume name instead of the MTD number and let Linux resolve the correct one. Signed-off-by: Mike Scherban <m-scherban@ti.com>
* | stm32f4: fix gpio description in commentAntonio Borneo2015-07-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On STM32F429 gpio PC6/PC7 can be allocated for USART6, as reported in the comment. But current code in drivers/serial/serial_stm32.c uses a different gpio mapping (PG14/PG9) for USART6. Fix the comment to match current code in the driver. Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> To: u-boot@lists.denx.de To: Kamil Lulko <rev13@wp.pl> Cc: Tom Rini <trini@konsulko.com>
* | stm32f4: fix minor typo in commentAntonio Borneo2015-07-081-1/+1
| | | | | | | | | | | | | | Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> To: u-boot@lists.denx.de To: Kamil Lulko <rev13@wp.pl> Cc: Tom Rini <trini@konsulko.com>
* | stm32f4: fix MAINTAINERS fileAntonio Borneo2015-07-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When "scripts/get_maintainer.pl" parses "board/.../MAINTAINERS", it uses the line containing board name as delimiter. Without this line, the script happily mixes the lines from current board MAINTAINERS file with lines from another file. Fix it by adding a reasonable board name. Tested by comparing output of: cat board/st/stm32f429-discovery/MAINTAINERS ./scripts/get_maintainer.pl -f board/st/stm32f429-discovery Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com> To: u-boot@lists.denx.de To: Kamil Lulko <rev13@wp.pl> Cc: Tom Rini <trini@konsulko.com>
* | siemens,am33x: adjust mtd partitionEgli, Samuel2015-07-081-17/+16
| | | | | | | | | | | | | | | | | | | | | | | | Use one mtd partition for rootfs and configuration by means of ubi volumes and get rid of configuration partition. We can use partition layout for both 256MB and 512MB flash. Signed-off-by: Samuel Egli <samuel.egli@siemens.com> Cc: Heiko Schocher <hs@denx.de> Cc: Roger Meier <r.meier@siemens.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Heiko Schocher <hs@denx.de>
* | arm: baltos: fix NAND bootYegor Yefremov2015-07-081-2/+8
| | | | | | | | | | | | | | | | Specify proper U-Boot offset, enable prefetch mode, increase bootm size and add FIT fallback, if board_name is not present in kernel-fit.itb image. Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
* | arm: baltos: drop I2C speed to 1000 HzYegor Yefremov2015-07-082-1/+3
| | | | | | | | | | | | | | | | This action is need to make I2C communication with PMIC stable for low temperature. Print current I2C speed in SPL for visual control. Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
* | arm: baltos: enable CMD_NET and FIT support in defconfigYegor Yefremov2015-07-082-4/+2
| | | | | | | | | | Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | arm: convert am3517_crane and am3517_evm to generic boardsYegor Yefremov2015-07-082-0/+2
| | | | | | | | | | | | | | | | Add CONFIG_SYS_GENERIC_BOARD to board's config header. Boot-tested on am3517_evm board. Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
* | ARM: beagle_x15: prevent DCAN1 _wait_target_disable failure in kernelRoger Quadros2015-07-081-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If board is booted with transitions happening on DCAN1 pins then the following warning is seen in the kernel at boot when the hwmod layer initializes. "omap_hwmod: dcan1: _wait_target_disable failed" This is because DCAN1 module's SWAKEUP mechanism is broken and it fails to correctly turn OFF if it sees a transition on the DCAN1 pins. Suggested workaround is to keep DCAN1 pins in safe mode while enabling/disabling DCAN1 module. The hwmod layer enables and disables all modules at boot and we have no opportunity to put the DCAN1 pins in safe mode at that point. DCAN1 is not used by u-boot so it doesn't matter to it if these pins are in safe mode. The kernel driver correctly configures the right mode when DCAN1 is active. Signed-off-by: Roger Quadros <rogerq@ti.com> [trini: s/PULLUP/PULL_UP/ based on DRA7xx EVM version of this patch] Signed-off-by: Tom Rini <trini@konsulko.com>
* | ARM: DRA7-evm: prevent DCAN1 _wait_target_disable failure in kernelRoger Quadros2015-07-081-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If board is booted with transitions happening on DCAN1 pins then the following warning is seen in the kernel at boot when the hwmod layer initializes. "omap_hwmod: dcan1: _wait_target_disable failed" This is because DCAN1 module's SWAKEUP mechanism is broken and it fails to correctly turn OFF if it sees a transition on the DCAN1 pins. Suggested workaround is to keep DCAN1 pins in safe mode while enabling/disabling DCAN1 module. The hwmod layer enables and disables all modules at boot and we have no opportunity to put the DCAN1 pins in safe mode at that point. DCAN1 is not used by u-boot so it doesn't matter to it if these pins are in safe mode. The kernel driver correctly configures the right mode when DCAN1 is active. Signed-off-by: Roger Quadros <rogerq@ti.com>
* | Makefile:Add GCC flag -fno-delete-null-pointer-checksPrabhakar Kushwaha2015-07-081-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | -fdelete-null-pointer-checks flag controls global dataflow analyses and eliminate useless checks for null pointers; It assume that if a pointer is checked after it has already been dereferenced, it cannot be null. This flag is enabled by default. gcc v4.9 has more optimizations added to this option. Hence it is very aggressive with GCC v4.9 series. Add -fno-delete-null-pointer-checks to disable the optimization Signed-off-by: Rohit Dharmakan <rohitarulraj@freescale.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
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