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* dm: pci: Save devfn without bus number in pci_uclass_child_post_bind()Bin Meng2015-08-261-2/+2
| | | | | | | | In pci_uclass_child_post_bind(), bdf is extracted from fdt_pci_addr. Mask bus number before save it to pplat->devfn. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* fdtdec: Fix possible infinite loop in fdtdec_get_pci_vendev()Bin Meng2015-08-261-2/+1
| | | | | | | | When there is no valid compatible string in current list, we should advance to next one in the compatible string list. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* patman: use -D option for git format-patchMasahiro Yamada2015-08-261-1/+1
| | | | | | | | This allows Patman to generate smaller patches for file removal. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Heiko Schocher <hs@denx.de>
* x86: superio: Add keyboard controller support to smsc_lpc47m driverBin Meng2015-08-263-5/+40
| | | | | | | | | Add an api to enable and configure the integrated keyboard controller on SMSC LPC47m superio chipset. It also adds several macros to help future extension. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Call fsp_init_phase_pci() in pci_uclass_post_probe()Bin Meng2015-08-261-0/+21
| | | | | | | | | | | | | | | | | Per Intel FSP specification, we should call FSP notify API to inform FSP that PCI enumeration has been done so that FSP will do any necessary initialization as required by the chipset's BIOS Writer's Guide (BWG). Unfortunately we have to put this call here as with driver model, the enumeration is all done on a lazy basis as needed, so until something is touched on PCI it won't happen. Note we only call this after U-Boot is relocated and root bus has finished probing. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: Remove the fsp_init_phase_pci() callBin Meng2015-08-261-7/+1
| | | | | | | | | It turns out that calling fsp_init_phase_pci() in arch_misc_init() is subject to break pci device drivers as with driver model, when the bus enumeration happens is not deterministic. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: queensbay: Move unprotect_spi_flash() to arch_misc_init()Bin Meng2015-08-261-2/+2
| | | | | | | | | | With dm pci conversion, pci config read/write in unprotect_spi_flash() silently fails as at that time dm pci is not ready and bus enumeration is not done yet. Actually we don't need to do this in that early phase, hence we delay this call to arch_misc_init(). Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Add comments about U-Boot entering start.S twiceBin Meng2015-08-263-4/+6
| | | | | | | | | Add some comments in start.S for the fact that with FSP U-Boot actually enters the code twice. Also change to use fsp_init() and fsp_continue for accuracy. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Enlarge the size of malloc() pool before relocationBin Meng2015-08-263-1/+30
| | | | | | | | | | After fsp_init() returns, the stack has already been switched to a place within system memory as defined by CONFIG_FSP_TEMP_RAM_ADDR. Enlarge the size of malloc() pool before relocation since we have plenty of memory now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: fsp: Delay x86_fsp_init() call a little bitBin Meng2015-08-261-3/+3
| | | | | | | | Move x86_fsp_init() call after initf_malloc() so that we can fix up the gd->malloc_limit later. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: pci: Support selected device/driver binding before relocationBin Meng2015-08-261-11/+30
| | | | | | | | | | | On some platforms pci devices behind bridge need to be probed (eg: a pci uart on recent x86 chipset) before relocation. But we won't bind all devices found during the enumeration. Only devices whose driver with DM_FLAG_PRE_RELOC set will be bound. Any other generic devices except bridges won't be bound. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: ifdtool: Drop microcode from the device tree when collatingSimon Glass2015-08-261-2/+53
| | | | | | | | | | | | | | When ifdtool collates the microcode into one place it effectively creates a copy of the 'data' properties in the device tree microcode nodes. This is wasteful since we now have two copies of the microcode in the ROM. To avoid this, remove the microcode data from the device tree and shrink it down. This means that there is only one copy and the overall ROM space used by the microcode does not increase. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ifdtool: Support collating microcode into one placeSimon Glass2015-08-262-10/+56
| | | | | | | | | | | | | | | | | | | | | The Intel Firmware Support Package (FSP) requires that microcode be provided very early before the device tree can be scanned. We already support adding a pointer to the microcode data in a place where early init code can access. However this just points into the device tree and can only point to a single lot of microcode. For boards which may have different CPU types we must support multiple microcodes and pass all of them to the FSP in one place. Enhance ifdtool to scan all the microcode, place it together in the ROM and update the microcode pointer to point there. This allows us to pass multiple microcode blocks to the FSP using its existing API. Enable the flag in the Makefile so that this feature is used by default for all boards. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ifdtool: Split microcode linking into its own functionSimon Glass2015-08-261-27/+78
| | | | | | | | | | | The code to set up the microcode pointer in the ROM shares almost nothing with the write_uboot() function. Move it into its own function so it will be easier to extend. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: ifdtool: Check that U-Boot does not overlap other regionsSimon Glass2015-08-261-11/+22
| | | | | | | | | | Since U-Boot and its device tree can grow we should check that it does not overlap the regions above it. Track the ROM offset that U-Boot reaches and check that other regions (written after U-Boot) do not interfere. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* x86: baytrail: Support multiple microcode copiesBin Meng2015-08-262-0/+9
| | | | | | | | | | | | Intel FSP has the capability to walk through the microcode blocks which are passed as the TempRamInit() parameter from U-Boot and finds the most appropriate microcode which is suitable for the cpu on which it is running. Now we've seen several steppings for Intel BayTrail series processors, adding those microcodes to the Intel BayleyBay and MinnowMax board device tree files. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: baytrail: Add microcode for BayTrail-I D0 steppingBin Meng2015-08-261-0/+3284
| | | | | | | | This commit adds the microcode blob for BayTrail-I D0 stepping, CPUID signature 30679h. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Simon Glass <sjg@chromium.org>
* x86: Correct microcode documentationSimon Glass2015-08-261-2/+2
| | | | | | | | This is incorrect since we require the -m parameter to the microcode tool. Update the two examples to show this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* efi: Update README.efi to clarify build and test instructionsBin Meng2015-08-261-13/+20
| | | | | | | | | The doc has a misleading 'make menuconfig' when building the EFI application and payload. Clarify this and also update information on test with QEMU. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* x86: Set up video framebuffer for coreboot before loading kernelBin Meng2015-08-261-2/+0
| | | | | | | | | Currenlty we only set up video framebuffer when VIDEO_VESA driver is used. With coreboot, VIDEO_COREBOOT driver is used instead. Since we already saved VESA mode in the VIDEO_COREBOOT driver, now we can also set up video framebuffer for coreboot before loading Linux kernel. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* video: coreboot: Save VESA mode for future useBin Meng2015-08-263-1/+27
| | | | | | | | When booting as a coreboot payload, the framebuffer details are passed from coreboot via configuration tables. We save these information into vesa_mode_info structure for future use. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Enable CONFIG_PCI_CONFIG_HOST_BRIDGE for all boardsBin Meng2015-08-265-4/+1
| | | | | | | It looks that x86 chipset always contains a host bridge at pci b.d.f 0.0.0, so enable this for all boards. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Only include cbfs command for corebootBin Meng2015-08-261-0/+2
| | | | | | When running U-Boot bare-metal, the cbfs command is useless. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: kconfig: Hide "System tables" for corebootBin Meng2015-08-261-1/+1
| | | | | | | When booting as a coreboot payload, we don't need write any configuration tables as coreboot does that for us. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: kconfig: Hide "System tables" for EFIBin Meng2015-08-261-3/+1
| | | | | | | Instead of hiding each menu entries under "System tables" for EFI, hide the main menu completely. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: coreboot: Allow >=4GiB memory bank sizeBin Meng2015-08-261-5/+4
| | | | | | | Some platforms may have >=4GiB memory, so we need make U-Boot report such configuration correctly when booting as the coreboot payload. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: Remove calculate_relocation_address()Bin Meng2015-08-263-60/+2
| | | | | | | Now that we have generic routine to calculate relocation address, remove the x86 specific one which is now only used by coreboot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: coreboot: Correctly report E820 typesBin Meng2015-08-261-2/+13
| | | | | | | coreboot has some extensions (type 6 & 16) to the E820 types. When we detect this, mark it as E820_RESERVED. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: coreboot: Increase memrange entry number to 32Bin Meng2015-08-261-6/+3
| | | | | | | | | Increase lib_sysinfo memrange entry number to 32 to sync with coreboot. This allows a complete E820 table to be reported to the kernel, as on some platforms (eg: Bayley Bay) having only 16 entires does not cover all the memory ranges. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* x86: doc: Update coreboot payload entry point addressBin Meng2015-08-261-3/+3
| | | | | | | | With recent EFI support, the entry point address of coreboot payload was changed. Now we update the address to use _x86boot_start, which is the same one for EFI. Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* net: e1000: Fix build warnings for 32-bitBin Meng2015-08-261-4/+5
| | | | | | | | | | | | | | | | commit 6497e37 "net: e1000: Support 64-bit physical address" causes compiler warnings on 32-bit U-Boot build below. drivers/net/e1000.c: In function 'e1000_configure_tx': drivers/net/e1000.c:4982:2: warning: right shift count >= width of type [enabled by default] drivers/net/e1000.c: In function 'e1000_configure_rx': drivers/net/e1000.c:5126:2: warning: right shift count >= width of type [enabled by default] This commit fixes the build warnings. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* Merge git://git.denx.de/u-boot-pxaTom Rini2015-08-2412-88/+94
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| * arm: pxa: colibri_pxa270: add optional i2c supportMarcel Ziswiler2015-08-241-0/+9
| | | | | | | | | | | | This is useful once Andrew's PXA I2C driver gets merged. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
| * arm: pxa: colibri_pxa270: add optional lcd supportMarcel Ziswiler2015-08-241-0/+13
| | | | | | | | | | | | | | | | Add optional LCD support. Note that depending on the toolchain used one might have to drop some other features to stay within the 0x40000 size limit. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
| * arm: pxa: colibri_pxa270: add some more nor flash detailsMarcel Ziswiler2015-08-241-0/+4
| | | | | | | | | | | | | | Add some more NOR flash details like size, bus width and lock/unlock time outs. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
| * arm: pxa: palmtreo680: get rid of obsolete CONFIG_SYS_LCD_PXA_NO_L_BIASMarcel Ziswiler2015-08-241-1/+0
| | | | | | | | | | | | | | Looks like the define CONFIG_SYS_LCD_PXA_NO_L_BIAS is not used anywhere else throughout the U-Boot sources any more. Drop it. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
| * lcd: pxa: clean-up include file orderMarcel Ziswiler2015-08-241-5/+4
| | | | | | | | | | | | | | Cleaning up order of include files by sorting them alphabetically keeping in mind to leave common.h on top. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
| * usb: pxa27x_udc: clean-up include file orderMarcel Ziswiler2015-08-241-3/+2
| | | | | | | | | | | | | | Cleaning up order of include files by sorting them alphabetically keeping in mind to leave common.h on top. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
| * serial: pxa: clean-up include file orderMarcel Ziswiler2015-08-241-2/+2
| | | | | | | | | | | | | | Cleaning up order of include files by sorting them alphabetically keeping in mind to leave common.h on top. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
| * arm: pxa: mmc: clean-up include file orderMarcel Ziswiler2015-08-241-5/+3
| | | | | | | | | | | | | | Cleaning up order of include files by sorting them alphabetically keeping in mind to leave common.h on top. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
| * arm: pxa: clean-up include file orderMarcel Ziswiler2015-08-242-3/+3
| | | | | | | | | | | | | | Cleaning up order of include files by sorting them alphabetically keeping in mind to leave common.h on top. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
| * arm: pxa: use common timer functionsAndrew Ruder2015-08-243-69/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves pxa to the common timer functions added in commit 8dfafdd - Introduce common timer functions <Rob Herring> The (removed) pxa timer code (specifically __udelay()) could deadlock at the 32-bit boundary of get_ticks(). get_ticks() returned a 32-bit value cast up to a 64-bit value. If get_ticks() + tmo in __udelay() crossed the 32-bit boundary, the while condition became unconditionally true and locked the processor. Rather than patch the specific pxa issues, simply move everything over to the common code. Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com> Cc: Marek Vasut <marex@denx.de> Cc: Tom Rini <trini@konsuiko.com>
| * pxa: Fix boot hang by avoiding vector relocationAndrew Ruder2015-08-242-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since commit 3ff46cc42b9d73d0 ("arm: relocate the exception vectors") pxa does not boot anymore. Add a specific relocate_vectors macro that skips the vector relocation, as the pxa SoC does not provide RAM at the high vectors address (0xFFFF0000), and (0x00000000) maps to ROM. This allows pxa to boot again. Cc: Marek Vasut <marex@denx.de> Signed-off-by: Andrew Ruder <andrew.ruder@elecsyscorp.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2015-08-242-4/+4
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| * MIPS: fix syntax for fdt_chosen/initrd.Govindraj Raja2015-08-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | The syntax for the fdt_chosen/initrd functions seem to deprecated in usage from MIPS bootm implementation. Third parameter is no more used in these api's Refer to : include/fdt_support.h Signed-off-by: Govindraj Raja <govindraj.raja@imgtec.com>
| * mips: Use unsigned int when reading c0 registersChris Packham2015-08-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In commit a18a477 (MIPS: use common code from lib/time.c) MIPS platforms started using common the common timer functions which are based around the fact that many platforms have a 32-bit free running counter register that can be used see commit 8dfafdd (Introduce common timer functions). Even MIPS64 has such a 32-bit register (some have an additional 64-bit free running counter, but that's something for another time). The problem is that in __read_32bit_c0_register() we read the value from this register into an _signed_ int and as it's returned up the call chain to timer_read_counter() it gets assigned to an unsigned long. On a 32-bit system there is no problem. On a 64-bit system odd things happen, sign extension seems to kick in and all of a sudden if the counter register happens to have the MSb (i.e. the sign bit) set the negative int gets sign extended into a very large unsigned long value. This in turn throws out things from get_ticks() up. Update __read_32bit_c0_register() and __read_32bit_c0_ctrl_register() to use "unsigned int res;" instead of "int res;". There seems to be little reason to treat these register values as signed. They are either counters (which by definition are unsigned) or are made up of various bit fields to be interpreted as per the CPU datasheet. Reported-by: Sachin Surendran <sachin.surendran@alliedtelesis.co.nz> Signed-off-by: Chris Packham <judge.packham@gmail.com>
* | Merge git://git.denx.de/u-boot-socfpgaTom Rini2015-08-2349-2760/+3220
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: configs/socfpga_arria5_defconfig configs/socfpga_cyclone5_defconfig configs/socfpga_socrates_defconfig Merged these by hand and re-ran savedefconfig on them. Signed-off-by: Tom Rini <trini@konsulko.com>
| * | arm: socfpga: Fix ArriaV SoCDK PLL configMarek Vasut2015-08-231-13/+13
| | | | | | | | | | | | | | | | | | | | | | | | Pull out the ArriaV SoCDK clock config from ancient Altera U-Boot "rel_socfpga_v2013.01.01_15.05.01_pr" and implant those values into mainline to get a booting ArriaV SoCDK. Signed-off-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: Enable ethernet on ArriaV SoCDKMarek Vasut2015-08-231-0/+3
| | | | | | | | | | | | | | | | | | | | | Synchronise the config options with Cyclone V SoCDK and other boards. This enables ethernet on the ArriaV SoCDK. Signed-off-by: Marek Vasut <marex@denx.de>
| * | arm: socfpga: Fix SD/MMC boot on ArriaV SoCDKMarek Vasut2015-08-231-0/+6
| | | | | | | | | | | | | | | | | | | | | Add the missing DT nodes, so that ArriaV SoCDK can boot from SD card. The SD card must be in slot J5 and BSEL must be 0x5. Signed-off-by: Marek Vasut <marex@denx.de>
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