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| * | x86: config: Enable USB on linkSimon Glass2014-11-251-2/+0
| | | | | | | | | | | | | | | | | | Enable USB support on link - there are two EHCI ports available. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: ivybridge: Set up EHCI USBSimon Glass2014-11-254-0/+33
| | | | | | | | | | | | | | | | | | Add init for EHCI so that USB can be used. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: dts: Add SATA settings for linkSimon Glass2014-11-252-1/+7
| | | | | | | | | | | | | | | | | | Add the requires settings to enable SATA on link. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: ivybridge: Add SATA initSimon Glass2014-11-258-0/+334
| | | | | | | | | | | | | | | | | | Add code to set up the SATA interfaces on boot. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: dts: Add LPC settings for linkSimon Glass2014-11-251-0/+8
| | | | | | | | | | | | | | | | | | Add some settings required to set up the LPC correctly. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: dts: Move PCI peripherals into a pci nodeSimon Glass2014-11-251-13/+15
| | | | | | | | | | | | | | | | | | | | | | | | These peripherals should not be at the top level, since they exist inside the PCI bus. We don't have a full device tree node for pci yet, but we should at least put it at the right level. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: ivybridge: Add additional LPC initSimon Glass2014-11-253-4/+572
| | | | | | | | | | | | | | | | | | | | | Set up all the remaining pieces of the LPC (low-pin-count) peripheral in PCH (Peripheral Controller Hub). Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: ivybridge: Add PCH initSimon Glass2014-11-253-0/+173
| | | | | | | | | | | | | | | | | | Add required init for the Intel Platform Controller Hub in ivybridge. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Add a simple header file for ACPISimon Glass2014-11-251-0/+24
| | | | | | | | | | | | | | | | | | | | | We don't use many features yet, so this only has a few declarations. It will be expanded as needed. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: ivybridge: Add support for BD82x6x PCHSimon Glass2014-11-255-0/+167
| | | | | | | | | | | | | | | | | | Add basic setup for the PCH. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Set up edge triggering on interrupt 9Simon Glass2014-11-252-0/+49
| | | | | | | | | | | | | | | | | | | | | Add this additional init in case it is needed by the OS. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | pci: Add functions to read and write a BAR addressSimon Glass2014-11-252-3/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some PCI functions cannot be auto-configured. Add a function to set up a fixed BAR which can be used in these situations. Also add a function to read the current address of a BAR. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: config: Enable plug-and-play for link PCISimon Glass2014-11-251-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | Enable this option so that we can configure the available PCI devices. Also make sure that PCI is available early after relocation as we use it for several other subsystems. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: pci: Add handlers before and after a PCI hose scanSimon Glass2014-11-252-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | Some boards will want to do some setup before and after a PCI hose is scanned. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Add ioapic.h headerSimon Glass2014-11-251-0/+38
| | | | | | | | | | | | | | | | | | Add definitions for the I/O Advanced Peripheral Interrupt Controller. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | rtc: mc146818: Set up RTC at start of daySimon Glass2014-11-253-5/+45
| | | | | | | | | | | | | | | | | | | | | Provide a function to set up the RTC ready for use. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Factor out common values in the link scriptSimon Glass2014-11-252-7/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | Define the reset base in config.mk so that it does not need to be calculated twice in the link script. Also tidy up the START_16 and RESET_VEC_LOC values to fit with this new approach. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Ensure that all relocation data is included in the imageSimon Glass2014-11-251-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some toolchains put the relocation data into separate sections. Adjust the linker script to catch this case. Without relocation data, U-Boot will not boot. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Panic if there is no relocation dataSimon Glass2014-11-251-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | This normally indicates a problem which will prevent relocation from functioning, resulting in a hang. Panic in this case to make it easier to debug. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | x86: Remove board_early_init_r()Simon Glass2014-11-254-20/+0
| | | | | | | | | | | | | | | | | | | | | | | | This function is not needed. Remove it to improve the generic init sequence slightly. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * | pci: Update pci_ids.h to include some missing IDsSimon Glass2014-11-251-6/+181
| | | | | | | | | | | | | | | | | | | | | This was taken from Linux 3.18 with some additional IDs from Chrome OS Coreboot commit 688ef385. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | Align embedded device tree correctlySimon Glass2014-11-251-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | Device trees must be aligned to a 4-byte boundary. This was dropped in the Kbuild conversion. Bring it back, and use 16-byte alignment for good measure. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | Fix SIZE_MAX compiler warning when using stdint.hSimon Glass2014-11-251-0/+2
| | | | | | | | | | | | | | | | | | | | | This new symbol may be defined by the compiler. If it is, avoid a compiler warning when USE_STDINT is defined. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | x86: Add ivybridge directory to MakefileSimon Glass2014-11-251-0/+2
| | | | | | | | | | | | | | | | | | | | | It is now required to add subdirectories in the x86 cpu Makefile. Add this to fix a build breakage for chromebook_link. Signed-off-by: Simon Glass <sjg@chromium.org>
* | | fs/ext4/ext4fs.c, fs/fs.c fs/fat/fat_write.c: Adjust 64bit math methodsTom Rini2014-12-013-11/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The changes to introduce loff_t into filesize means that we need to do 64bit math on 32bit platforms. Make sure we use the right wrappers for these operations. Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Suriyan Ramasami <suriyan.r@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@ti.com> Tested-by: Pierre Aubert <p.aubert@staubli.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2014-11-2721-30/+500
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| * | | ARM: UniPhier: move CONFIG_CMD_* and CONFIG_FIT* defines to defconfigMasahiro Yamada2014-11-284-15/+75
| | | | | | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | ARM: UniPhier: enable Device Tree controlMasahiro Yamada2014-11-284-0/+4
| | | | | | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | usb: UniPhier: support OF configurationMasahiro Yamada2014-11-2810-4/+109
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_OF_CONTROL is defined, search device tree nodes that are compatible with "panasonic,uniphier-ehci" and take the base address from their "reg" property. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Marek Vasut <marex@denx.de>
| * | | serial: UniPhier: support OF configurationMasahiro Yamada2014-11-287-8/+122
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit implements the ofdata_to_platdata handler for the UniPhier serial driver and adds serial device nodes to the device tree sources. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | ARM: UniPhier: add device tree sourcesMasahiro Yamada2014-11-287-0/+181
| | | | | | | | | | | | | | | | | | | | | | | | This commit adds basic device tree sources for UniPhier SoCs/boards. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | ARM: UniPhier: add dummy gpio.h to enable CONFIG_OF_CONTROLMasahiro Yamada2014-11-281-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled. It includes <asm/gpio.h> and then <asm/gpio.h> includes <asm/arch/gpio.h>. Consequently, all the SoCs that enable CONFIG_OF_CONTROL must have <asm/arch/gpio.h> even if they do not support GPIO. In the first place, GPIO has nothing to do with OF_CONTROL. It is wrong that lib/fdtdec.c includes GPIO functions; it should be split into two files, FDT-common things and GPIO things. It is, however, a pretty big work to fix that correctly. This is a compromised commit to add a dummy <asm/arch/gpio.h> to support OF_CONTROL for UniPhier platform. This dummy header will be removed after FDT-GPIO stuff is fixed correctly. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | ARM: UniPhier: do not compile platform data when CONFIG_OF_CONTROL=yMasahiro Yamada2014-11-283-3/+3
| | |/ | |/| | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2014-11-2710-330/+45
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| * | | MIPS: bootm: remove unused or redundant header filesDaniel Schwierzeck2014-11-271-3/+0
| | | | | | | | | | | | | | | | Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | MIPS: bootm: add missing initramfs relocationDaniel Schwierzeck2014-11-271-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The initramfs is currently only relocated if the user calls the bootm ramdisk subcommand. If bootm should be used without subcommands, the arch-specific bootm code needs to implement the relocation. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | MIPS: remove board.cDaniel Schwierzeck2014-11-272-323/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | After all MIPS boards are switched to generic-board, the MIPS specific board.c can be removed. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | MIPS: vct: switch to generic boardDaniel Schwierzeck2014-11-271-0/+3
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Acked-by: Stefan Roese <sr@denx.de>
| * | | MIPS: qemu_mips: switch to generic boardDaniel Schwierzeck2014-11-272-0/+6
| | | | | | | | | | | | | | | | Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | MIPS: pb1x00: switch to generic boardDaniel Schwierzeck2014-11-271-0/+3
| | | | | | | | | | | | | | | | Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | MIPS: dbau1x00: switch to generic boardDaniel Schwierzeck2014-11-271-0/+3
| | | | | | | | | | | | | | | | Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * | | MIPS: fix setup of initial stack frameDaniel Schwierzeck2014-11-272-4/+10
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | To get correct stack walking and backtrace functionality in gdb, registers fp and ra should be initialized before calling board_init_f or board_init_r. Thus allocating stack space and zeroing it as it is currently done in board.c becomes obsolete. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* | | mtd: nand: s3c: Unify the register definition and namingMarek Vasut2014-11-264-39/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge struct s3c2410_nand and struct s3c2440_nand into one unified struct s3c24x0_nand. While at it, fix up and rename the functions to retrieve the NAND base address and fix up the s3c NAND driver to reflect this change. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Lukasz Majewski <l.majewski@samsung.com> Cc: Minkyu Kang <mk7.kang@samsung.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Vladimir Zapolskiy <vz@mleia.com>
* | | mtd/nand/vf610_nfc: Disable subpage writesSanchayan Maity2014-11-261-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch disables subpage writes for vf610_nfc nand driver. This is required, as without this fix, writing unaligned u-boot images with DFU results in a hang. Trying to write unalgined binary images also results in a hang, without disabling subpage writes. Patch has been tested on a Colibri VF61 module. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
* | | mtd: denali: set some registers after nand_scan_ident()Masahiro Yamada2014-11-261-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some but not all of implementations of the Denali NAND controller have hardware circuits to detect the device parameters such as page_size, erase_size, etc. Even on those SoCs with such hardware supported, the hardware is known to detect wrong parameters for some nasty (almost buggy) NAND devices. The device parameters detected during nand_scan_ident() are more trustworthy. This commit sets some hardware registers to mtd->pagesize, mtd->oobsize, etc. in the code between nand_scan_ident() and nand_scan_tail(). Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Chin Liang See <clsee@altera.com>
* | | mtd: denali: use CONFIG_SYS_NAND_SELF_INITMasahiro Yamada2014-11-263-40/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some variants of the Denali NAND controller need some registers set up based on the device information that has been detected during nand_scan_ident(). CONFIG_SYS_NAND_SELF_INIT has to be defined to insert code between nand_scan_ident() and nand_scan_tail(). It is also helpful to reduce the difference between this driver and its Linux counterpart because this driver was ported from Linux. Moreover, doc/README.nand recommends to use CONFIG_SYS_NAND_SELF_INIT. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Chin Liang See <clsee@altera.com>
* | | nand: reinstate lazy bad block scanningRostislav Lisovy2014-11-261-3/+7
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit ff94bc40af3481d47546595ba73c136de6af6929 ("mtd, ubi, ubifs: resync with Linux-3.14") accidentally reverted part of the commit 13f0fd94e3cae6f8a0d9fba5d367e311edc8ebde ("NAND: Scan bad blocks lazily."). Reinstate the change as by commit fb49454b1b6c7c6e238ac3c0b1e302e73eb1a1ea ("nand: reinstate lazy bad block scanning") Signed-off-by: Rostislav Lisovy <lisovy@merica.cz> Acked-by: Heiko Schocher <hs@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2014-11-2619-71/+335
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| * | arm: ls102xa: Select ge2_clk125 for eTSEC clock muxingAlison Wang2014-11-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EC1 pins in RCW can be selected as RGMII1, GPIO3, CAN1/2, FTM1 or SAI1/2. There is a bug that EC3 RGMII could not work when selecting EC1 as other functionality except RGMII. The workaround is to select ge2_clk125 for eTSEC clock muxing in register SCFG_ETSECCMCR. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arm: ls102xa: Add SystemID EEPROM support for LS1021ATWR boardAlison Wang2014-11-242-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SystemID information could be read through I2C1 from EEPROM on LS1021ATWR board. As LS1 is a little-endian processor, getting the version ID by be32_to_cpu() is wrong. Fix it by using e.version directly. This change will be compatible for both ARM and PowerPC. As there is an errata that I2C1 could not work in SD boot, reading EEPROM through I2C1 is disabled too in SD boot. Signed-off-by: Alison Wang <alison.wang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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