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* image: fix getenv_bootm_size() functionMasahiro Yamada2016-01-191-2/+2
| | | | | | | | Currently, this function returns wrong size if "bootm_low" is defined, but "bootm_size" is not. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch 'master' of git://git.denx.de/u-boot-mipsTom Rini2016-01-1654-1026/+2396
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| * MIPS: implement bit manipulating I/O accessorsDaniel Schwierzeck2016-01-161-0/+55
| | | | | | | | | | | | | | Add support for functions clrbits_X(), setbits_X() and clrsetbits_X() on MIPS. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: fix SPDX license identifier in remaining arch header filesDaniel Schwierzeck2016-01-1614-55/+32
| | | | | | | | | | | | | | Add a SPDX license identifier to MIPS header files where it is still missing. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: sync processor and register definitions with linux-4.4Daniel Schwierzeck2016-01-168-553/+1211
| | | | | | | | | | | | | | Update definitions for processor, registers as well as assemby macros. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: sync I/O related header files with linux-4.4Daniel Schwierzeck2016-01-1610-364/+941
| | | | | | | | | | | | | | | | | | | | | | | | | | Mainly sync asm/io.h to get a working ioremap() implementation as well as the full set of I/O accessors. Pull in additional header files to make this work. Furthermore port over the directory 'arch/mips/include/asm/mach-generic/' with contains default definitions for I/O and memory spaces and default implementations for mapping those spaces. All files in that directory can be overwritten by a SoC/machine. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * net: pcnet: refactor mapping of virtual addresses to physical onesDaniel Schwierzeck2016-01-161-7/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pci_virt_to_mem() uses virt_to_phys() to get the physical address. But pci_virt_to_mem() is also called with uncached addresses which is wrong according to the documentation of virt_to_phys(). Refactor the PCI_TO_MEM() macro to optionally map an uncached address back to a cached one before calling pci_virt_to_mem(). Currently pcnet works because virt_to_phys() is incorrectly implemented on MIPS. With the upcoming asm header file update for MIPS, the virt_to_phys() implementation will be fixed. Thus this patch is needed to keep pcnet working on MIPS Malta board. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: kconfig: add option for MIPS_L1_CACHE_SHIFTDaniel Schwierzeck2016-01-162-10/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Kconfig symbol for L1 cache shift like the kernel does. The value of CONFIG_SYS_CACHELINE_SIZE is not a reliable source for ARCH_DMA_MINALIGN anymore, because it is optional on MIPS. If CONFIG_SYS_CACHELINE_SIZE is not defined by a board, the cache sizes are automatically detected and ARCH_DMA_MINALIGN would be set to 128 Bytes. The default value for CONFIG_MIPS_L1_CACHE_SHIFT is 5 which corresponds to 32 Bytes. All current MIPS boards already used that value. While on it, fix the Malta board to use a value of 6 like the kernel port does. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: vct: fix I/O accessor callsDaniel Schwierzeck2016-01-161-2/+4
| | | | | | | | | | | | | | | | Use void pointers as address argument for readl( and writel()). This is required for the upcoming MIPS asm header file and I/O accessor update. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: malta: fix IO accessor callDaniel Schwierzeck2016-01-161-1/+2
| | | | | | | | | | | | | | Use void pointer as address argument for readl(). This is required for the upcoming MIPS asm header file and I/O accessor update. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: malta: do not pull in target header files in config.hDaniel Schwierzeck2016-01-161-6/+3
| | | | | | | | | | | | | | | | | | config.h is used in target and host code and therefore should not pull in target header files to avoid compile errors. This change is also required for the MIPS header file sync done in follow-up patches. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: Kconfig: optimize gcc -march and -mtune setupDaniel Schwierzeck2016-01-164-15/+24
| | | | | | | | | | | | | | | | Move setup of -march to arch/mips/Makefile and follow the design on ARM. Also add a possibility to chose specific CPU tune options. Signed-off-by: Wills Wang <wills.wang@live.com> Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: au1x00: move SoC header files to arch/mips/mach-au1x00/include/mach/Daniel Schwierzeck2016-01-168-7/+7
| | | | | | | | Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: Kconfig: refactor machine setupDaniel Schwierzeck2016-01-161-1/+6
| | | | | | | | | | | | | | | | Refactor machine setup like it is done on ARM. While on it, also support "include <mach/file.h" for machine specific header files. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: add initial infrastructure for device-tree filesDaniel Schwierzeck2016-01-167-1/+44
| | | | | | | | | | | | | | | | Prepare sub-folder for device-tree files. Make support for device-tree on MIPS available in Kbuild/Kconfig. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com>
| * MIPS: do not build position-independent executables for SPLDaniel Schwierzeck2016-01-161-4/+14
| | | | | | | | | | | | | | | | | | SPL binaries are usually linked to a fixed address in SRAM. Furthermore SPL binaries do not need to relocate itself. Thus do not build them as position-independent binaries which helps to largely reduce the size of SPL binaries. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: create .text sub-sections for assembler functionsDaniel Schwierzeck2016-01-161-1/+3
| | | | | | | | | | | | | | | | Put all functions coded in assembly in sub-sections of section .text. This allows the linker to garbage collect unused assembly functions too. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: fix annotation of _start and relocate_codeDaniel Schwierzeck2016-01-162-7/+11
| | | | | | | | | | | | | | Correctly annotate _start and relocate_code as functions to produce more readable disassembly code generated by objdump. Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
| * MIPS: add asm/gpio.h to fix compilation error with CONFIG_CMD_GPIO.Purna Chandra Mandal2016-01-161-0/+1
| | | | | | | | | | | | | | | | | | | | With CONFIG_CMD_GPIO compilation reports error. common/cmd_gpio.c:13:22: fatal error: asm/gpio.h: No such file or directory #include <asm/gpio.h> ^ Signed-off-by: Purna Chandra Mandal <purna.mandal@microchip.com> Reviewed-by: Chin Liang See <clsee@altera.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-socfpgaTom Rini2016-01-163-32/+47
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| * | socfpga: Modify qts-filter args to allow input for bsp generated files and ↵Dalon Westergreen2016-01-161-31/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | quartus project directories The hps_isw_handoff and bsp/generated folders are typically not in the same path.This patch adds support for specifying the different input directories for the bsp and quartus projects. Signed-off-by: Dalon Westergreen <dwesterg@gmail.com> Acked-by: Marek Vasut <marex@denx.de> Acked-by: Chin Liang See <clsee@altera.com>
| * | arm: socfpga: set the fpga global bit to disable HPS to FPGA signalsDinh Nguyen2016-01-161-1/+1
| | | | | | | | | | | | | | | | | | | | | We should be setting the FPGA Interface Group global bit that will correctly disable all interfaces between the FPGA and HPS. Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
| * | ddr: altera: Init the rule ID in debug codeMarek Vasut2016-01-161-0/+1
| |/ | | | | | | | | | | | | | | | | | | Init the rule ID, otherwise the debug code will always dump the protection settings entry 0. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@opensource.altera.com> Cc: Dinh Nguyen <dinh.linux@gmail.com>
* | common: usb: fix checking conditionPeng Fan2016-01-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | We support max USB_MAXENDPOINTS, so need to use "epno >= USB_MAXENDPOINTS", but not "epno > USB_MAXENDPOINTS". If use ">", we may exceeds the array of if_desc->ep_desc. Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Hans de Goede <hdegoede@redhat.com> Cc: Marek Vasut <marex@denx.de> Cc: Paul Kocialkowski <contact@paulk.fr> Cc: "Stefan Brüns" <stefan.bruens@rwth-aachen.de> Cc: Vincent Palatin <vpalatin@chromium.org>
* | usb: host: ehci-vf: Implement board_usb_phy_mode weak functionSanchayan Maity2016-01-161-0/+10
| | | | | | | | | | | | | | | | | | | | Add board_usb_phy_mode weak function on similar lines to ehci-mx6. However since Vybrid USB does not have a true OTG, make this weak functon just return 0. The function is supposed to be implemented by the individual boards using a GPIO for providing the OTG pin functionality. Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
* | usb: host: ehci-vf: Remove hardcoded USB host client configurationSanchayan Maity2016-01-161-5/+0
| | | | | | | | | | | | | | | | The current ehci-vf USB driver for Vybrid hardcodes the USB host and client functionality. Remove this. Reported-by: Santhosh Kumar Janardhanam <santhosh.kj@hcl.com> Signed-off-by: Sanchayan Maity <maitysanchayan@gmail.com>
* | usb:ci_udc: Remove ULPI setting for i.MX OTG controllerYe.Li2016-01-161-11/+3
|/ | | | | | | | | All the i.MX6, i.MX23 and i.MX28 OTG controllers only support UTMI interface. Set to ULPI is not correct, even the controller will reject this setting in PORTSC register. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* Merge git://git.denx.de/u-boot-rockchipTom Rini2016-01-153-1/+15
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| * dm: spi_flash: Allow the uclass to work without printf()Simon Glass2016-01-151-1/+7
| | | | | | | | | | | | | | For SPL we don't really need sprintf() and with tiny-printf this is not available. Allow this to be dropped in SPL when using tiny-printf. Signed-off-by: Simon Glass <sjg@chromium.org>
| * mmc: rockchip: the non-removable property must point to emmchuang lin2016-01-151-0/+2
| | | | | | | | | | | | | | | | | | the non-removable property point to sdcard before, it is wrong, it must point to emmc, correct it. Signed-off-by: Lin Huang <hl@rock-chips.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * MAINTAINERS: add entry for RockchipMasahiro Yamada2016-01-151-0/+6
| | | | | | | | | | | | | | | | Rockchip has its own git repository maintained by Simon. Document this. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: Simon Glass <sjg@chromium.org>
* | eth-raw-os.c: Add cast to bind(2) callTom Rini2016-01-151-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | With more recent gcc versions we otherwise get an error like: note: expected 'const struct sockaddr *' but argument is of type 'struct sockaddr_in *' and the common solution here is to cast, rather than re-work the code. Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* | x86: Fix board init breakageSimon Glass2016-01-151-1/+1
| | | | | | | | | | | | | | | | | | Commit ecc30663 ("Fix board init code to respect the C runtime environment") breaks x86. This was mentioned on https://patchwork.ozlabs.org/patch/548644 but not addressed. Correct it so that x86 boards boot again. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | dm: pci: Avoid a memory leak when allocating the ROMSimon Glass2016-01-151-12/+33
| | | | | | | | | | | | | | | | | | | | Adjust pci_rom_load() to return an indication of whether it allocated memory or not. Adjust the caller to free it. This fixes a memory leak when PCI_VGA_RAM_IMAGE_START is not used. Reported-by: Coverity (CID: 134194) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | dm: pci: Add a 'fall through' commentSimon Glass2016-01-151-0/+1
| | | | | | | | | | | | | | | | | | For this class it is intended to set up the PCI device, so add a comment to indicate this. This avoids a coverity warning. Reported-by: Coverity (CID: 134194) Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* | Fix GCC format-security errors and convert sprintfs.Ben Whitten2016-01-1453-72/+75
|/ | | | | | | | | | | With format-security errors turned on, GCC picks up the use of sprintf with a format parameter not being a string literal. Simple uses of sprintf are also converted to use strcpy. Signed-off-by: Ben Whitten <ben.whitten@gmail.com> Acked-by: Wolfgang Denk <wd@denx.de> Reviewed-by: Tom Rini <trini@konsulko.com>
* Merge branch 'master' of git://git.denx.de/u-boot-x86Tom Rini2016-01-1431-105/+3143
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| * x86: qemu: add documentaion for the fw_cfg interfaceMiao Yan2016-01-131-3/+31
| | | | | | | | | | | | | | | | Document the usage of 'qfw' command Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: qemu: remove cpu node in device treeMiao Yan2016-01-132-14/+0
| | | | | | | | | | | | | | | | | | Remove 'cpu' node in device tree for QEMU targets, and let U-Boot detect and fix up those information at runtime. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: qemu: fix cpu device in smp bootMiao Yan2016-01-132-11/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, when booting with more that one CPU enabled, U-Boot scans 'cpu' node in device tree and calculates CPU number. This does not scale well as changing CPU number also requires modifying .dts and re-compiling U-Boot. This patch uses fw_cfg interface provided by QEMU to detect online CPU number at runtime, and dynamically adds 'cpu' device to U-Boot's driver model. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: use actual CPU number for allocating memoryMiao Yan2016-01-131-3/+3
| | | | | | | | | | | | | | | | | | | | Use actual CPU number, instead of maximum cpu configured, to allocate stack memory in 'load_sipi_vector' Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: fix a typo in function nameMiao Yan2016-01-131-3/+3
| | | | | | | | | | | | | | | | | | Rename 'find_cpu_by_apid_id' to 'find_cpu_by_apic_id'. This should be a typo. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: qemu: add a cpu uclass driver for qemu targetMiao Yan2016-01-134-5/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a cpu uclass driver for qemu. Previously, the qemu target gets cpu number from board dts files, which are manually created at compile time. This does not scale when more cpus are assigned to guest as the dts files must be modified as well. This patch adds a cpu uclass driver for qemu targets to directly read online cpu number from firmware. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: qemu: add fw_cfg supportMiao Yan2016-01-134-1/+380
| | | | | | | | | | | | | | | | | | | | | | | | | | The QEMU fw_cfg interface allows the guest to retrieve various data information from QEMU. For example, APCI/SMBios tables, number of online cpus, kernel data and command line, etc. This patch adds support for QEMU fw_cfg interface. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: adjust ramdisk load addressMiao Yan2016-01-131-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | By default, ramdisk load address is defined to 02000000 in env string. When loading bzImage to 01000000 (default address), there's a chance that the ramdisk header would be overwritten by the kernel. Thus increase the gap and make ramdisk load at 04000000 by default and also this patch introduces a new configuration item CONFIG_RAMDISK_ADDR for this purpose Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * x86: ivybridge: Add macros for LPC decode rangesBin Meng2016-01-131-0/+10
| | | | | | | | | | | | | | | | Add several macros for LPC decode registers on PCH. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * x86: fsp: Always use hex numbers in the hob command outputBin Meng2016-01-131-2/+2
| | | | | | | | | | | | | | | | | | In the 'fsp hob' command output, decimal numbers and hexadecimal numbers are used mixedly. Now change to always use hex numbers to keep consistency. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
| * x86: ivybridge: Do not require HAVE_INTEL_MEBin Meng2016-01-133-1/+2
| | | | | | | | | | | | | | | | | | Do not set HAVE_INTEL_ME by default as for some cases Intel ME firmware even does not reside on the same SPI flash as U-Boot. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * x86: ivybridge: Add microcode blobs for all the steppingsBin Meng2016-01-134-0/+2472
| | | | | | | | | | | | | | | | | | | | | | This adds microcode blobs created from Intel FSP package for the Chief River platform. They are for all the Ivy Bridge steppings: 306a2 (B0), 306a4 (C0), 306a5 (K0/M0), 306a8 (E0/L0), except the 306a9 which is already in the U-Boot tree. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org>
| * tools: microcode-tool: Support parsing header file with a license blockBin Meng2016-01-131-0/+14
| | | | | | | | | | | | | | | | | | The microcode header files in the Intel Chief River FSP package have a license comment block. Update the microcode-tool to support parsing it and extract the license text to the .dtsi file. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
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