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| * sunxi: Add mk802 board / defconfigHans de Goede2015-01-222-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | The mk802 is the "classic" Allwinner A10 based hdmi tv-stick, it features 512M or 1G RAM, 4G nand, a mini-hdmi female connector, USB-A receptacle, mini-usb receptacle (OTG) and USB-wifi. Somewhat unique the mk802 does not use the AXP209 pmic, it does not have a pmic at all. For more details see: http://linux-sunxi.org/Rikomagic_mk802 Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Remove CONFIG_TARGET_FOO for sun4i, sun6i and sun8i boardsHans de Goede2015-01-2212-64/+9
| | | | | | | | | | | | | | | | | | | | CONFIG_TARGET_FOO is only used in board/sunxi/Makefile to select the dram config for sun5i and sun7i boards and in board/sunxi/gmac.c for some special handling of the bananapi/bananapro (both sun7i), iow it is not used at all on any sun4i, sun6i and sun8i boards so lets get rid of it there. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Convert sun4i boards to use auto dram configurationHans de Goede2015-01-227-99/+10
| | | | | | | | | | | | | | | | | | | | | | | | Currently we've separate detailed dram settings for all sun4i boards, this moves them over to using auto dram configuration so that we can get rid of all the per board dram_foo.c files. Tested-by: Hans de Goede <hdegoede@redhat.com> on a A10-OLinuXino-Lime, Chuwi_V7_CW0825 and ba10_tv_box Tested-by: Zoltan HERPAI <wigyori@uid0.hu> on a pcduino Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Stop differentiating between 512M and 1G variants of the same boardHans de Goede2015-01-2213-142/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While working on adding more boards I noticed that we lack a config for the 512M cubieboard, and that some of the new boards which I want to add also have 512M and 1G variants, rather then adding 2 defconfig's for all of these, lets switch the exising boards which have both a 512M and 1024M variant over to the sun4i dram autoconfig code. This also drops the foo_RAMSIZE_defconfig variants of boards where we currently have 2 separate configs already. Note: 1) The newly introduced CONFIG_DRAM_EMR1 kconfig value is not used with a value other then its default for now, but we need this to be configurable to support some new boards with auto dram config. 2) We always set all CONFIG_DRAM_foo values in defconfigs, even if they match the defaults, this is done to make it more clear what values are used for a certain board. This has been tested on a Mele A1000, Mini-X and a Cubieboard, all 1G variants, the dram autoconfig code has also been tested on a 512M mk802 (a defconfig for the mk802 is added in a later patch). Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: ba10_tv_box_defconfig: Fix USB not workingHans de Goede2015-01-221-1/+1
| | | | | | | | | | | | | | PH12 is Vbus enable for Vbus2, not Vbus1. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: axp209: Disable interrupts when intializing the axp209Hans de Goede2015-01-221-1/+13
| | | | | | | | | | | | | | | | | | | | We do not use the axp209 interrupt, and at least in my mini-x (which does not have a power button) the pwr-button pin and the irq pin are soldered together, so if the axp209 keeps it irq asserted too long it will see a 10s pwr-button press and hard power off the board, disabling the irqs fixes this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: mmc: Add support for sun9i (A80)Hans de Goede2015-01-222-4/+20
| | | | | | | | | | | | | | The clocks on the A80 are hooked up slightly different, add support for this. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: mmc: Use a realistic timeout when sending a mmc commandHans de Goede2015-01-221-1/+1
| | | | | | | | | | | | | | | | Wait 1 second for the sdcard to respond, rather then waiting for 0xfffff milliseconds. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sun9i: Add sun9i (A80) clock setup supportHans de Goede2015-01-222-0/+69
| | | | | | | | | | | | | | | | Add initial sun9i (A80) clock setup support, enough to get the uart + mmc going. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sun9i: Add clock_sun9i.h with ccu register layout for sun9iHans de Goede2015-01-222-0/+141
| | | | | | | | | | | | | | Add a headerfile with the sun9i ccu register layout. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sun9i: Add cpu_sun9i.h with iomem definesHans de Goede2015-01-222-0/+112
| | | | | | | | | | | | | | Add a headerfile with all the base addresses from the sun9i blocks. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Rename cpu.h to cpu_sun4i.hHans de Goede2015-01-222-145/+157
| | | | | | | | | | | | | | | | | | sun4i - sun8i have (aprox.) the same iomem layout, but sun9i is quite different, so add a wrapper cpu.h which includes the right mach specific cpu_sun#i.h based on mach, like we already do with clock.h and dram.h . Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Move clock_get_pllX / clock_set_pllX protos to mach specific headersHans de Goede2015-01-223-4/+12
| | | | | | | | | | | | | | | | | | | | | | Which pll-s are available depends on the machine type, move the clock_get_pllX / clock_set_pllX prototypes to the clock_sun?i.h header files so that we only declare what is actually available. e.g. clock_get_pll5p() is not available on sun6i / sun8i, and with sun9i we get a completely different set of plls. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: Drop pll6 setting from clock_init_uartHans de Goede2015-01-221-4/+1
| | | | | | | | | | | | | | | | As the comment says now that we have SPL support this is no longer necessary, as PLL6 is already setup with the exact same parameters by the SPL. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
| * sunxi: display: Make lcd display clk phase configurableHans de Goede2015-01-226-9/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While running some tests with an Olinuxino-A13-Micro + a 7" Olimex LCD module I noticed that the screen flickered. This is caused by the lcd display clk phase reg value being set to 0, where it should be 1 in this setup. This commit adds a Kconfig option for the lcd display clk phase, so that we can set it per board. This defaults to 1, because looking at all the fex files in sunxi-boards, that is by far the most used value. This commit updated the Ippo and MSI Primo73 tablet defconfigs to override the default of 1 with 0, as that is the correct value for those tablets, this keeps the register settings the same as before this commit. The Olinuxino-A13 defconfigs are not updated, changing the register setting for these boards from 0 to 1, this is intentional. Signed-off-by: Hans de Goede <hdegoede@redhat.com> Acked-by: Ian Campbell <ijc@hellion.org.uk>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2015-01-2248-132/+1582
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| * | board/T1040rdb: Add VSC9953 support for T1040rdb boardCodrin Ciubotariu2015-01-212-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | This patch configures and initializes the L2 switch on T1040rdb board. The external L2 switch ports may be connected to PHYs only over QSGMII, for T1040rdb. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
| * | board/T1040qds: Add VSC9953 support for T1040qds boardCodrin Ciubotariu2015-01-212-0/+97
| | | | | | | | | | | | | | | | | | | | | | | | This patch configures and initializes the L2 switch on T1040QDS board. The L2 switch ports must be initialized according to the SerDes protocols. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
| * | board/T104xrdb: T1040 FMAN ports FM1@DTSEC1 and FM1@DTSEC2 have no PHYsCodrin Ciubotariu2015-01-211-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's T1040qds board may be configured to have up to 5 FMAN ports (FM1@DTSEC1 to FM1@DTSEC5). From these 5 ports, 2 of them may be fixed-links (FM1@DTSEC1 annd FM1@DTSEC2), connected to other two ports from an intergrated VSC9953 L2 Switch (switch ports 8 and 9). These fixed-link ports have no PHYs attatched, so they don't have a corresponding MDIO. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | board/T1040qds: T1040 FMAN ports FM1@DTSEC1 and FM1@DTSEC2 have no PHYsCodrin Ciubotariu2015-01-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's T1040qds board may be configured to have up to 5 FMAN ports (FM1@DTSEC1 to FM1@DTSEC5). From these 5 ports, 2 of them may be fixed-links (FM1@DTSEC1 annd FM1@DTSEC2), connected to other two ports from an intergrated VSC9953 L2 Switch (switch ports 8 and 9). These fixed-link ports have no PHYs attatched, so they don't have a corresponding MDIO. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | board/T1040qds: Fix lane-to-slot mapping for SerDes protocol 0x89Codrin Ciubotariu2015-01-211-0/+1
| | | | | | | | | | | | | | | Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arch/powerpc: Initialize VSC9953 L2 SwitchCodrin Ciubotariu2015-01-211-0/+5
| | | | | | | | | | | | | | | | | | | | | This patch initializes VSC9953 L2 Switch for boards that have CONFIG_VSC9953 defined in their config file. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com>
| * | net/vsc9953: Add driver for Vitesse VSC9953 L2 Switch IPCodrin Ciubotariu2015-01-164-0/+948
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a driver for VSC9953 L2 Switch. This Vitesse IP is integrated in Freescale T1040 and T1020 SoCs. The L2 switch has 10 Ethernet ports: 2 internal fixed-links (ports 8 and 9) at 2.5 Gbps and and 8 external ports at 1 Gbps. The external ports may be connected to PHYs over QSGMII and SGMII. Commands have also been added to enable/disable a port and to check a port's link speed, duplexity and status. The commands are: ethsw port <port_nr> enable|disable - enable/disable an l2 switch port ethsw port <port_nr> show - show an l2 switch port's configuration port_nr=0..9; use "all" for all ports For more detailse please see doc/README.t1040-l2switch Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | net/fm: Enable FMAN ports if l2switch ports are connected over SGMIICodrin Ciubotariu2015-01-161-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If SerDes is configured to connect L2 Switch ports from T1040 over SGMII or QSGMII, the two FMAN fixed ports (FM1@DTSEC1 and FM2@DTSEC2) that are connected to two L2 swtch ports must be enabled. These ports don't have PHYs and must be treated accordingly. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arch/powerpc: Add SGMII support for the L2 Switch portsCodrin Ciubotariu2015-01-163-4/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some Freescale SoCs like T1020 and T1040 have an integrated L2 Switch. The L2 Switch ports may be connected to Ethernet PHYs over SGMII and QSGMII. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | arch/powerpc: Fix mapping of Freescale SerDes protocolsCodrin Ciubotariu2015-01-162-30/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The number of supported serdes protocols on Freescale SoCs has increased over time. Until now, an u64 variable have been initialized on boot with the configured protocols. However, since this number has increased (enum srds_prtcl has more than 64 values), 64 bits are no longer sufficient to hold track of all the configured protocols. This patch replaces the u64 map values with static arrays. To keep track of the number of serdes protocols, the SERDES_PRCTL_COUNT vale has been added at the end of enum srds_prtcl. This value must always be the last one. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | net/fm: Fix error when FMAN MAC has no PHYCodrin Ciubotariu2015-01-161-12/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-boot assumes that all FMAN ports have a PHY. Some SoCs (like T1040) have fixed links. This means that the ports are connected MAC to MAc and there is no Ethernet PHY attatched. This patch initializes a FMAN MAC even if it doesn't have a PHY attached. Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | phylib: add support for aquantia PHYsShaohui Xie2015-01-164-0/+161
| | | | | | | | | | | | | | | | | | | | | | | | This patch supports AQ1202, AQ2104, AQR105 PHY. Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | mpc85xx: clean up the old deep sleep frameworktang yuantian2015-01-162-30/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | All the boards that support deep sleep feature are converted to deep sleep generic board interface. The old interface which support non-generic board is not used anymore. So clean it up. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | mpc85xx/t1040qds: convert deep sleep to generic board interfacetang yuantian2015-01-163-12/+33
| | | | | | | | | | | | | | | | | | | | | | | | A new deep sleep interface is introduced to support generic board structure. Converts it to use new interface. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | mpc85xx/t102xqds: convert deep sleep to generic board interfacetang yuantian2015-01-163-12/+33
| | | | | | | | | | | | | | | | | | | | | | | | A new deep sleep interface is introduced to support generic board structure. Converts it to use new interface. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc/t1024rdb: Add support for T1024RDB-PBShengzhou Liu2015-01-164-4/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | T1024RDB-PB board adds 2.5G SGMII support with AQR105 PHY. rcw_0x095 is used for 10G XFI + 3x PCIex1 rcw_0x135 is used for 2.5G SGMII + 2x PCIex1 Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | mpc85xx/t102xrdb: convert deep sleep to generic board interfacetang yuantian2015-01-164-21/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A new deep sleep interface is introduced to support generic board structure. Converts it to use new interface. Besides, added SPI/SD/NAND boot deep sleep support. Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | t1024qds: add missing T1024QDS_defconfigShengzhou Liu2015-01-161-0/+4
| | | | | | | | | | | | | | | | | | | | | Add missing T1024QDS_defconfig for NOR boot on T1024QDS. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc/t1024: add serdes protocol 0x40 and 0x5fShengzhou Liu2015-01-161-0/+2
| | | | | | | | | | | | | | | | | | | | | Add serdes protocol 0x40 and 0x5f. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc: SECURE BOOT- Add secure boot target for T1042RDBgaurav rana2015-01-162-0/+5
| | | | | | | | | | | | | | | | | | | | | Secure boot target is added for T1042RDB platform. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc/913x: Add config flag for bootdelayharninder rai2015-01-162-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_BOOTDELAY is missing from board header file. Add this macro to enable counting down of auto boot. Signed-off-by: Harninder Rai <harninder.rai@freescale.com> [York Sun: Add commit message] Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc/mpc85xx: Define PBI Flash Base for C29XPCIE Secure BootAneesh Bansal2015-01-161-0/+2
| | | | | | | | | | | | | | | | | | | | | CONFIG_SYS_PBI_FLASH_BASE is defined for Secure Boot on C29X Signed-off-by: Aneesh Bansal <aneesh.bansal@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | b4860: Correct LIODN assignment for PCIeTudor Laurentiu2015-01-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For B4 the LIODN register for PCIe is in PCIe address space and not in GUTs Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Varun Sethi <Varun.Sethi@freescale.com> Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Laurentiu Tudor <Laurentiu.Tudor@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc/t4240rdb: Add alternate SerDes 2 protocol to align with RCWChunhe Lan2015-01-162-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | SerDes 2 protocol 56 is not valid any longer due to the new RCW; protocol 55 is used instead, so add SerDes 2 protocol 55 to align with RCW. Signed-off-by: Chunhe Lan <Chunhe.Lan@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc: mpc85xx: Add dummy gpio.h to enable CONFIG_OF_CONTROLRuchika Gupta2015-01-161-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_OF_CONTROL is enabled, lib/fdtdec.c is compiled. It includes <asm/gpio.h> and then <asm/gpio.h> includes <asm/arch/gpio.h>. As a result, all the SoCs that enable CONFIG_OF_CONTROL must have <asm/arch/gpio.h>. The right fix would be to split the lib/fdtdec.c to remove dependency on GPIO. This commit adds a dummy <asm/arch/gpio.h> to support OF_CONTROL for mpc85xx platform. A file mpc85xx_gpio.h exists in arch/powerpc/include/asm. The defintions in that file conflict with the ones in asm-generic/gpio.h. Hence a dummy header file has been added. This will be removed after FDT-GPIO stuff is fixed correctly. Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc/mpc85xx: SECURE BOOT- Add secure boot target for P5040DSgaurav rana2015-01-162-0/+5
| | | | | | | | | | | | | | | | | | | | | Secure boot target is added for P5040DS platform. Signed-off-by: Gaurav Rana <gaurav.rana@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | powerpc/c29xpcie: Add secure boot supportPo Liu2015-01-164-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | Add NOR and SPI flash secure boot target for C29XPCIE board. Signed-off-by: Po Liu <Po.Liu@freescale.com> Signed-off-by: Mingkai.Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2015-01-2212-1126/+128
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| * | | ARM: UniPhier: add SG_MEMCONF macros for DDR channel 2Masahiro Yamada2015-01-231-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | PH1-sLD3, PH1-LD6b have DDR channel 2. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | ARM: UniPhier: rename SG_MEMCONF_* macros for readabilityMasahiro Yamada2015-01-231-20/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Match the suffixes of SG_MEMCONF_* macros with SZ_* macros defined by <linux/sizes.h> for readability. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | ARM: UniPhier: use <linux/sizes.h> for readabilityMasahiro Yamada2015-01-231-12/+13
| | | | | | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | ARM: UniPhier: remove non-sense inline directivesMasahiro Yamada2015-01-233-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The inlining is done by GCC when needed, there is no need to do it explicitly. Furthermore, the inline keyword does not force-inline the code, but is only a hint for the compiler. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | ARM: UniPhier: add static to local functionsMasahiro Yamada2015-01-236-15/+15
| | | | | | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * | | ARM: UniPhier: fix IECTRL set code for PH1-Pro4Masahiro Yamada2015-01-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For PH1-Pro4, the bit 6 of the IECTRL must be set. It is the only available bit in this register. There is no effect of the write access to the other bits. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
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