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* mx6_common: Fix LOADADDR and SYS_TEXT_BASE for i.MX6ULPeng Fan2015-08-021-1/+1
| | | | | | | DRAM space starts from 0x80000000 for i.MX6UL, so need to fix LOADADDR, SYS_TEXT_BASE. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* mxc: gpio add i.MX6UL supportPeng Fan2015-08-021-0/+4
| | | | | | i.MX6UL does not have GPIO6/7, so do not include them for i.MX6UL. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* imx: mx6 add PAD_CTL_SPEED_LOW for i.MX6SX/ULPeng Fan2015-08-021-0/+4
| | | | | | | PAD_CTL_SPEED_LOW for i.MX6SX/UL is (0 << 6) Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* imx: mx6ul update soc related settingsPeng Fan2015-08-021-5/+4
| | | | | | | | 1.Update WDOG settings. 2.No need to gate/ungate all PFDs for i.MX6UL. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* imx: mx6ul select SYS_L2CACHE_OFFPeng Fan2015-08-021-0/+4
| | | | | | | | | i.MX6UL features an Cortex-A7 core, it does not have PL310 as other i.MX6 chips. To Cortex-A7 core, If D-Cache is enabled, L2 Cache is enabled. There is on specific switch for on/off L2 Cache, so default select SYS_L2CACHE_OFF. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* imx:mx6ul add clock supportPeng Fan2015-08-022-90/+159
| | | | | | | | | | | | | | | 1. Add enet, uart, i2c, ipg clock support for i.MX6UL. 2. Correct get_periph_clk, it should account for MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK. 3. Refactor get_mmdc_ch0_clk to make all i.MX6 share one function, but not use 'ifdef'. 4. Use CONFIG_FSL_QSPI for enable_qspi_clk, but not #ifdef CONFIG_MX6SX. 5. Use CONFIG_PCIE_IMX for pcie clock settings, use CONFIG_CMD_SATA for sata clock settings. In this way, we not need "#if defined(CONFIG_MX6Q) || defined....", only need one CONFIG_PCIE_IMX in header file. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* imx: mx6ul remove errata for i.MX6ULPeng Fan2015-08-021-1/+3
| | | | | | | | Since i.MX6UL use A7 core, but not A9 core, we do not need the erratas for i.MX6UL. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* imx-common: timer: add i.MX6UL supportPeng Fan2015-08-021-3/+5
| | | | | | Add i.MX6UL GPT timer support. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* imx: mx6ul Add CONFIG_SYS_CACHELINE_SIZE for i.MX6ULPeng Fan2015-08-021-0/+4
| | | | | | | Since i.MX6UL's cache line size is 64bytes, need to define the macro CONFIG_SYS_CACHELINE_SIZE to 64 for i.MX6UL. Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* imx: mx6ul: Update imx registers head filePeng Fan2015-08-021-25/+35
| | | | | | | | | | | | 1. Update imx register base address for i.MX6UL. 2. Remove duplicated MXS_APBH/GPMI/BCH_BASE. 3. Remove #ifdef for register addresses that equal to "AIPS2_OFF_BASE_ADDR + 0x34000" for different chips. 4. According fuse map, complete fuse_bank4_regs. 5. Move AIPS3_ARB_BASE_ADDR and AIPS3_ARB_END_ADDR out of #ifdef CONFIG_MX6SX, because we can use runtime check Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* imx: mx6ul: Add pins IOMUX head filePeng Fan2015-08-022-0/+1067
| | | | | | | Add i.MX6UL pins IOMUX file which defines the IOMUX settings for choose. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* imx: mx6ul: Add i.MX6UL CPU typePeng Fan2015-08-022-1/+4
| | | | | | | | | | Add MXC_CPU_MX6UL for i.MX6UL CPU type which is got at runtime from DIGPROG register. But the value has been occupied by MXC_CPU_MX6D which is not real id from DIGPROG register, so change i.MX6D to value 0x67 which was not occupied. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com>
* sf: kconfig: add kconfig options for spi flashesNikita Kiryanov2015-08-023-8/+52
| | | | | | | | | | Add kconfig options for various SPI flashes and use them in cm-fx6 defconfig. Cc: Jagan Teki <jteki@openedev.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
* usb: kconfig: create a menu for usbNikita Kiryanov2015-08-021-0/+2
| | | | | | | | | | With recent additions to USB Kconfig the number of USB options had grown large enough to warrant a separate menu for USB. Add a Kconfig menu for USB. Cc: Marek Vasut <marex@denx.de> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* usb: kconfig: usb keyboard kconfigNikita Kiryanov2015-08-023-2/+29
| | | | | | | | | | Add Kconfig options for USB keyboard and use them for cm-fx6. Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
* arm: mx6: usb: kconfig: add USB_EHCI_MX6 kconfig optionNikita Kiryanov2015-08-023-3/+11
| | | | | | | | | | | | Add USB_EHCI_MX6 option to menuconfig and use it when migrating cm-fx6 usb config to defconfig. Cc: Masahiro Yamada <yamada.masahiro@socionext.com> Cc: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
* arm: mx6: kconfig: don't select CPU_V7 per boardNikita Kiryanov2015-08-021-3/+0
| | | | | | | | | | CPU_V7 is already selected by ARCH_MX6, so no point in selecting it again by boards that depend on ARCH_MX6. Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
* arm: mx6: cm-fx6: move cm-fx6 target under ARCH_MX6Nikita Kiryanov2015-08-023-8/+9
| | | | | | | | | | cm-fx6 is an MX6 based board, and the menuconfig hierarchy should reflect that. Make TARGET_CM_FX6 dependant on ARCH_MX6. Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
* arm: mx6: cm-fx6: move CMD configs to defconfigNikita Kiryanov2015-08-022-3/+5
| | | | | | | | | | Move CONFIG_CMD_* options that can be selected in menuconfig to cm-fx6 defconfig. Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
* arm: mx6: cm-fx6: setup hdmi only on hdmi enableNikita Kiryanov2015-08-021-6/+3
| | | | | | | | | Refactor display code to only setup hdmi if do_enable_hdmi() is invoked. Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
* arm: mx6: cm-fx6: add support for displaytype env varNikita Kiryanov2015-08-021-1/+4
| | | | | | | | | | | | | Add support for selecting display preset using the environment variable "displaytype". This is a preparation for future merging of compulab omap3_display.c display selection code with the cm-fx6 display selection code. The "panel" environment variable is retained for backwards compatibility. Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
* arm: mx6: cm-fx6: make it possible to not init displayNikita Kiryanov2015-08-022-25/+48
| | | | | | | | | | | | | | | | | Implement a cm-fx6 specific board_video_skip() to provide the option to not initialize the display. The new function does not init display if the environment variable "panel" is not defined, or if it is set to an unsupported value. Collateral changes: - Don't use the global displays array (it's CONFIG_IMX_VIDEO_SKIP specific). - Don't use detect_hdmi(), since env controlled init makes it unnecessary. Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
* arm: mx6: cm-fx6: map HDMI to IPU1 DI0 explicitlyNikita Kiryanov2015-08-021-0/+2
| | | | | | | | | | | | | | | U-Boot does not explicitly assign the display to an IPU interface. Instead, it relies on the power-on default of DI0. Since the kernel reassigns HDMI display to DI1, after a warm reset the HDMI display no longer works in U-Boot. Fix this by explicitly assigning HDMI to IPU1 DI0 in U-Boot. Cc: Stefano Babic <sbabic@denx.de> Cc: Igor Grinberg <grinberg@compulab.co.il> Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Acked-by: Igor Grinberg <grinberg@compulab.co.il>
* imx: mx6qpsabreauto: Add MX6QP SABREAUTO CPU3 board supportPeng Fan2015-08-024-7/+177
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Add DDR script for mx6qpsabreauto board. 2. On CPU3 board, enet RGMII tx clock is from internal PLL. Set the GPR5[9] and init the enet pll output to 125Mhz. 3. On CPU3 board, SW1ABC=VDDSOC_IN, SW2=VDDARM_IN. Build target: mx6qpsabreauto_config Boot Log: U-Boot 2015.07-rc2-00071-gfd985ff (Jun 29 2015 - 22:10:55 +0800) CPU: Freescale i.MX6QP rev1.0 996 MHz (running at 792 MHz) CPU: Automotive temperature grade (-40C to 125C) at 34C Reset cause: POR Board: MX6Q-Sabreauto revA I2C: ready DRAM: 2 GiB PMIC: PFUZE100 ID=0x10 Flash: 32 MiB NAND: 0 MiB MMC: FSL_SDHC: 0 *** Warning - bad CRC, using default environment No panel detected: default to HDMI Display: HDMI (1024x768) In: serial Out: serial Err: serial Net: FEC [PRIME] Hit any key to stop autoboot: 0 Note: In this patch, we still add a new config mx6qpsabreauto_config, since SPL is not supported now, and IMX_CONFIG is needed at build time, so add this config. Future, when SPL is converted, this config can be removed. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Robin Gong <b38343@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
* imx: mx6sabresd/sabreauto runtime setting fdt_filePeng Fan2015-08-025-12/+38
| | | | | | | | | | | | | Detect the SOC and board variant at runtime and change the dtb name, but not hardcoding the fdt_file env variable. Take the following patch as a reference. Íd58699b157df75f1aa0b363ea9c21add21a0c "mx6cuboxi: Load the correct 'fdtfile' variable" Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* imx: mx6qp Enable PRG clock for IPUPeng Fan2015-08-021-0/+5
| | | | | | | | | | The i.MX6DQP has a PRG module, need to enable its clock for using IPU. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Brown Oliver <B37094@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* imx: mx6: hab : Remove the cache issue workaroud in hab for i.MX6QPYe.Li2015-08-021-1/+2
| | | | | | | | | Since the i.MX6QP has fixed the issue in boot ROM, so remove the workaround for i.MX6QP. Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* imx: mx6: ccm: Change the clock settings for i.MX6QPPeng Fan2015-08-023-34/+49
| | | | | | | | | | | | Since i.MX6QP changes some CCM registers, so modify the clocks settings to follow the hardware changes. In c files, use runtime check and discard #ifdef. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* imx: add cpu type for i.MX6QP/DPPeng Fan2015-08-024-5/+16
| | | | | | | | | | | Add cpu type for i.MX6QP/DP. This patch also fix is_mx6dqp(), since get_cpu_rev can return MXC_CPU_MX6QP and MXC_CPU_MX6DP, we should use: (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP)). Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Acked-by: Stefano Babic <sbabic@denx.de>
* cgtqmx6eval: Use standard boot scriptOtavio Salvador2015-07-261-28/+66
| | | | | | | Use more standard boot scripts and also add the capability of booting via NFS. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* cgtqmx6eval: Align DCD settings with Congatec's U-bootOtavio Salvador2015-07-261-77/+51
| | | | | | | Use the same DCD settings from Congatec's U-boot tree for the P/N 016113 card. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* cgtqmx6eval: Add SATA supportOtavio Salvador2015-07-262-0/+14
| | | | | | Add SATA support. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* cgtqmx6eval: Add splash screen supportOtavio Salvador2015-07-262-0/+193
| | | | | | Add LVDS and HDMI support. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* cgtqmx6eval: Add USB supportOtavio Salvador2015-07-262-0/+59
| | | | | | Add USB support. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* cgtqmx6eval: Add PMIC supportOtavio Salvador2015-07-262-0/+98
| | | | | | | | cgtqmx6eval has a PFUZE100 FSL PMIC connected to I2C2. Add support for it. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* cgtqmx6eval: Add thermal supportOtavio Salvador2015-07-262-0/+11
| | | | | | | | Add thermal support so that we can see the following message on boot: CPU: Industrial temperature grade (-40C to 105C) at 33C Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* cgtqmx6eval: Add ESDHC3 supportOtavio Salvador2015-07-261-1/+21
| | | | | | | | cgtqmx6eval has an eMMC connected to ESDHC3. Add support for it. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* cgtqmx6eval: Fit into single linesOtavio Salvador2015-07-261-4/+2
| | | | | | There is no need to use multiple lines when they fit into a single line. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* cgtqmx6eval: Improve the error handlingOtavio Salvador2015-07-261-3/+7
| | | | | | | | Perfoming an OR operation on the error is not a good approach. Return the error immediately for each ESDHC instance instead. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* cgtqmx6eval: Staticize when possibleOtavio Salvador2015-07-261-4/+4
| | | | | | Declare 'static' when possible. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* cgtqmx6eval: Use the default CONFIG_SYS_PBSIZEOtavio Salvador2015-07-261-3/+0
| | | | | | | | | | | | | Entering the maximum number of characters defined by CONFIG_SYS_CBSIZE into the console and hitting enter afterwards, causes a hang in the system because CONFIG_SYS_PBSIZE is not capable of storing the extra characters of the error message: "Unknown command '' - try 'help'". Use the default CONFIG_SYS_PBSIZE definition from config_fallbacks.h to solve this problem. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* cgtqmx6eval: Use default promptOtavio Salvador2015-07-261-3/+0
| | | | | | Remove the custom prompt and use the default instead. Signed-off-by: Otavio Salvador <otavio@ossystems.com.br>
* mmc:fsl_esdhc invalidate dcache before readPeng Fan2015-07-261-0/+8
| | | | | | | | | | | | | | | | | | | | | DCIMVAC is upgraded to DCCIMVAC for the individual processor (Cortex-A7) that the DCIMVAC is executed on. We should follow the linux dma follow. Before DMA read, first invalidate dcache then after DMA read, invalidate dcache again. With the DMA direction DMA_FROM_DEVICE, the dcache need be invalidated again after the DMA completion. The reason is that we need explicity make sure the dcache been invalidated thus to get the DMA'ed memory correctly from the physical memory. Any cache-line fill during the DMA operations such as the pre-fetching can cause the DMA coherency issue, thus CPU get the stale data. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Signed-off-by: Ye.Li <B37916@freescale.com> Signed-off-by: Nitin Garg <nitin.garg@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com> Reviewed-by: Stefano Babic <sbabic@denx.de>
* mx6sxsabresd: Use 'int' for return valuesFabio Estevam2015-07-261-1/+2
| | | | | | | | | | The variable 'ret' is used to store the value returned by pfuze_mode_init(), so it should be of type 'int' instead of 'unsigned int' in order to correctly handle negative numbers. Fix the variable type. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* mx6sabresd: Use 'int' for return valuesFabio Estevam2015-07-261-1/+2
| | | | | | | | | | The variable 'ret' is used to store the value returned by pfuze_mode_init(), so it should of type 'int' instead of 'unsigned int' in order to correctly handle negative numbers. Fix the variable type. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* warp: Add MAX77696 supportFabio Estevam2015-07-262-0/+61
| | | | | | | | Warp has a MAX77696 PMIC connected via I2C1 bus. Add support for it. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* power: pmic: Add support for MAX77696 PMICFabio Estevam2015-07-263-0/+93
| | | | | | Add support for MAX77696 PMIC. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
* thermal: Fix commentsFabio Estevam2015-07-261-12/+4
| | | | | | | | | | It seems that many comments were copied from the I2C uclass, so adjust the comments for the thermal class. Reported-by: Simon Glass <sjg@chromium.org> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Otavio Salvador <otavio@ossystems.com.br> Acked-by: Simon Glass <sjg@chromium.org>
* imx: imximage: add new CHECK/CLR BIT commandAdrian Alonso2015-07-262-27/+93
| | | | | | | | | | | | | | | * Extend imximage DCD version 2 to support DCD commands CMD_WRITE_CLR_BIT 4 [address] [mask bit] means: while ((*address & ~mask) != 0); CMD_CHECK_BITS_SET 4 [address] [mask bit] means: while ((*address & mask) != mask); CMD_CHECK_BITS_CLR 4 [address] [mask bit] means: *address = *address & ~mask; * Add set_dcd_param_v2 helper function to set DCD command parameters Signed-off-by: Adrian Alonso <aalonso@freescale.com> Signed-off-by: Peng Fan <Peng.Fan@freescale.com>
* arm: mx6: tqma6: Add WRU-IV baseboard for the TQMa6 SoMStefan Roese2015-07-266-0/+437
| | | | | | | | | This patch adds support for the "OHB System AG" baseboard with is equipped with the TQMa6S SoM. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Markus Niebel <Markus.Niebel@tq-group.com> Cc: Stefano Babic <sbabic@denx.de>
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