summaryrefslogtreecommitdiffstats
Commit message (Collapse)AuthorAgeFilesLines
...
| * | power: axp221: Remove switch case to simplify axp_set_eldoChen-Yu Tsai2016-05-251-20/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ELDO enable bits and registers are contiguous for axp221. Instead of a switch case testing against the index, just use the index to shift the bit or register offset. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Disable VIDEO for SoCs without display supportChen-Yu Tsai2016-05-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The newer chips use a newer display pipeline, which is not supported. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Add default MMC0 card detect pin for A83T, H3 and A64 SoCsChen-Yu Tsai2016-05-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | A83T, H3, and A64 have a dedicated pin for card detect on the PF pingroup. This is used in all designs. Set it as the default. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: Sort SoC variants by family (sunXi) first, chip name secondChen-Yu Tsai2016-05-251-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | In most other places, we sort SoC descriptions by family (sunXi) first, then by the chip name (A20). Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
| * | sunxi: make SoC variant choice mandatoryChen-Yu Tsai2016-05-251-1/+0
| |/ | | | | | | | | | | | | | | | | The user should always select an SoC variant to support. Not choosing one doesn't make sense for a bootloader. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Hans de Goede <hdegoede@redhat.com> Signed-off-by: Hans de Goede <hdegoede@redhat.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-uniphierTom Rini2016-05-2534-22/+426
|\ \
| * | ARM: uniphier: add EHCI nodes for PH1-LD11Masahiro Yamada2016-05-262-0/+48
| | | | | | | | | | | | | | | | | | Make the USB feature really available. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | clk: uniphier: add Media I/O clock driver support for PH1-LD11Masahiro Yamada2016-05-261-0/+4
| | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: add PH1-LD11 SoC supportMasahiro Yamada2016-05-2624-4/+354
| | | | | | | | | | | | | | | | | | This is a low-cost ARMv8 SoC from Socionext Inc. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: rename UMC register macros of PH1-LD20Masahiro Yamada2016-05-262-4/+4
| | | | | | | | | | | | | | | | | | Correct some register names. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: rename umc-ld20-regs.h to umc64-regs.hMasahiro Yamada2016-05-262-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This header will be shared between PH1-LD11 and PH1-LD20 (and hopefully new ARMv8 SoCs developed in the future), so umc64-regs.h would be a better fit. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: clean up boot mode tablesMasahiro Yamada2016-05-265-13/+13
| | | | | | | | | | | | | | | | | | Tidy up alignment of open parentheses. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | ARM: uniphier: disable cache in SPL of PH1-LD20Masahiro Yamada2016-05-261-0/+2
| |/ | | | | | | | | | | | | | | The Boot ROM has enabled D-cache and MMU setting DDR memory area as Normal Memory in its page table. Disable D-cache and MMU before jumping to U-Boot proper. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2016-05-257-3/+39
|\ \ | |/ |/|
| * powerpc:t4240: MAC9 and MAC10 should not be identified as 1G interface in ↵Ying Zhang2016-05-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | some case When using rcw protocols to support 10G on MAC9 and MAC10, these MACs should not be identified as 1G interface, otherwise, one MAC will be listed as two Ethernet ports. For example, MAC9 will be listed as FM1@TGEC1 and FM1@DTSEC9. Signed-off-by: Ying Zhang <b40530@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * powerpc:t4240rdb: Disable the non-existent ethernet ports on T4240RDBYing Zhang2016-05-241-0/+5
| | | | | | | | | | | | | | | | | | Disable the non-existent ethernet ports on T4240RDB:FM1_DTSEC5, FM1_DTSEC6, FM2_DTSEC5 and FM2_DTSEC6. Signed-off-by: Ying Zhang <ying.zhang22455@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * powerpc/mpc85xx: set L2PE in L2CSR0 before enabling L2 cacheAneesh Bansal2016-05-241-0/+23
| | | | | | | | | | | | | | | | | | | | While enabling L2 cache, the value of L2PE (L2 cache parity/ECC error checking enable) must not be changed while the L2 cache is enabled. So, L2PE must be set before enabling L2 cache. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * powerpc/t2080qds: Enable qixis commands to reboot from NAND and SDYork Sun2016-05-191-0/+4
| | | | | | | | | | Signed-off-by: York Sun <york.sun@nxp.com> CC: Shengzhou Liu <Shengzhou.Liu@nxp.com>
| * powerpc/t208xrdb: Update MAINTAINERS fileYork Sun2016-05-191-1/+1
| | | | | | | | | | Signed-off-by: York Sun <york.sun@nxp.com> CC: Shengzhou Liu <Shengzhou.Liu@nxp.com>
| * powerpc/t208xqds: Update MAINTAINERS fileYork Sun2016-05-191-1/+1
| | | | | | | | | | Signed-off-by: York Sun <york.sun@nxp.com> CC: Shengzhou Liu <Shengzhou.Liu@nxp.com>
| * powerpc: Disable flush or invalidate dcache by range for some SoCsYork Sun2016-05-191-0/+4
| | | | | | | | | | | | | | | | | | | | | | Commit ac337168a unified functions to flush and invalidate dcache by range. These two functions were no-op for SoCs other than 4xx and MPC86xx. Adding these functions seemed to be correct but introduced issues when the dcache is flushed. While the root cause is under investigation, disable these functions for affected SoCs so various drivers can work. Signed-off-by: York Sun <york.sun@nxp.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-05-2455-218/+631
|\ \
| * | armv8: ls1043ardb: enable scsi command and pcie to sata converterPo Liu2016-05-181-0/+21
| | | | | | | | | | | | | | | | | | | | | Enable scsi command and pcie to sata chip 88SE9170. Signed-off-by: Po Liu <po.liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | driver/ddr/fsl: Add workaround for erratum A-010165Shengzhou Liu2016-05-182-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | During DDR-2133 operation, the transmit data eye margins determined during the memory controller initialization may be sub-optimal, set DEBUG_29[12] and DEBUG_29[13:16] = 4'b0100 before MEM_EN is set. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | arm: ls1021a: Enable CONFIG_OF_LIBFDT and CONFIG_FIT in defconfigAlison Wang2016-05-1815-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | In defconfig, enable CONFIG_OF_LIBFDT to support booting DT linux kernel and enable COFNIG_FIT to support FIT image. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls1043ardb: invert irq pin polarity for AQR105 PHYShaohui Xie2016-05-182-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | To use AQR105 PHY's interrupt, we need to invert the IRQ pin polarity by setting relative bit in SCFG_INTPCR register, because AQR105 interrupt is low active but GIC accepts high active. Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | crypto/fsl: add support for multiple SEC engines initializationAlex Porosanu2016-05-184-117/+172
| | | | | | | | | | | | | | | | | | | | | | | | | | | For SoCs that contain multiple SEC engines, each of them needs to be initialized (by means of initializing among others the random number generator). Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | arch/arm, arch/powerpc: add # of SEC engines on the SOCAlex Porosanu2016-05-184-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some SOCs, specifically the ones in the C29x familiy can have multiple security engines. This patch adds a system configuration define which indicates the maximum number of SEC engines that can be found on a SoC. Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | arch/arm: add SEC JR0 offsetAlex Porosanu2016-05-185-10/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale PPC SoCs do not hard-code security engine's Job Ring 0 address, rather a define is used. This patch adds the same functionality to the ARM based SoCs (i.e. LS1/LS2 and i.MX parts) Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv7: ls102xa: spl: fix the macro name of MMC modeQianyu Gong2016-05-181-1/+1
| | | | | | | | | | | | | | | | | | | | | MMCSD_MODE_FAT has been renamed to MMCSD_MODE_FS by commit 205b4f33. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-layerscape: spl: fix the macro name of MMC modeQianyu Gong2016-05-181-1/+1
| | | | | | | | | | | | | | | | | | | | | MMCSD_MODE_FAT has be renmaed to MMCSD_MODE_FS by commit 205b4f33. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-layerscape: spl: remove duplicate init_early_memctl_regs()Qianyu Gong2016-05-181-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | init_early_memctl_regs() is also be called in board_early_init_f(). So remove the duplicated call in spl code. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls1043ardb: fix types of variablesQianyu Gong2016-05-181-3/+3
| | | | | | | | | | | | | | | | | | | | | Using u16 for cfg_rcw_src and u8 for sd1refclk_sel is enough. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls1043a: remove redundant code in board filesQianyu Gong2016-05-182-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | gd->env_addr will be initialized in env_init() in common/env_nowhere.c if CONFIG_ENV_IS_NOWHERE is defined. So no need to do it again. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls1043a: copy kernel from QSPI when booting with QSPI enabledQianyu Gong2016-05-181-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | IFC won't be initialized in U-Boot if QSPI is enabled on LS1043AQDS. So this patch could fix 'sync abort' caused by autoboot that tries to access IFC address. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8/ls1043ardb: fix the limitation of using 'cpld reset'Qianyu Gong2016-05-182-2/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current 'cpld reset' will just write global_rst register but couldn't switch to NOR boot if the board's switches are for NAND/SD boot. So need to write rcw source registers for NOR boot as well. Signed-off-by: Gong Qianyu <Qianyu.Gong@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | arm: uniform usage of u32 in ls102x caam configVincent Siles2016-05-181-1/+1
| | | | | | | | | | | | | | | | | | | | | Mix usage of uint32_t and u32 fixed in favor of u32. Signed-off-by: Vincent Siles <vincent.siles@provenrun.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | arm: Fix SCFG ICID reg addressesVincent Siles2016-05-181-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the LS102x boards, in order to initialize the ICID values of masters, the dev_stream_id array holds absolute offsets from the base of SCFG. In ls102xa_config_ssmu_stream_id, the base pointer is cast to uint32_t * before adding the offset, leading to an invalid address. Casting it to void * solves the issue. Signed-off-by: Vincent Siles <vincent.siles@provenrun.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: fsl-layerscape: Remove unnecessary flushing dcacheAlison Wang2016-05-181-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | As the issue about the stack will get corrupted when switching between the early and final mmu tables is fixed by commit 70e21b064, the workaround to flush dcache is unnecessary and should be removed. Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls2080a: update eth primePrabhakar Kushwaha2016-05-182-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | As per new PHY framework, DPNI naming convetion is no more used. Use new naming convention. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls2080: enable sec_init in U-BootAneesh Bansal2016-05-181-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | Define CONFIG_FSL_CAAM for LS2080 which would enable call to sec_init() during U-Boot. Signed-off-by: Aneesh Bansal <aneesh.bansal@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8/ls1043a: update the node for QSPI supportYuan Yao2016-05-181-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | The address value and size value set for QSPI dts node "reg" property have type of u64 on arm64. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | sf: Disable 4-KB erase command for SPANSION S25FS-S familyYuan Yao2016-05-181-0/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The S25FS-S family physical sectors may be configured as a hybrid combination of eight 4-kB parameter sectors at the top or bottom of the address space with all but one of the remaining sectors being uniform size. The default status of the flash is in this hybrid architecture. The parameter sectors and the uniform sectors have different erase commands. This patch disable the hybrid sector architecture then the flash will has uniform sector size and uniform erase command. This configuration is temporary, the flash will revert to hybrid architecture after power on reset. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | spi: fsl_qspi: Enable Spansion S25FS-S family flashesYuan Yao2016-05-182-6/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The flash type of LS2085AQDS QSPI is S25FS256S. It has special write any device register command and read any device register command. This patch enable support for those commands. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | spi: fsl_qspi: Assign AMBA mem according CS num in dtsYuan Yao2016-05-181-12/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | QSPI controller automatic enable the chipselect signal according the dest AMBA memory address. Now we distribute the AMBA memory zone averagely to every chipselect slave device according chipselect numbers got from dts node. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | spi: fsl_qspi: Fix issues on arm64Yuan Yao2016-05-181-19/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The address value and size value get from dts "reg" property have type of u64 on arm64. If we assign those values to "u32" variables, driver can't work correctly. Converting the type of those variables to fdt_xxx_t. Signed-off-by: Yuan Yao <yao.yuan@nxp.com> Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8/fdt: add fixup_crypto_nodeAlex Porosanu2016-05-171-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | For Qoriq PPC&ARM v7 platforms, the crypto node is being fixup'ed in order to update the SEC internal version (aka SEC ERA). This patch adds the same functionality to the ARMv8 SoCs. Signed-off-by: Alex Porosanu <alexandru.porosanu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8: ls2080a: Update MAINTAINERS filePrabhakar Kushwaha2016-05-172-2/+2
| | | | | | | | | | | | | | | | | | | | | Update MAINTAINERS file for ls2080aqds and ls2080ardb platforms. Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | armv8/ls2080ardb: Update DDR timing to support more UDIMMsShengzhou Liu2016-05-171-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Optimize DDR timing for good margins to support new Transcend and Apacer DDR4 UDIMM besides current Micron UDIMM. Verified 1333MT/s, 1600MT/s, 1866MT/s, 2133MT/s rate with following UDIMM on LS2080ARDB. - Micron UDIMM: MTA18ASF1G72AZ-2G1A1Z - Apacer UDIMM: 78.C1GM4.AF10B - Transcend UDIMM: TS1GLH72V1H Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
| * | driver/ddr/fsl: Add workaround for erratum A-009801Shengzhou Liu2016-05-173-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | The initial training for the DDRC may provide results that are not optimized. The workaround provides better read timing margins. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
OpenPOWER on IntegriCloud