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* exynos: Enable pre-relocation malloc()Simon Glass2014-10-084-6/+10
| | | | | | | Enable this feature to support driver model before relocation. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* samsung: Enable device tree for smdkc100Simon Glass2014-10-086-4/+39
| | | | | | | Change this board to add a device tree. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* samsung: Enable device tree for s5p_goniSimon Glass2014-10-089-7/+170
| | | | | | | | | Change this board to add a device tree. This also adds a pinmux header file although it is not used as yet. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* config: Move smdkv310 to use common exynos4 fileSimon Glass2014-10-085-51/+34
| | | | | | | | | Most of the smdkv310 features are common with other exynos4 boards. To permit easier addition of driver model support, use the common file and add a device tree file. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* config: Move arndale to use common exynos5250 fileSimon Glass2014-10-0810-212/+66
| | | | | | | | Most of the arndale features are common with other exynos5250 boards. To permit easier addition of driver model support, use the common file. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* exynos: config: Move cros_ec and tps65090 out of smdk boardsSimon Glass2014-10-085-18/+43
| | | | | | | | | These boards do not in fact have a Chrome OS EC, nor a TPS565090 PMIC, so move the settings into a separate common file to be used by those that need it. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* exynos: Move common smdk5420 things to common fileSimon Glass2014-10-083-11/+5
| | | | | | | | A few things are common but are not in the common file. Fix this and rename the file to fit with the other exynos*-common files. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* exynos: Move common exynos settings into a common fileSimon Glass2014-10-089-171/+105
| | | | | | | | | | | | | Since exynos4 and exyno5 share many settings, we should move these into a common file to avoid duplication. In effect the changes are that all exynos boards now have EXT4 and FAT write support. This affects exynos5250 and exynos5420 which previously did not. This also disables the ext2 commands which are equivalent to ext4 anyway. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* exynos: Rename -dt config files to -commonSimon Glass2014-10-0812-16/+16
| | | | | | | | | | We want exynos5250-dt.h to be a board which can support any exynos5250 device. This matches the naming used by Linux. As a first step, rename the existing -dt files to -common to make it clear they are common files, and not specific boards. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* exynos: dts: Add device tree node for cros_ec keyboardSimon Glass2014-10-081-0/+55
| | | | | | | Add a keyboard definition so that the keyboard can be used on pit. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* dm: exynos: Split out the cros_ec driversSimon Glass2014-10-083-2/+3
| | | | | | | | | | | | | With the driver model conversion we are going to be using driver model for SPI and not for I2C. This works OK so long as a board doesn't need both dm and non-dm versions of the cros_ec driver. Since pit uses SPI and snow uses I2C we need to split the configs so that only one driver is compiled for each platform. We can fix this later when driver model supports I2C. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* cros_ec: exynos: Use the correct tps65090 driver in each caseSimon Glass2014-10-083-1/+4
| | | | | | | | | | Exynos 5250 boards (snow, spring) use the I2C driver but Exynos 5420 boards cannot due to a hardware design decision. Select the correct driver to use in each case. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* cros_ec: power: Add a tunnelled version of the tps65090 driverSimon Glass2014-10-082-0/+219
| | | | | | | | | | | | | Unfortunately on Pit the AP has no direct access to the tps65090 but must talk through the EC (over SPI) to the EC's I2C bus. When driver model supports PMICs this will be relatively easy. In the meantime the best approach is to duplicate the driver. It will be refactored once driver model support is expanded. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* exynos5: Enable data cacheSimon Glass2014-10-081-1/+1
| | | | | | | | | Things run faster when the data cache is enabled, so turn it on along with the 'dcache' command. Signed-off-by: Simon Glass <sjg@chromium.org> Tested-by: Ajay Kumar <ajaykumar.rs@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Exynos: Use 900MHz ARM frequency in SPL for peach_pitSimon Glass2014-10-081-1/+1
| | | | | | | | | The device seems to hang in SPL if the full speed is used when booting from USB, perhaps because the PMIC has not been set to the maximum ARM core voltage yet. Slow it down to a reliable speed. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* Merge branch 'uboot'Minkyu Kang2014-10-07637-2031/+11739
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| * git-mailrc: add me as a maintainer of UniPhier platformMasahiro Yamada2014-10-051-0/+1
| | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * MAINTAINERS: add me as a maintainer of UniPhier platformMasahiro Yamada2014-10-051-0/+9
| | | | | | | | | | | | Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Acked-by: Albert ARIBAUD <albert.u.boot@aribaud.net> Acked-by: Michal Simek <monstr@monstr.eu>
| * ARM: UniPhier: add Kconfig and defconfigMasahiro Yamada2014-10-055-0/+61
| | | | | | | | | | | | | | This commit allows to build Panasonic UniPhier family: PH1-LD4, PH1-Pro4, PH1-sLD8 Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * ARM: UniPhier: add UniPhier SoC support codeMasahiro Yamada2014-10-0563-0/+4951
| | | | | | | | | | | | These are used by Panasonic UniPhier SoC family. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * serial: add UniPhier serial driverMasahiro Yamada2014-10-053-0/+207
| | | | | | | | | | | | The driver for on-chip UART used on Panasonic UniPhier platform. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
| * mtd: denali: add Denali NAND driver for SPLMasahiro Yamada2014-10-053-0/+242
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The SPL-mode driver for Denali(Cadence) NAND Flash Memory Controller IP. This driver requires two CONFIG macros: - CONFIG_SPL_NAND_DENALI Define to enable this driver. - CONFIG_SYS_NAND_BAD_BLOCK_POS Specify bad block mark position in the oob space. Typically 0. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Chin Liang See <clsee@altera.com> Cc: Scott Wood <scottwood@freescale.com>
| * mtd: denali: add Denali controller configs to KconfigMasahiro Yamada2014-10-053-6/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit 3eb3e72a3f66 (nand/denali: Adding Denali NAND driver support) introduced some new options, and some of them were documented by commit f9860cf081ef (nand/denali: Document CONFIG symbols). This commit allows users to enable/disable them via Kconfig with more detailed help docs. Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com> Cc: Chin Liang See <clsee@altera.com> Cc: Scott Wood <scottwood@freescale.com>
| * Merge branch 'for-tom' of git://git.denx.de/u-boot-dmTom Rini2014-09-264-110/+89
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| | * spi: Add brackets and tidy defines in spi.hSimon Glass2014-09-261-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | Some of the #defines in spi.h are not bracketed. To avoid future mistakes add brackets. Also add an explanatory comment for SPI_CONN_DUAL_... Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * dm: spi: Move cmd device code into its own functionSimon Glass2014-09-261-21/+32
| | | | | | | | | | | | | | | | | | | | | | | | In preparation for changing the error handling in this code for driver model, move it into its own function. Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com> Signed-off-by: Simon Glass <sjg@chromium.org>
| | * sandbox: config: Enable all SPI flash chipsSimon Glass2014-09-261-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Sandbox may as well support everything. This increases the amount of code that is built/tested by sandbox, and also provides access to all the supported SPI flash devices. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| | * sandbox: Convert SPI flash emulation to use sf_paramsSimon Glass2014-09-261-76/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present sandbox has its own table of supported SPI flash chips. Now that the SPI flash system is fully consolidated and has its own list, sandbox should use that. This enables us to expand the number of chips that sandbox supports. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2014-09-2639-251/+1018
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| | * | board/ls1021aqds: Add DDR4 supportYork Sun2014-09-256-2/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS1021AQDS has a variant with DDR4 slot. This patch adds a new defconfig for this variant to enable DDR4 support. RAW timing parameters are not added for DDR4. The board timing parameters are only tuned for single- rank 1600 and 1800MT/s with Micron DIMM 9ASF51272AZ-2G1A1 due to DIMM availability. Signed-off-by: York Sun <yorksun@freescale.com> CC: Alison Wang <alison.wang@freescale.com>
| | * | driver/ddr/fsl: Fix DDR4 driverYork Sun2014-09-252-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When accumulated ECC is enabled, the DQ_MAP for ECC[4:7] needs to be set to 0, i.e. 0->0, 1->1, etc., required by controller logic, even these pins are not actually connected. Also fix a bug when reading from DDR register to use proper accessor for correct endianess. Signed-off-by: York Sun <yorksun@freescale.com>
| | * | ARMv8/ls2085a: Move u-boot location to make room for RCWYork Sun2014-09-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | When booting with SP, RCW resides at the beginning of IFC NOR flash. Signed-off-by: York Sun <yorksun@freescale.com>
| | * | ARMv8/ls2085a: Enable secondary coresYork Sun2014-09-252-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Spin table is at the very beginning of boot code. Each core has an individual release address within the spin table, the ft_cpu_setup fn updates the "cpu-release-addr" property of each cpu node with the corresponding release address. Also fix CPU_RELEASE_ADDR to point to secondary_boot_func. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
| | * | armv8/fsl-lsch3: Release secondary cores from boot hold off with Boot PageYork Sun2014-09-2512-89/+518
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Secondary cores need to be released from holdoff by boot release registers. With GPP bootrom, they can boot from main memory directly. Individual spin table is used for each core. Spin table and the boot page is reserved in device tree so OS won't overwrite. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Arnab Basu <arnab.basu@freescale.com>
| | * | fdt_support: Make of_bus_default_count_cells non staticArnab Basu2014-09-252-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | of_bus_default_count_cells can be used to get the #address-cells and #size-cells defined by the current node's parent node. This is required when using of_read_number to read from FDT nodes that can be 32 or 64 bytes depending on values defined by the parent. Signed-off-by: Arnab Basu <arnab.basu@freescale.com> CC: Scott Wood <scottwood@freescale.com>
| | * | fdt_support: Move of_read_number to fdt_support.hArnab Basu2014-09-252-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is being done so that it can be used outside 'fdt_support.c'. Making life more convenient when reading device node properties that can be 32 or 64 bits long. Signed-off-by: Arnab Basu <arnab.basu@freescale.com> Cc: Scott Wood <scottwood@freescale.com>
| | * | driver/ddr/fsl: Fix tXP and tCKEYork Sun2014-09-254-14/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver was written using old DDR3 spec which only covers low speeds. The value would be suboptimal for higher speeds. Fix both timing according to latest DDR3 spec, remove tCKE as an config option. Signed-off-by: York Sun <yorksun@freescale.com>
| | * | ARMv8/ls2085a_emu: Enable DP-DDR as standalone memory blockYork Sun2014-09-256-5/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | DP-DDR is used for DPAA, separated from main memory pool for general use. It has 32-bit bus width and use a standard DDR4 DIMM (64-bit). Signed-off-by: York Sun <yorksun@freescale.com>
| | * | driver/ddr: Restruct driver to allow standalone memory spaceYork Sun2014-09-258-108/+238
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-boot has been initializing DDR for the main memory. The presumption is the memory stays as a big continuous block, either linear or interleaved. This change is to support putting some DDR controllers to separated space without counting into main memory. The standalone memory controller could use different number of DIMM slots. Signed-off-by: York Sun <yorksun@freescale.com>
| | * | board/ls2085a: Add support of NOR and NAND flash for simulatorPrabhakar Kushwaha2014-09-252-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support of NOR and NAND flash for simulator target. Here IFC - CS0: NOR flash IFC - CS1: NAND flash Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * | driver/mtd: Use generic timer API for FSL IFC, eLBCPrabhakar Kushwaha2014-09-252-15/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Freescale's flash control driver is using architecture specific timer API i.e. usec2ticks Replace usec2ticks with get_timer() (generic timer API) Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * | board/ls2085a: Update env_addr after NOR flash relocationPrabhakar Kushwaha2014-09-241-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LS2085a has 2 regions in system memory map. Region1 is default map from where system boots. Once u-boot is moved to DDR, IFC is re-mapped to Region2. So, update gd->env_addr to reflect correct address. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| * | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxTom Rini2014-09-2614-39/+82
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| | * | powerpc: add --bss-plt to LDFLAGSChris Packham2014-09-251-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With some versions of gcc (that we know of 4.6.3 and 4.8.2 are affected) it is necessary to specify --bss-plt to get the final blrl in the _GOT2_TABLE_. Without this the last symbol does not get it's address relocated. For the P2041RDB board this ended up being NetArpWaitTimerStart which caused the ARP packets to timeout immediately. Signed-off-by: Joakim Tjernlund <joakim.tjernlund@transmode.se> Signed-off-by: Chris Packham <judge.packham@gmail.com> Acked-by: Joakim Tjernlund <joakim.tjernlund@transmode.se> Acked-by: Scott Wood <scottwood@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * | board/t1040qds: Add sgmii ports support in 0xA7 protocolPriyanka Jain2014-09-242-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | T1042QDS (T1042 is T1040 Personality without L2 switch) supports following sgmii interfaces with serdes protocol 0xA7 -SGMII-MAC3 on Lane B - slot 7 -SGMII-MAC5 on Lane H - slot 7 -SGMII2.5G-MAC1 on Lane C - slot 6 -SGMII2.5G-MAC2 on Lane D - slot 5 Add support of above sgmii interfaces Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
| | * | powerpc/t104xrdb: Set DDR ODT to 75ohmPriyanka Jain2014-09-242-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DDR-ODT require cfg_dram_type switch set properly as per DDR type. T1040RDB, T1042RDB boards have DDR3L type DDR, so cfg_dram_type should be set to OFF for DDR3L Update t104xrdb/README for switch setting Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * | powerpc/mpc85xx: Serdes protocol "00" is supportedEbony Zhu2014-09-241-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "0x00" is a valid serdes protocol for QorIQ parts, and can not be used to test whether the serdes is enabled or disabled. Signed-off-by: Ebony Zhu <b45385@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * | B4860QDS: Enable mac command supportShaveta Leekha2014-09-241-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One of the I2C EEPROM is used to store/save and edit mac addresses of ports. this patch add required CONFIG to support the same Signed-off-by: Shaveta Leekha <shaveta@freescale.com>
| | * | powerpc/b4860: Updated default hwconfig to enable only cpc2Shaveta Leekha2014-09-241-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CPC1 is not being enabled by default as powerpc is supposed to use only CPC2. Though by editing hwconfig en_cpc option, CPC1 can also be enabled. Signed-off-by: Shaveta Leekha <shaveta@freescale.com> Signed-off-by: Sandeep Singh <Sandeep@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
| | * | powerpc/8xxx: Fix in USB device-tree fixupramneek mehresh2014-09-241-11/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix following issues in USB device-tree fixup: - returns when either dr_mode or phy_type not defined. This was terminating fix-up when only either property was defined in hwconfig string - updates dr_mode_type or dr_phy_type with junk value when their index is -1. Now these are updated only when their respective index is pointing to relevant types in modes[] and phys[] array - dr_mode_type and dr_phy_type were not NULL for each controller Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
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