diff options
Diffstat (limited to 'include/asm-sh')
32 files changed, 0 insertions, 4851 deletions
diff --git a/include/asm-sh/bitops.h b/include/asm-sh/bitops.h deleted file mode 100644 index c57d628478..0000000000 --- a/include/asm-sh/bitops.h +++ /dev/null @@ -1,153 +0,0 @@ -#ifndef __ASM_SH_BITOPS_H -#define __ASM_SH_BITOPS_H - -#ifdef __KERNEL__ -#include <asm/irqflags.h> -/* For __swab32 */ -#include <asm/byteorder.h> - -static inline void set_bit(int nr, volatile void * addr) -{ - int mask; - volatile unsigned int *a = addr; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - local_irq_save(flags); - *a |= mask; - local_irq_restore(flags); -} - -/* - * clear_bit() doesn't provide any barrier for the compiler. - */ -#define smp_mb__before_clear_bit() barrier() -#define smp_mb__after_clear_bit() barrier() -static inline void clear_bit(int nr, volatile void * addr) -{ - int mask; - volatile unsigned int *a = addr; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - local_irq_save(flags); - *a &= ~mask; - local_irq_restore(flags); -} - -static inline void change_bit(int nr, volatile void * addr) -{ - int mask; - volatile unsigned int *a = addr; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - local_irq_save(flags); - *a ^= mask; - local_irq_restore(flags); -} - -static inline int test_and_set_bit(int nr, volatile void * addr) -{ - int mask, retval; - volatile unsigned int *a = addr; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - local_irq_save(flags); - retval = (mask & *a) != 0; - *a |= mask; - local_irq_restore(flags); - - return retval; -} - -static inline int test_and_clear_bit(int nr, volatile void * addr) -{ - int mask, retval; - volatile unsigned int *a = addr; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - local_irq_save(flags); - retval = (mask & *a) != 0; - *a &= ~mask; - local_irq_restore(flags); - - return retval; -} - -static inline int test_and_change_bit(int nr, volatile void * addr) -{ - int mask, retval; - volatile unsigned int *a = addr; - unsigned long flags; - - a += nr >> 5; - mask = 1 << (nr & 0x1f); - local_irq_save(flags); - retval = (mask & *a) != 0; - *a ^= mask; - local_irq_restore(flags); - - return retval; -} - -static inline unsigned long ffz(unsigned long word) -{ - unsigned long result; - - __asm__("1:\n\t" - "shlr %1\n\t" - "bt/s 1b\n\t" - " add #1, %0" - : "=r" (result), "=r" (word) - : "0" (~0L), "1" (word) - : "t"); - return result; -} - -/** - * ffs - find first bit in word. - * @word: The word to search - * - * Undefined if no bit exists, so code should check against 0 first. - */ -static inline int ffs (int x) -{ - int r = 1; - - if (!x) - return 0; - if (!(x & 0xffff)) { - x >>= 16; - r += 16; - } - if (!(x & 0xff)) { - x >>= 8; - r += 8; - } - if (!(x & 0xf)) { - x >>= 4; - r += 4; - } - if (!(x & 3)) { - x >>= 2; - r += 2; - } - if (!(x & 1)) { - x >>= 1; - r += 1; - } - return r; -} -#define PLATFORM_FFS - -#endif /* __KERNEL__ */ - -#endif /* __ASM_SH_BITOPS_H */ diff --git a/include/asm-sh/byteorder.h b/include/asm-sh/byteorder.h deleted file mode 100644 index 25626a0760..0000000000 --- a/include/asm-sh/byteorder.h +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_SH_BYTEORDER_H_ -#define __ASM_SH_BYTEORDER_H_ - -#include <config.h> -#include <asm/types.h> - -#ifdef __LITTLE_ENDIAN__ -#include <linux/byteorder/little_endian.h> -#else -#include <linux/byteorder/big_endian.h> -#endif - -#endif diff --git a/include/asm-sh/cache.h b/include/asm-sh/cache.h deleted file mode 100644 index 2cfc0a7944..0000000000 --- a/include/asm-sh/cache.h +++ /dev/null @@ -1,35 +0,0 @@ -#ifndef __ASM_SH_CACHE_H -#define __ASM_SH_CACHE_H - -#if defined(CONFIG_SH4) || defined(CONFIG_SH4A) - -int cache_control(unsigned int cmd); - -#define L1_CACHE_BYTES 32 -struct __large_struct { unsigned long buf[100]; }; -#define __m(x) (*(struct __large_struct *)(x)) - -void dcache_wback_range(u32 start, u32 end) -{ - u32 v; - - start &= ~(L1_CACHE_BYTES - 1); - for (v = start; v < end; v += L1_CACHE_BYTES) { - asm volatile ("ocbwb %0" : /* no output */ - : "m" (__m(v))); - } -} - -void dcache_invalid_range(u32 start, u32 end) -{ - u32 v; - - start &= ~(L1_CACHE_BYTES - 1); - for (v = start; v < end; v += L1_CACHE_BYTES) { - asm volatile ("ocbi %0" : /* no output */ - : "m" (__m(v))); - } -} -#endif /* CONFIG_SH4 || CONFIG_SH4A */ - -#endif /* __ASM_SH_CACHE_H */ diff --git a/include/asm-sh/clk.h b/include/asm-sh/clk.h deleted file mode 100644 index 9cac6b09f9..0000000000 --- a/include/asm-sh/clk.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (C) 2009 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef __ASM_SH_CLK_H__ -#define __ASM_SH_CLK_H__ - -static inline unsigned long get_peripheral_clk_rate(void) -{ - return CONFIG_SYS_CLK_FREQ; -} - -static inline unsigned long get_tmu0_clk_rate(void) -{ - return CONFIG_SYS_CLK_FREQ; -} - -#endif /* __ASM_SH_CLK_H__ */ diff --git a/include/asm-sh/config.h b/include/asm-sh/config.h deleted file mode 100644 index 978cc92f40..0000000000 --- a/include/asm-sh/config.h +++ /dev/null @@ -1,27 +0,0 @@ -/* - * Copyright 2009 Freescale Semiconductor, Inc. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#ifndef _ASM_CONFIG_H_ -#define _ASM_CONFIG_H_ - -/* Relocation to SDRAM works on all sh boards */ -#define CONFIG_RELOC_FIXUP_WORKS - -#endif diff --git a/include/asm-sh/cpu_sh2.h b/include/asm-sh/cpu_sh2.h deleted file mode 100644 index 8bc9bc64c5..0000000000 --- a/include/asm-sh/cpu_sh2.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * Copyright (C) 2008 Renesas Solutions Corp. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ASM_CPU_SH2_H_ -#define _ASM_CPU_SH2_H_ - -/* cache control */ -#define CCR_CACHE_STOP 0x00000008 -#define CCR_CACHE_ENABLE 0x00000005 -#define CCR_CACHE_ICI 0x00000008 - -#define CACHE_OC_ADDRESS_ARRAY 0xf0000000 -#define CACHE_OC_WAY_SHIFT 13 -#define CACHE_OC_NUM_ENTRIES 256 -#define CACHE_OC_ENTRY_SHIFT 4 - -#if defined(CONFIG_CPU_SH7203) -# include <asm/cpu_sh7203.h> -#else -# error "Unknown SH2 variant" -#endif - -#endif /* _ASM_CPU_SH2_H_ */ diff --git a/include/asm-sh/cpu_sh3.h b/include/asm-sh/cpu_sh3.h deleted file mode 100644 index 6db38a2f84..0000000000 --- a/include/asm-sh/cpu_sh3.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * (C) Copyright 2007 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ASM_CPU_SH3_H_ -#define _ASM_CPU_SH3_H_ - -/* cache control */ -#define CCR_CACHE_STOP 0x00000008 -#define CCR_CACHE_ENABLE 0x00000005 -#define CCR_CACHE_ICI 0x00000008 - -#define CACHE_OC_ADDRESS_ARRAY 0xf0000000 -#define CACHE_OC_WAY_SHIFT 13 -#define CACHE_OC_NUM_ENTRIES 256 -#define CACHE_OC_ENTRY_SHIFT 4 - -#if defined(CONFIG_CPU_SH7710) -#include <asm/cpu_sh7710.h> -#elif defined(CONFIG_CPU_SH7720) -#include <asm/cpu_sh7720.h> -#else -#error "Unknown SH3 variant" -#endif - -#endif /* _ASM_CPU_SH3_H_ */ diff --git a/include/asm-sh/cpu_sh4.h b/include/asm-sh/cpu_sh4.h deleted file mode 100644 index fdcebd608e..0000000000 --- a/include/asm-sh/cpu_sh4.h +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ASM_CPU_SH4_H_ -#define _ASM_CPU_SH4_H_ - -/* cache control */ -#define CCR_CACHE_STOP 0x00000808 -#define CCR_CACHE_ENABLE 0x00000101 -#define CCR_CACHE_ICI 0x00000800 - -#define CACHE_OC_ADDRESS_ARRAY 0xf4000000 - -#if defined (CONFIG_CPU_SH7750) || \ - defined(CONFIG_CPU_SH7751) -#define CACHE_OC_WAY_SHIFT 14 -#define CACHE_OC_NUM_ENTRIES 512 -#else -#define CACHE_OC_WAY_SHIFT 13 -#define CACHE_OC_NUM_ENTRIES 256 -#endif -#define CACHE_OC_ENTRY_SHIFT 5 - -#if defined (CONFIG_CPU_SH7750) || \ - defined(CONFIG_CPU_SH7751) -# include <asm/cpu_sh7750.h> -#elif defined (CONFIG_CPU_SH7722) -# include <asm/cpu_sh7722.h> -#elif defined (CONFIG_CPU_SH7723) -# include <asm/cpu_sh7723.h> -#elif defined (CONFIG_CPU_SH7763) -# include <asm/cpu_sh7763.h> -#elif defined (CONFIG_CPU_SH7780) -# include <asm/cpu_sh7780.h> -#elif defined (CONFIG_CPU_SH7785) -# include <asm/cpu_sh7785.h> -#else -# error "Unknown SH4 variant" -#endif - -#if defined(CONFIG_SH_32BIT) -#define PMB_ADDR_ARRAY 0xf6100000 -#define PMB_ADDR_ENTRY 8 -#define PMB_VPN 24 - -#define PMB_DATA_ARRAY 0xf7100000 -#define PMB_DATA_ENTRY 8 -#define PMB_PPN 24 -#define PMB_UB 9 /* Buffered write */ -#define PMB_V 8 /* Valid */ -#define PMB_SZ1 7 /* Page size (upper bit) */ -#define PMB_SZ0 4 /* Page size (lower bit) */ -#define PMB_C 3 /* Cacheability */ -#define PMB_WT 0 /* Write-through */ - -#define PMB_ADDR_BASE(entry) (PMB_ADDR_ARRAY + (entry << PMB_ADDR_ENTRY)) -#define PMB_DATA_BASE(entry) (PMB_DATA_ARRAY + (entry << PMB_DATA_ENTRY)) -#define mk_pmb_addr_val(vpn) ((vpn << PMB_VPN)) -#define mk_pmb_data_val(ppn, ub, v, sz1, sz0, c, wt) \ - ((ppn << PMB_PPN) | (ub << PMB_UB) | \ - (v << PMB_V) | (sz1 << PMB_SZ1) | \ - (sz0 << PMB_SZ0) | (c << PMB_C) | \ - (wt << PMB_WT)) -#endif - -#endif /* _ASM_CPU_SH4_H_ */ diff --git a/include/asm-sh/cpu_sh7203.h b/include/asm-sh/cpu_sh7203.h deleted file mode 100644 index 77dcac43d3..0000000000 --- a/include/asm-sh/cpu_sh7203.h +++ /dev/null @@ -1,41 +0,0 @@ -#ifndef _ASM_CPU_SH7203_H_ -#define _ASM_CPU_SH7203_H_ - -/* Cache */ -#define CCR1 0xFFFC1000 -#define CCR CCR1 - -/* PFC */ -#define PACR 0xA4050100 -#define PBCR 0xA4050102 -#define PCCR 0xA4050104 -#define PETCR 0xA4050106 - -/* Port Data Registers */ -#define PADR 0xA4050120 -#define PBDR 0xA4050122 -#define PCDR 0xA4050124 - -/* BSC */ - -/* SDRAM controller */ - -/* SCIF */ -#define SCSMR_0 0xFFFE8000 -#define SCIF0_BASE SCSMR_0 - -/* Timer(CMT) */ -#define CMSTR 0xFFFEC000 -#define CMCSR_0 0xFFFEC002 -#define CMCNT_0 0xFFFEC004 -#define CMCOR_0 0xFFFEC006 -#define CMCSR_1 0xFFFEC008 -#define CMCNT_1 0xFFFEC00A -#define CMCOR_1 0xFFFEC00C - -/* On chip oscillator circuits */ -#define FRQCR 0xA415FF80 -#define WTCNT 0xA415FF84 -#define WTCSR 0xA415FF86 - -#endif /* _ASM_CPU_SH7203_H_ */ diff --git a/include/asm-sh/cpu_sh7710.h b/include/asm-sh/cpu_sh7710.h deleted file mode 100644 index e223f1ca16..0000000000 --- a/include/asm-sh/cpu_sh7710.h +++ /dev/null @@ -1,64 +0,0 @@ -#ifndef _ASM_CPU_SH7710_H_ -#define _ASM_CPU_SH7710_H_ - -#define CACHE_OC_NUM_WAYS 4 -#define CCR_CACHE_INIT 0x0000000D - -/* MMU and Cache control */ -#define MMUCR 0xFFFFFFE0 -#define CCR 0xFFFFFFEC - -/* PFC */ -#define PACR 0xA4050100 -#define PBCR 0xA4050102 -#define PCCR 0xA4050104 -#define PETCR 0xA4050106 - -/* Port Data Registers */ -#define PADR 0xA4050120 -#define PBDR 0xA4050122 -#define PCDR 0xA4050124 - -/* BSC */ -#define CMNCR 0xA4FD0000 -#define CS0BCR 0xA4FD0004 -#define CS2BCR 0xA4FD0008 -#define CS3BCR 0xA4FD000C -#define CS4BCR 0xA4FD0010 -#define CS5ABCR 0xA4FD0014 -#define CS5BBCR 0xA4FD0018 -#define CS6ABCR 0xA4FD001C -#define CS6BBCR 0xA4FD0020 -#define CS0WCR 0xA4FD0024 -#define CS2WCR 0xA4FD0028 -#define CS3WCR 0xA4FD002C -#define CS4WCR 0xA4FD0030 -#define CS5AWCR 0xA4FD0034 -#define CS5BWCR 0xA4FD0038 -#define CS6AWCR 0xA4FD003C -#define CS6BWCR 0xA4FD0040 - -/* SDRAM controller */ -#define SDCR 0xA4FD0044 -#define RTCSR 0xA4FD0048 -#define RTCNT 0xA4FD004C -#define RTCOR 0xA4FD0050 - -/* SCIF */ -#define SCSMR_0 0xA4400000 -#define SCIF0_BASE SCSMR_0 -#define SCSMR_0 0xA4410000 -#define SCIF1_BASE SCSMR_1 - -/* Timer */ -#define TSTR0 0xA412FE92 -#define TSTR TSTR0 -#define TCNT0 0xa412FE98 -#define TCR0 0xa412FE9C - -/* On chip oscillator circuits */ -#define FRQCR 0xA415FF80 -#define WTCNT 0xA415FF84 -#define WTCSR 0xA415FF86 - -#endif /* _ASM_CPU_SH7710_H_ */ diff --git a/include/asm-sh/cpu_sh7720.h b/include/asm-sh/cpu_sh7720.h deleted file mode 100644 index 1b393b88a6..0000000000 --- a/include/asm-sh/cpu_sh7720.h +++ /dev/null @@ -1,230 +0,0 @@ -/* - * Copyright 2007 (C) - * Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> - * - * Copyright 2008 (C) - * Mark Jonas <mark.jonas@de.bosch.com> - * - * SH7720 Internal I/O register - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ASM_CPU_SH7720_H_ -#define _ASM_CPU_SH7720_H_ - -#define CACHE_OC_NUM_WAYS 4 -#define CCR_CACHE_INIT 0x0000000B - -/* EXP */ -#define TRA 0xFFFFFFD0 -#define EXPEVT 0xFFFFFFD4 -#define INTEVT 0xFFFFFFD8 - -/* MMU */ -#define MMUCR 0xFFFFFFE0 -#define PTEH 0xFFFFFFF0 -#define PTEL 0xFFFFFFF4 -#define TTB 0xFFFFFFF8 - -/* CACHE */ -#define CCR 0xFFFFFFEC - -/* INTC */ -#define IPRF 0xA4080000 -#define IPRG 0xA4080002 -#define IPRH 0xA4080004 -#define IPRI 0xA4080006 -#define IPRJ 0xA4080008 -#define IRR5 0xA4080020 -#define IRR6 0xA4080022 -#define IRR7 0xA4080024 -#define IRR8 0xA4080026 -#define IRR9 0xA4080028 -#define IRR0 0xA4140004 -#define IRR1 0xA4140006 -#define IRR2 0xA4140008 -#define IRR3 0xA414000A -#define IRR4 0xA414000C -#define ICR1 0xA4140010 -#define ICR2 0xA4140012 -#define PINTER 0xA4140014 -#define IPRC 0xA4140016 -#define IPRD 0xA4140018 -#define IPRE 0xA414001A -#define ICR0 0xA414FEE0 -#define IPRA 0xA414FEE2 -#define IPRB 0xA414FEE4 - -/* BSC */ -#define BSC_BASE 0xA4FD0000 -#define CMNCR (BSC_BASE + 0x00) -#define CS0BCR (BSC_BASE + 0x04) -#define CS2BCR (BSC_BASE + 0x08) -#define CS3BCR (BSC_BASE + 0x0C) -#define CS4BCR (BSC_BASE + 0x10) -#define CS5ABCR (BSC_BASE + 0x14) -#define CS5BBCR (BSC_BASE + 0x18) -#define CS6ABCR (BSC_BASE + 0x1C) -#define CS6BBCR (BSC_BASE + 0x20) -#define CS0WCR (BSC_BASE + 0x24) -#define CS2WCR (BSC_BASE + 0x28) -#define CS3WCR (BSC_BASE + 0x2C) -#define CS4WCR (BSC_BASE + 0x30) -#define CS5AWCR (BSC_BASE + 0x34) -#define CS5BWCR (BSC_BASE + 0x38) -#define CS6AWCR (BSC_BASE + 0x3C) -#define CS6BWCR (BSC_BASE + 0x40) -#define SDCR (BSC_BASE + 0x44) -#define RTCSR (BSC_BASE + 0x48) -#define RTCNR (BSC_BASE + 0x4C) -#define RTCOR (BSC_BASE + 0x50) -#define SDMR2 (BSC_BASE + 0x4000) -#define SDMR3 (BSC_BASE + 0x5000) - -/* DMAC */ - -/* CPG */ -#define UCLKCR 0xA40A0008 -#define FRQCR 0xA415FF80 - -/* LOW POWER MODE */ - -/* TMU */ -#define TMU_BASE 0xA412FE90 -#define TSTR (TMU_BASE + 0x02) -#define TCOR0 (TMU_BASE + 0x04) -#define TCNT0 (TMU_BASE + 0x08) -#define TCR0 (TMU_BASE + 0x0C) -#define TCOR1 (TMU_BASE + 0x10) -#define TCNT1 (TMU_BASE + 0x14) -#define TCR1 (TMU_BASE + 0x18) -#define TCOR2 (TMU_BASE + 0x1C) -#define TCNT2 (TMU_BASE + 0x20) -#define TCR2 (TMU_BASE + 0x24) - -/* TPU */ -#define TPU_BASE 0xA4480000 -#define TPU_TSTR (TPU_BASE + 0x00) -#define TPU_TCR0 (TPU_BASE + 0x10) -#define TPU_TMDR0 (TPU_BASE + 0x14) -#define TPU_TIOR0 (TPU_BASE + 0x18) -#define TPU_TIER0 (TPU_BASE + 0x1C) -#define TPU_TSR0 (TPU_BASE + 0x20) -#define TPU_TCNT0 (TPU_BASE + 0x24) -#define TPU_TGRA0 (TPU_BASE + 0x28) -#define TPU_TGRB0 (TPU_BASE + 0x2C) -#define TPU_TGRC0 (TPU_BASE + 0x30) -#define TPU_TGRD0 (TPU_BASE + 0x34) -#define TPU_TCR1 (TPU_BASE + 0x50) -#define TPU_TMDR1 (TPU_BASE + 0x54) -#define TPU_TIOR1 (TPU_BASE + 0x58) -#define TPU_TIER1 (TPU_BASE + 0x5C) -#define TPU_TSR1 (TPU_BASE + 0x60) -#define TPU_TCNT1 (TPU_BASE + 0x64) -#define TPU_TGRA1 (TPU_BASE + 0x68) -#define TPU_TGRB1 (TPU_BASE + 0x6C) -#define TPU_TGRC1 (TPU_BASE + 0x70) -#define TPU_TGRD1 (TPU_BASE + 0x74) -#define TPU_TCR2 (TPU_BASE + 0x90) -#define TPU_TMDR2 (TPU_BASE + 0x94) -#define TPU_TIOR2 (TPU_BASE + 0x98) -#define TPU_TIER2 (TPU_BASE + 0x9C) -#define TPU_TSR2 (TPU_BASE + 0xB0) -#define TPU_TCNT2 (TPU_BASE + 0xB4) -#define TPU_TGRA2 (TPU_BASE + 0xB8) -#define TPU_TGRB2 (TPU_BASE + 0xBC) -#define TPU_TGRC2 (TPU_BASE + 0xC0) -#define TPU_TGRD2 (TPU_BASE + 0xC4) -#define TPU_TCR3 (TPU_BASE + 0xD0) -#define TPU_TMDR3 (TPU_BASE + 0xD4) -#define TPU_TIOR3 (TPU_BASE + 0xD8) -#define TPU_TIER3 (TPU_BASE + 0xDC) -#define TPU_TSR3 (TPU_BASE + 0xE0) -#define TPU_TCNT3 (TPU_BASE + 0xE4) -#define TPU_TGRA3 (TPU_BASE + 0xE8) -#define TPU_TGRB3 (TPU_BASE + 0xEC) -#define TPU_TGRC3 (TPU_BASE + 0xF0) -#define TPU_TGRD3 (TPU_BASE + 0xF4) - -/* CMT */ - -/* SIOF */ - -/* SCIF */ -#define SCIF0_BASE 0xA4430000 - -/* SIM */ - -/* IrDA */ - -/* IIC */ - -/* LCDC */ - -/* USBF */ - -/* MMCIF */ - -/* PFC */ -#define PFC_BASE 0xA4050100 -#define PACR (PFC_BASE + 0x00) -#define PBCR (PFC_BASE + 0x02) -#define PCCR (PFC_BASE + 0x04) -#define PDCR (PFC_BASE + 0x06) -#define PECR (PFC_BASE + 0x08) -#define PFCR (PFC_BASE + 0x0A) -#define PGCR (PFC_BASE + 0x0C) -#define PHCR (PFC_BASE + 0x0E) -#define PJCR (PFC_BASE + 0x10) -#define PKCR (PFC_BASE + 0x12) -#define PLCR (PFC_BASE + 0x14) -#define PMCR (PFC_BASE + 0x16) -#define PPCR (PFC_BASE + 0x18) -#define PRCR (PFC_BASE + 0x1A) -#define PSCR (PFC_BASE + 0x1C) -#define PTCR (PFC_BASE + 0x1E) -#define PUCR (PFC_BASE + 0x20) -#define PVCR (PFC_BASE + 0x22) -#define PSELA (PFC_BASE + 0x24) -#define PSELB (PFC_BASE + 0x26) -#define PSELC (PFC_BASE + 0x28) -#define PSELD (PFC_BASE + 0x2A) - -/* I/O Port */ -#define PORT_BASE 0xA4050100 -#define PADR (PORT_BASE + 0x40) -#define PBDR (PORT_BASE + 0x42) -#define PCDR (PORT_BASE + 0x44) -#define PDDR (PORT_BASE + 0x46) -#define PEDR (PORT_BASE + 0x48) -#define PFDR (PORT_BASE + 0x4A) -#define PGDR (PORT_BASE + 0x4C) -#define PHDR (PORT_BASE + 0x4E) -#define PJDR (PORT_BASE + 0x50) -#define PKDR (PORT_BASE + 0x52) -#define PLDR (PORT_BASE + 0x54) -#define PMDR (PORT_BASE + 0x56) -#define PPDR (PORT_BASE + 0x58) -#define PRDR (PORT_BASE + 0x5A) -#define PSDR (PORT_BASE + 0x5C) -#define PTDR (PORT_BASE + 0x5E) -#define PUDR (PORT_BASE + 0x60) -#define PVDR (PORT_BASE + 0x62) - -/* H-UDI */ - -#endif /* _ASM_CPU_SH7720_H_ */ diff --git a/include/asm-sh/cpu_sh7722.h b/include/asm-sh/cpu_sh7722.h deleted file mode 100644 index 0975b78e9b..0000000000 --- a/include/asm-sh/cpu_sh7722.h +++ /dev/null @@ -1,1337 +0,0 @@ -/* - * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * - * SH7722 Internal I/O register - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ASM_CPU_SH7722_H_ -#define _ASM_CPU_SH7722_H_ - -#define CACHE_OC_NUM_WAYS 4 -#define CCR_CACHE_INIT 0x0000090d - -/* EXP */ -#define TRA 0xFF000020 -#define EXPEVT 0xFF000024 -#define INTEVT 0xFF000028 - -/* MMU */ -#define PTEH 0xFF000000 -#define PTEL 0xFF000004 -#define TTB 0xFF000008 -#define TEA 0xFF00000C -#define MMUCR 0xFF000010 -#define PASCR 0xFF000070 -#define IRMCR 0xFF000078 - -/* CACHE */ -#define CCR 0xFF00001C -#define RAMCR 0xFF000074 - -/* XY MEMORY */ -#define XSA 0xFF000050 -#define YSA 0xFF000054 -#define XDA 0xFF000058 -#define YDA 0xFF00005C -#define XPR 0xFF000060 -#define YPR 0xFF000064 -#define XEA 0xFF000068 -#define YEA 0xFF00006C - -/* INTC */ -#define ICR0 0xA4140000 -#define ICR1 0xA414001C -#define INTPRI0 0xA4140010 -#define INTREQ0 0xA4140024 -#define INTMSK0 0xA4140044 -#define INTMSKCLR0 0xA4140064 -#define NMIFCR 0xA41400C0 -#define USERIMASK 0xA4700000 -#define IPRA 0xA4080000 -#define IPRB 0xA4080004 -#define IPRC 0xA4080008 -#define IPRD 0xA408000C -#define IPRE 0xA4080010 -#define IPRF 0xA4080014 -#define IPRG 0xA4080018 -#define IPRH 0xA408001C -#define IPRI 0xA4080020 -#define IPRJ 0xA4080024 -#define IPRK 0xA4080028 -#define IPRL 0xA408002C -#define IMR0 0xA4080080 -#define IMR1 0xA4080084 -#define IMR2 0xA4080088 -#define IMR3 0xA408008C -#define IMR4 0xA4080090 -#define IMR5 0xA4080094 -#define IMR6 0xA4080098 -#define IMR7 0xA408009C -#define IMR8 0xA40800A0 -#define IMR9 0xA40800A4 -#define IMR10 0xA40800A8 -#define IMR11 0xA40800AC -#define IMCR0 0xA40800C0 -#define IMCR1 0xA40800C4 -#define IMCR2 0xA40800C8 -#define IMCR3 0xA40800CC -#define IMCR4 0xA40800D0 -#define IMCR5 0xA40800D4 -#define IMCR6 0xA40800D8 -#define IMCR7 0xA40800DC -#define IMCR8 0xA40800E0 -#define IMCR9 0xA40800E4 -#define IMCR10 0xA40800E8 -#define IMCR11 0xA40800EC -#define MFI_IPRA 0xA40B0000 -#define MFI_IPRB 0xA40B0004 -#define MFI_IPRC 0xA40B0008 -#define MFI_IPRD 0xA40B000C -#define MFI_IPRE 0xA40B0010 -#define MFI_IPRF 0xA40B0014 -#define MFI_IPRG 0xA40B0018 -#define MFI_IPRH 0xA40B001C -#define MFI_IPRI 0xA40B0020 -#define MFI_IPRJ 0xA40B0024 -#define MFI_IPRK 0xA40B0028 -#define MFI_IPRL 0xA40B002C -#define MFI_IMR0 0xA40B0080 -#define MFI_IMR1 0xA40B0084 -#define MFI_IMR2 0xA40B0088 -#define MFI_IMR3 0xA40B008C -#define MFI_IMR4 0xA40B0090 -#define MFI_IMR5 0xA40B0094 -#define MFI_IMR6 0xA40B0098 -#define MFI_IMR7 0xA40B009C -#define MFI_IMR8 0xA40B00A0 -#define MFI_IMR9 0xA40B00A4 -#define MFI_IMR10 0xA40B00A8 -#define MFI_IMR11 0xA40B00AC -#define MFI_IMCR0 0xA40B00C0 -#define MFI_IMCR1 0xA40B00C4 -#define MFI_IMCR2 0xA40B00C8 -#define MFI_IMCR3 0xA40B00CC -#define MFI_IMCR4 0xA40B00D0 -#define MFI_IMCR5 0xA40B00D4 -#define MFI_IMCR6 0xA40B00D8 -#define MFI_IMCR7 0xA40B00DC -#define MFI_IMCR8 0xA40B00E0 -#define MFI_IMCR9 0xA40B00E4 -#define MFI_IMCR10 0xA40B00E8 -#define MFI_IMCR11 0xA40B00EC - -/* BSC */ -#define CMNCR 0xFEC10000 -#define CS0BCR 0xFEC10004 -#define CS2BCR 0xFEC10008 -#define CS4BCR 0xFEC10010 -#define CS5ABCR 0xFEC10014 -#define CS5BBCR 0xFEC10018 -#define CS6ABCR 0xFEC1001C -#define CS6BBCR 0xFEC10020 -#define CS0WCR 0xFEC10024 -#define CS2WCR 0xFEC10028 -#define CS4WCR 0xFEC10030 -#define CS5AWCR 0xFEC10034 -#define CS5BWCR 0xFEC10038 -#define CS6AWCR 0xFEC1003C -#define CS6BWCR 0xFEC10040 -#define RBWTCNT 0xFEC10054 - -/* SBSC */ -#define SBSC_SDCR 0xFE400008 -#define SBSC_SDWCR 0xFE40000C -#define SBSC_SDPCR 0xFE400010 -#define SBSC_RTCSR 0xFE400014 -#define SBSC_RTCNT 0xFE400018 -#define SBSC_RTCOR 0xFE40001C -#define SBSC_RFCR 0xFE400020 - -/* DMAC */ -#define SAR_0 0xFE008020 -#define DAR_0 0xFE008024 -#define TCR_0 0xFE008028 -#define CHCR_0 0xFE00802C -#define SAR_1 0xFE008030 -#define DAR_1 0xFE008034 -#define TCR_1 0xFE008038 -#define CHCR_1 0xFE00803C -#define SAR_2 0xFE008040 -#define DAR_2 0xFE008044 -#define TCR_2 0xFE008048 -#define CHCR_2 0xFE00804C -#define SAR_3 0xFE008050 -#define DAR_3 0xFE008054 -#define TCR_3 0xFE008058 -#define CHCR_3 0xFE00805C -#define SAR_4 0xFE008070 -#define DAR_4 0xFE008074 -#define TCR_4 0xFE008078 -#define CHCR_4 0xFE00807C -#define SAR_5 0xFE008080 -#define DAR_5 0xFE008084 -#define TCR_5 0xFE008088 -#define CHCR_5 0xFE00808C -#define SARB_0 0xFE008120 -#define DARB_0 0xFE008124 -#define TCRB_0 0xFE008128 -#define SARB_1 0xFE008130 -#define DARB_1 0xFE008134 -#define TCRB_1 0xFE008138 -#define SARB_2 0xFE008140 -#define DARB_2 0xFE008144 -#define TCRB_2 0xFE008148 -#define SARB_3 0xFE008150 -#define DARB_3 0xFE008154 -#define TCRB_3 0xFE008158 -#define DMAOR 0xFE008060 -#define DMARS_0 0xFE009000 -#define DMARS_1 0xFE009004 -#define DMARS_2 0xFE009008 - -/* CPG */ -#define FRQCR 0xA4150000 -#define VCLKCR 0xA4150004 -#define SCLKACR 0xA4150008 -#define SCLKBCR 0xA415000C -#define PLLCR 0xA4150024 -#define DLLFRQ 0xA4150050 - -/* LOW POWER MODE */ -#define STBCR 0xA4150020 -#define MSTPCR0 0xA4150030 -#define MSTPCR1 0xA4150034 -#define MSTPCR2 0xA4150038 -#define BAR 0xA4150040 - -/* RWDT */ -#define RWTCNT 0xA4520000 -#define RWTCSR 0xA4520004 -#define WTCNT RWTCNT - - -/* TMU */ -#define TSTR 0xFFD80004 -#define TCOR0 0xFFD80008 -#define TCNT0 0xFFD8000C -#define TCR0 0xFFD80010 -#define TCOR1 0xFFD80014 -#define TCNT1 0xFFD80018 -#define TCR1 0xFFD8001C -#define TCOR2 0xFFD80020 -#define TCNT2 0xFFD80024 -#define TCR2 0xFFD80028 - -/* TPU */ -#define TPU_TSTR 0xA4C90000 -#define TPU_TCR0 0xA4C90010 -#define TPU_TMDR0 0xA4C90014 -#define TPU_TIOR0 0xA4C90018 -#define TPU_TIER0 0xA4C9001C -#define TPU_TSR0 0xA4C90020 -#define TPU_TCNT0 0xA4C90024 -#define TPU_TGR0A 0xA4C90028 -#define TPU_TGR0B 0xA4C9002C -#define TPU_TGR0C 0xA4C90030 -#define TPU_TGR0D 0xA4C90034 -#define TPU_TCR1 0xA4C90050 -#define TPU_TMDR1 0xA4C90054 -#define TPU_TIER1 0xA4C9005C -#define TPU_TSR1 0xA4C90060 -#define TPU_TCNT1 0xA4C90064 -#define TPU_TGR1A 0xA4C90068 -#define TPU_TGR1B 0xA4C9006C -#define TPU_TGR1C 0xA4C90070 -#define TPU_TGR1D 0xA4C90074 -#define TPU_TCR2 0xA4C90090 -#define TPU_TMDR2 0xA4C90094 -#define TPU_TIER2 0xA4C9009C -#define TPU_TSR2 0xA4C900A0 -#define TPU_TCNT2 0xA4C900A4 -#define TPU_TGR2A 0xA4C900A8 -#define TPU_TGR2B 0xA4C900AC -#define TPU_TGR2C 0xA4C900B0 -#define TPU_TGR2D 0xA4C900B4 -#define TPU_TCR3 0xA4C900D0 -#define TPU_TMDR3 0xA4C900D4 -#define TPU_TIER3 0xA4C900DC -#define TPU_TSR3 0xA4C900E0 -#define TPU_TCNT3 0xA4C900E4 -#define TPU_TGR3A 0xA4C900E8 -#define TPU_TGR3B 0xA4C900EC -#define TPU_TGR3C 0xA4C900F0 -#define TPU_TGR3D 0xA4C900F4 - -/* CMT */ -#define CMSTR 0xA44A0000 -#define CMCSR 0xA44A0060 -#define CMCNT 0xA44A0064 -#define CMCOR 0xA44A0068 - -/* SIO */ -#define SIOMDR 0xA4500000 -#define SIOCTR 0xA4500004 -#define SIOSTBCR0 0xA4500008 -#define SIOSTBCR1 0xA450000C -#define SIOTDR 0xA4500014 -#define SIORDR 0xA4500018 -#define SIOSTR 0xA450001C -#define SIOIER 0xA4500020 -#define SIOSCR 0xA4500024 - -/* SIOF */ -#define SIMDR0 0xA4410000 -#define SISCR0 0xA4410002 -#define SITDAR0 0xA4410004 -#define SIRDAR0 0xA4410006 -#define SICDAR0 0xA4410008 -#define SICTR0 0xA441000C -#define SIFCTR0 0xA4410010 -#define SISTR0 0xA4410014 -#define SIIER0 0xA4410016 -#define SITDR0 0xA4410020 -#define SIRDR0 0xA4410024 -#define SITCR0 0xA4410028 -#define SIRCR0 0xA441002C -#define SPICR0 0xA4410030 -#define SIMDR1 0xA4420000 -#define SISCR1 0xA4420002 -#define SITDAR1 0xA4420004 -#define SIRDAR1 0xA4420006 -#define SICDAR1 0xA4420008 -#define SICTR1 0xA442000C -#define SIFCTR1 0xA4420010 -#define SISTR1 0xA4420014 -#define SIIER1 0xA4420016 -#define SITDR1 0xA4420020 -#define SIRDR1 0xA4420024 -#define SITCR1 0xA4420028 -#define SIRCR1 0xA442002C -#define SPICR1 0xA4420030 - -/* SCIF */ -/* -#define SCSMR 0xFFE00000 -#define SCBRR 0xFFE00004 -#define SCSCR 0xFFE00008 -#define SCFTDR 0xFFE0000C -#define SCFSR 0xFFE00010 -#define SCFRDR 0xFFE00014 -#define SCFCR 0xFFE00018 -#define SCFDR 0xFFE0001C -#define SCLSR 0xFFE00024 -#define SCSMR1 0xFFE10000 -#define SCBRR1 0xFFE10004 -#define SCSCR1 0xFFE10008 -#define SCFTDR1 0xFFE1000C -#define SCFSR1 0xFFE10010 -#define SCFRDR1 0xFFE10014 -#define SCFCR1 0xFFE10018 -#define SCFDR1 0xFFE1001C -#define SCLSR1 0xFFE10024 -#define SCSMR2 0xFFE20000 -#define SCBRR2 0xFFE20004 -#define SCSCR2 0xFFE20008 -#define SCFTDR2 0xFFE2000C -#define SCFSR2 0xFFE20010 -#define SCFRDR2 0xFFE20014 -#define SCFCR2 0xFFE20018 -#define SCFDR2 0xFFE2001C -#define SCLSR2 0xFFE20024 -#define SCSMR3 0xFFE30000 -#define SCBRR3 0xFFE30004 -#define SCSCR3 0xFFE30008 -#define SCFTDR3 0xFFE3000C -#define SCFSR3 0xFFE30010 -#define SCFRDR3 0xFFE30014 -#define SCFCR3 0xFFE30018 -#define SCFDR3 0xFFE3001C -#define SCLSR3 0xFFE30024 -*/ -#define SCIF0_BASE 0xFFE00000 - -/* SIM */ -#define SIM_SCSMR 0xA4490000 -#define SIM_SCBRR 0xA4490002 -#define SIM_SCSCR 0xA4490004 -#define SIM_SCTDR 0xA4490006 -#define SIM_SCSSR 0xA4490008 -#define SIM_SCRDR 0xA449000A -#define SIM_SCSCMR 0xA449000C -#define SIM_SCSC2R 0xA449000E -#define SIM_SCWAIT 0xA4490010 -#define SIM_SCGRD 0xA4490012 -#define SIM_SCSMPL 0xA4490014 -#define SIM_SCDMAEN 0xA4490016 - -/* IrDA */ -#define IRIF_INIT1 0xA45D0012 -#define IRIF_INIT2 0xA45D0014 -#define IRIF_RINTCLR 0xA45D0016 -#define IRIF_TINTCLR 0xA45D0018 -#define IRIF_SIR0 0xA45D0020 -#define IRIF_SIR1 0xA45D0022 -#define IRIF_SIR2 0xA45D0024 -#define IRIF_SIR3 0xA45D0026 -#define IRIF_SIR_FRM 0xA45D0028 -#define IRIF_SIR_EOF 0xA45D002A -#define IRIF_SIR_FLG 0xA45D002C -#define IRIF_SIR_STS2 0xA45D002E -#define IRIF_UART0 0xA45D0030 -#define IRIF_UART1 0xA45D0032 -#define IRIF_UART2 0xA45D0034 -#define IRIF_UART3 0xA45D0036 -#define IRIF_UART4 0xA45D0038 -#define IRIF_UART5 0xA45D003A -#define IRIF_UART6 0xA45D003C -#define IRIF_UART7 0xA45D003E -#define IRIF_CRC0 0xA45D0040 -#define IRIF_CRC1 0xA45D0042 -#define IRIF_CRC2 0xA45D0044 -#define IRIF_CRC3 0xA45D0046 -#define IRIF_CRC4 0xA45D0048 - -/* IIC */ -#define ICDR0 0xA4470000 -#define ICCR0 0xA4470004 -#define ICSR0 0xA4470008 -#define ICIC0 0xA447000C -#define ICCL0 0xA4470010 -#define ICCH0 0xA4470014 -#define ICDR1 0xA4750000 -#define ICCR1 0xA4750004 -#define ICSR1 0xA4750008 -#define ICIC1 0xA475000C -#define ICCL1 0xA4750010 -#define ICCH1 0xA4750014 - -/* FLCTL */ -#define FLCMNCR 0xA4530000 -#define FLCMDCR 0xA4530004 -#define FLCMCDR 0xA4530008 -#define FLADR 0xA453000C -#define FLDATAR 0xA4530010 -#define FLDTCNTR 0xA4530014 -#define FLINTDMACR 0xA4530018 -#define FLBSYTMR 0xA453001C -#define FLBSYCNT 0xA4530020 -#define FLDTFIFO 0xA4530024 -#define FLECFIFO 0xA4530028 -#define FLTRCR 0xA453002C -#define FLADR2 0xA453003C - -/* MFI */ -#define MFIIDX 0xA4C10000 -#define MFIGSR 0xA4C10004 -#define MFISCR 0xA4C10008 -#define MFIMCR 0xA4C1000C -#define MFIIICR 0xA4C10010 -#define MFIEICR 0xA4C10014 -#define MFIADR 0xA4C10018 -#define MFIDATA 0xA4C1001C -#define MFIRCR 0xA4C10020 -#define MFIINTEVT 0xA4C1002C -#define MFIIMASK 0xA4C10030 -#define MFIBCR 0xA4C10040 -#define MFIADRW 0xA4C10044 -#define MFIADRR 0xA4C10048 -#define MFIDATAW 0xA4C1004C -#define MFIDATAR 0xA4C10050 -#define MFIMCRW 0xA4C10054 -#define MFIMCRR 0xA4C10058 -#define MFIDNRW 0xA4C1005C -#define MFIDNRR 0xA4C10060 -#define MFISIZEW 0xA4C10064 -#define MFISIZER 0xA4C10068 -#define MFIDEVCR 0xA4C10038 -#define MFISM4 0xA4C10080 - -/* VPU */ -#define VP4_CTRL 0xFE900000 -#define VP4_VOL_CTRL 0xFE900004 -#define VP4_IMAGE_SIZE 0xFE900008 -#define VP4_MB_NUM 0xFE90000C -#define VP4_DWY_ADDR 0xFE900010 -#define VP4_DWC_ADDR 0xFE900014 -#define VP4_D2WY_ADDR 0xFE900018 -#define VP4_D2WC_ADDR 0xFE90001C -#define VP4_DP1_ADDR 0xFE900020 -#define VP4_DP2_ADDR 0xFE900024 -#define VP4_STRS_ADDR 0xFE900028 -#define VP4_STRE_ADDR 0xFE90002C -#define VP4_VOP_CTRL 0xFE900030 -#define VP4_VOP_TIME 0xFE900034 -#define VP4_263_CTRL 0xFE900038 -#define VP4_264_CTRL 0xFE90003C -#define VP4_VLC_CTRL 0xFE900040 -#define VP4_ENDIAN 0xFE900044 -#define VP4_CMD 0xFE900048 -#define VP4_ME_TH1 0xFE90004C -#define VP4_ME_TH2 0xFE900050 -#define VP4_ME_COSTMB 0xFE900054 -#define VP4_ME_SKIP 0xFE900058 -#define VP4_ME_CTRL 0xFE90005C -#define VP4_MBRF_CTRL 0xFE900060 -#define VP4_MC_CTRL 0xFE900064 -#define VP4_PRED_CTRL 0xFE900068 -#define VP4_SLC_SIZE 0xFE90006C -#define VP4_VOP_MINBIT 0xFE900070 -#define VP4_MB_MAXBIT 0xFE900074 -#define VP4_MB_TBIT 0xFE900078 -#define VP4_RCQNT 0xFE90007C -#define VP4_RCRP 0xFE900080 -#define VP4_RCDJ 0xFE900084 -#define VP4_RCWQ 0xFE900088 -#define VP4_FWD_TIME 0xFE900094 -#define VP4_BWD_TIME 0xFE900098 -#define VP4_PST_TIME 0xFE90009C -#define VP4_ILTFRAME 0xFE9000A0 -#define VP4_EC_REF 0xFE9000A4 -#define VP4_STATUS 0xFE900100 -#define VP4_IRQ_ENB 0xFE900104 -#define VP4_IRQ_STA 0xFE900108 -#define VP4_VOP_BIT 0xFE90010C -#define VP4_PRV_BIT 0xFE900110 -#define VP4_SLC_MB 0xFE900114 -#define VP4_QSUM 0xFE900118 -#define VP4_DEC_ERR 0xFE90011C -#define VP4_ERR_AREA 0xFE900120 -#define VP4_NEXT_CODE 0xFE900124 -#define VP4_MB_ATTR 0xFE900128 -#define VP4_DBMON 0xFE90012C -#define VP4_DEBUG 0xFE900130 -#define VP4_ERR_DET 0xFE900134 -#define VP4_CLK_STOP 0xFE900138 -#define VP4_MB_SADA 0xFE90013C -#define VP4_MB_SADR 0xFE900140 -#define VP4_MAT_RAM 0xFE901000 -#define VP4_NC_RAM 0xFE902000 -#define WT 0xFE9020CC -#define VP4_CPY_ADDR 0xFE902264 -#define VP4_CPC_ADDR 0xFE902268 -#define VP4_R0Y_ADDR 0xFE90226C -#define VP4_R0C_ADDR 0xFE902270 -#define VP4_R1Y_ADDR 0xFE902274 -#define VP4_R1C_ADDR 0xFE902278 -#define VP4_R2Y_ADDR 0xFE90227C -#define VP4_R2C_ADDR 0xFE902280 -#define VP4_R3Y_ADDR 0xFE902284 -#define VP4_R3C_ADDR 0xFE902288 -#define VP4_R4Y_ADDR 0xFE90228C -#define VP4_R4C_ADDR 0xFE902290 -#define VP4_R5Y_ADDR 0xFE902294 -#define VP4_R5C_ADDR 0xFE902298 -#define VP4_R6Y_ADDR 0xFE90229C -#define VP4_R6C_ADDR 0xFE9022A0 -#define VP4_R7Y_ADDR 0xFE9022A4 -#define VP4_R7C_ADDR 0xFE9022A8 -#define VP4_R8Y_ADDR 0xFE9022AC -#define VP4_R8C_ADDR 0xFE9022B0 -#define VP4_R9Y_ADDR 0xFE9022B4 -#define VP4_R9C_ADDR 0xFE9022B8 -#define VP4_RAY_ADDR 0xFE9022BC -#define VP4_RAC_ADDR 0xFE9022C0 -#define VP4_RBY_ADDR 0xFE9022C4 -#define VP4_RBC_ADDR 0xFE9022C8 -#define VP4_RCY_ADDR 0xFE9022CC -#define VP4_RCC_ADDR 0xFE9022D0 -#define VP4_RDY_ADDR 0xFE9022D4 -#define VP4_RDC_ADDR 0xFE9022D8 -#define VP4_REY_ADDR 0xFE9022DC -#define VP4_REC_ADDR 0xFE9022E0 -#define VP4_RFY_ADDR 0xFE9022E4 -#define VP4_RFC_ADDR 0xFE9022E8 - -/* VIO(CEU) */ -#define CAPSR 0xFE910000 -#define CAPCR 0xFE910004 -#define CAMCR 0xFE910008 -#define CMCYR 0xFE91000C -#define CAMOR 0xFE910010 -#define CAPWR 0xFE910014 -#define CAIFR 0xFE910018 -#define CSTCR 0xFE910020 -#define CSECR 0xFE910024 -#define CRCNTR 0xFE910028 -#define CRCMPR 0xFE91002C -#define CFLCR 0xFE910030 -#define CFSZR 0xFE910034 -#define CDWDR 0xFE910038 -#define CDAYR 0xFE91003C -#define CDACR 0xFE910040 -#define CDBYR 0xFE910044 -#define CDBCR 0xFE910048 -#define CBDSR 0xFE91004C -#define CLFCR 0xFE910060 -#define CDOCR 0xFE910064 -#define CDDCR 0xFE910068 -#define CDDAR 0xFE91006C -#define CEIER 0xFE910070 -#define CETCR 0xFE910074 -#define CSTSR 0xFE91007C -#define CSRTR 0xFE910080 -#define CDAYR2 0xFE910090 -#define CDACR2 0xFE910094 -#define CDBYR2 0xFE910098 -#define CDBCR2 0xFE91009C - -/* VIO(VEU) */ -#define VESTR 0xFE920000 -#define VESWR 0xFE920010 -#define VESSR 0xFE920014 -#define VSAYR 0xFE920018 -#define VSACR 0xFE92001C -#define VBSSR 0xFE920020 -#define VEDWR 0xFE920030 -#define VDAYR 0xFE920034 -#define VDACR 0xFE920038 -#define VTRCR 0xFE920050 -#define VRFCR 0xFE920054 -#define VRFSR 0xFE920058 -#define VENHR 0xFE92005C -#define VFMCR 0xFE920070 -#define VVTCR 0xFE920074 -#define VHTCR 0xFE920078 -#define VAPCR 0xFE920080 -#define VECCR 0xFE920084 -#define VAFXR 0xFE920090 -#define VSWPR 0xFE920094 -#define VEIER 0xFE9200A0 -#define VEVTR 0xFE9200A4 -#define VSTAR 0xFE9200B0 -#define VBSRR 0xFE9200B4 - -/* VIO(BEU) */ -#define BESTR 0xFE930000 -#define BSMWR1 0xFE930010 -#define BSSZR1 0xFE930014 -#define BSAYR1 0xFE930018 -#define BSACR1 0xFE93001C -#define BSAAR1 0xFE930020 -#define BSIFR1 0xFE930024 -#define BSMWR2 0xFE930028 -#define BSSZR2 0xFE93002C -#define BSAYR2 0xFE930030 -#define BSACR2 0xFE930034 -#define BSAAR2 0xFE930038 -#define BSIFR2 0xFE93003C -#define BSMWR3 0xFE930040 -#define BSSZR3 0xFE930044 -#define BSAYR3 0xFE930048 -#define BSACR3 0xFE93004C -#define BSAAR3 0xFE930050 -#define BSIFR3 0xFE930054 -#define BTPSR 0xFE930058 -#define BMSMWR1 0xFE930070 -#define BMSSZR1 0xFE930074 -#define BMSAYR1 0xFE930078 -#define BMSACR1 0xFE93007C -#define BMSMWR2 0xFE930080 -#define BMSSZR2 0xFE930084 -#define BMSAYR2 0xFE930088 -#define BMSACR2 0xFE93008C -#define BMSMWR3 0xFE930090 -#define BMSSZR3 0xFE930094 -#define BMSAYR3 0xFE930098 -#define BMSACR3 0xFE93009C -#define BMSMWR4 0xFE9300A0 -#define BMSSZR4 0xFE9300A4 -#define BMSAYR4 0xFE9300A8 -#define BMSACR4 0xFE9300AC -#define BMSIFR 0xFE9300F0 -#define BBLCR0 0xFE930100 -#define BBLCR1 0xFE930104 -#define BPROCR 0xFE930108 -#define BMWCR0 0xFE93010C -#define BLOCR1 0xFE930114 -#define BLOCR2 0xFE930118 -#define BLOCR3 0xFE93011C -#define BMLOCR1 0xFE930120 -#define BMLOCR2 0xFE930124 -#define BMLOCR3 0xFE930128 -#define BMLOCR4 0xFE93012C -#define BMPCCR1 0xFE930130 -#define BMPCCR2 0xFE930134 -#define BPKFR 0xFE930140 -#define BPCCR0 0xFE930144 -#define BPCCR11 0xFE930148 -#define BPCCR12 0xFE93014C -#define BPCCR21 0xFE930150 -#define BPCCR22 0xFE930154 -#define BPCCR31 0xFE930158 -#define BPCCR32 0xFE93015C -#define BDMWR 0xFE930160 -#define BDAYR 0xFE930164 -#define BDACR 0xFE930168 -#define BAFXR 0xFE930180 -#define BSWPR 0xFE930184 -#define BEIER 0xFE930188 -#define BEVTR 0xFE93018C -#define BRCNTR 0xFE930194 -#define BSTAR 0xFE930198 -#define BBRSTR 0xFE93019C -#define BRCHR 0xFE9301A0 -#define CLUT 0xFE933000 - -/* JPU */ -#define JCMOD 0xFEA00000 -#define JCCMD 0xFEA00004 -#define JCSTS 0xFEA00008 -#define JCQTN 0xFEA0000C -#define JCHTN 0xFEA00010 -#define JCDRIU 0xFEA00014 -#define JCDRID 0xFEA00018 -#define JCVSZU 0xFEA0001C -#define JCVSZD 0xFEA00020 -#define JCHSZU 0xFEA00024 -#define JCHSZD 0xFEA00028 -#define JCDTCU 0xFEA0002C -#define JCDTCM 0xFEA00030 -#define JCDTCD 0xFEA00034 -#define JINTE 0xFEA00038 -#define JINTS 0xFEA0003C -#define JCDERR 0xFEA00040 -#define JCRST 0xFEA00044 -#define JIFCNT 0xFEA00060 -#define JIFECNT 0xFEA00070 -#define JIFESYA1 0xFEA00074 -#define JIFESCA1 0xFEA00078 -#define JIFESYA2 0xFEA0007C -#define JIFESCA2 0xFEA00080 -#define JIFESMW 0xFEA00084 -#define JIFESVSZ 0xFEA00088 -#define JIFESHSZ 0xFEA0008C -#define JIFEDA1 0xFEA00090 -#define JIFEDA2 0xFEA00094 -#define JIFEDRSZ 0xFEA00098 -#define JIFDCNT 0xFEA000A0 -#define JIFDSA1 0xFEA000A4 -#define JIFDSA2 0xFEA000A8 -#define JIFDDRSZ 0xFEA000AC -#define JIFDDMW 0xFEA000B0 -#define JIFDDVSZ 0xFEA000B4 -#define JIFDDHSZ 0xFEA000B8 -#define JIFDDYA1 0xFEA000BC -#define JIFDDCA1 0xFEA000C0 -#define JIFDDYA2 0xFEA000C4 -#define JIFDDCA2 0xFEA000C8 -#define JCQTBL0 0xFEA10000 -#define JCQTBL1 0xFEA10040 -#define JCQTBL2 0xFEA10080 -#define JCQTBL3 0xFEA100C0 -#define JCHTBD0 0xFEA10100 -#define JCHTBA0 0xFEA10120 -#define JCHTBD1 0xFEA10200 -#define JCHTBA1 0xFEA10220 - -/* LCDC */ -#define MLDDCKPAT1R 0xFE940400 -#define MLDDCKPAT2R 0xFE940404 -#define SLDDCKPAT1R 0xFE940408 -#define SLDDCKPAT2R 0xFE94040C -#define LDDCKR 0xFE940410 -#define LDDCKSTPR 0xFE940414 -#define MLDMT1R 0xFE940418 -#define MLDMT2R 0xFE94041C -#define MLDMT3R 0xFE940420 -#define MLDDFR 0xFE940424 -#define MLDSM1R 0xFE940428 -#define MLDSM2R 0xFE94042C -#define MLDSA1R 0xFE940430 -#define MLDSA2R 0xFE940434 -#define MLDMLSR 0xFE940438 -#define MLDWBFR 0xFE94043C -#define MLDWBCNTR 0xFE940440 -#define MLDWBAR 0xFE940444 -#define MLDHCNR 0xFE940448 -#define MLDHSYNR 0xFE94044C -#define MLDVLNR 0xFE940450 -#define MLDVSYNR 0xFE940454 -#define MLDHPDR 0xFE940458 -#define MLDVPDR 0xFE94045C -#define MLDPMR 0xFE940460 -#define LDPALCR 0xFE940464 -#define LDINTR 0xFE940468 -#define LDSR 0xFE94046C -#define LDCNT1R 0xFE940470 -#define LDCNT2R 0xFE940474 -#define LDRCNTR 0xFE940478 -#define LDDDSR 0xFE94047C -#define LDRCR 0xFE940484 -#define LDCMRKRGBR 0xFE9404C4 -#define LDCMRKCMYR 0xFE9404C8 -#define LDCMRK1R 0xFE9404CC -#define LDCMRK2R 0xFE9404D0 -#define LDCMGKRGBR 0xFE9404D4 -#define LDCMGKCMYR 0xFE9404D8 -#define LDCMGK1R 0xFE9404DC -#define LDCMGK2R 0xFE9404E0 -#define LDCMBKRGBR 0xFE9404E4 -#define LDCMBKCMYR 0xFE9404E8 -#define LDCMBK1R 0xFE9404EC -#define LDCMBK2R 0xFE9404F0 -#define LDCMHKPR 0xFE9404F4 -#define LDCMHKQR 0xFE9404F8 -#define LDCMSELR 0xFE9404FC -#define LDCMTVR 0xFE940500 -#define LDCMTVSELR 0xFE940504 -#define LDCMDTHR 0xFE940508 -#define LDCMCNTR 0xFE94050C -#define SLDMT1R 0xFE940600 -#define SLDMT2R 0xFE940604 -#define SLDMT3R 0xFE940608 -#define SLDDFR 0xFE94060C -#define SLDSM1R 0xFE940610 -#define SLDSM2R 0xFE940614 -#define SLDSA1R 0xFE940618 -#define SLDSA2R 0xFE94061C -#define SLDMLSR 0xFE940620 -#define SLDHCNR 0xFE940624 -#define SLDHSYNR 0xFE940628 -#define SLDVLNR 0xFE94062C -#define SLDVSYNR 0xFE940630 -#define SLDHPDR 0xFE940634 -#define SLDVPDR 0xFE940638 -#define SLDPMR 0xFE94063C -#define LDDWD0R 0xFE940800 -#define LDDWD1R 0xFE940804 -#define LDDWD2R 0xFE940808 -#define LDDWD3R 0xFE94080C -#define LDDWD4R 0xFE940810 -#define LDDWD5R 0xFE940814 -#define LDDWD6R 0xFE940818 -#define LDDWD7R 0xFE94081C -#define LDDWD8R 0xFE940820 -#define LDDWD9R 0xFE940824 -#define LDDWDAR 0xFE940828 -#define LDDWDBR 0xFE94082C -#define LDDWDCR 0xFE940830 -#define LDDWDDR 0xFE940834 -#define LDDWDER 0xFE940838 -#define LDDWDFR 0xFE94083C -#define LDDRDR 0xFE940840 -#define LDDWAR 0xFE940900 -#define LDDRAR 0xFE940904 -#define LDPR00 0xFE940000 - -/* VOU */ -#define VOUER 0xFE960000 -#define VOUCR 0xFE960004 -#define VOUSTR 0xFE960008 -#define VOUVCR 0xFE96000C -#define VOUISR 0xFE960010 -#define VOUBCR 0xFE960014 -#define VOUDPR 0xFE960018 -#define VOUDSR 0xFE96001C -#define VOUVPR 0xFE960020 -#define VOUIR 0xFE960024 -#define VOUSRR 0xFE960028 -#define VOUMSR 0xFE96002C -#define VOUHIR 0xFE960030 -#define VOUDFR 0xFE960034 -#define VOUAD1R 0xFE960038 -#define VOUAD2R 0xFE96003C -#define VOUAIR 0xFE960040 -#define VOUSWR 0xFE960044 -#define VOURCR 0xFE960048 -#define VOURPR 0xFE960050 - -/* TSIF */ -#define TSCTLR 0xA4C80000 -#define TSPIDR 0xA4C80004 -#define TSCMDR 0xA4C80008 -#define TSSTR 0xA4C8000C -#define TSTSDR 0xA4C80010 -#define TSBUFCLRR 0xA4C80014 -#define TSINTER 0xA4C80018 -#define TSPSCALER 0xA4C80020 -#define TSPSCALERR 0xA4C80024 -#define TSPCRADCMDR 0xA4C80028 -#define TSPCRADCR 0xA4C8002C -#define TSTRPCRADCR 0xA4C80030 -#define TSDPCRADCR 0xA4C80034 - -/* SIU */ -#define IFCTL 0xA454C000 -#define SRCTL 0xA454C004 -#define SFORM 0xA454C008 -#define CKCTL 0xA454C00C -#define TRDAT 0xA454C010 -#define STFIFO 0xA454C014 -#define DPAK 0xA454C01C -#define CKREV 0xA454C020 -#define EVNTC 0xA454C028 -#define SBCTL 0xA454C040 -#define SBPSET 0xA454C044 -#define SBBUS 0xA454C048 -#define SBWFLG 0xA454C058 -#define SBRFLG 0xA454C05C -#define SBWDAT 0xA454C060 -#define SBRDAT 0xA454C064 -#define SBFSTS 0xA454C068 -#define SBDVCA 0xA454C06C -#define SBDVCB 0xA454C070 -#define SBACTIV 0xA454C074 -#define DMAIA 0xA454C090 -#define DMAIB 0xA454C094 -#define DMAOA 0xA454C098 -#define DMAOB 0xA454C09C -#define SPLRI 0xA454C0B8 -#define SPRRI 0xA454C0BC -#define SPURI 0xA454C0C4 -#define SPTIS 0xA454C0C8 -#define SPSTS 0xA454C0CC -#define SPCTL 0xA454C0D0 -#define SPIRI 0xA454C0D4 -#define SPQCF 0xA454C0D8 -#define SPQCS 0xA454C0DC -#define SPQCT 0xA454C0E0 -#define DPEAK 0xA454C0F0 -#define DSLPD 0xA454C0F4 -#define DSLLV 0xA454C0F8 -#define BRGASEL 0xA454C100 -#define BRRA 0xA454C104 -#define BRGBSEL 0xA454C108 -#define BRRB 0xA454C10C - -/* USB */ -#define IFR0 0xA4480000 -#define ISR0 0xA4480010 -#define IER0 0xA4480020 -#define EPDR0I 0xA4480030 -#define EPDR0O 0xA4480034 -#define EPDR0S 0xA4480038 -#define EPDR1 0xA448003C -#define EPDR2 0xA4480040 -#define EPDR3 0xA4480044 -#define EPDR4 0xA4480048 -#define EPDR5 0xA448004C -#define EPDR6 0xA4480050 -#define EPDR7 0xA4480054 -#define EPDR8 0xA4480058 -#define EPDR9 0xA448005C -#define EPSZ0O 0xA4480080 -#define EPSZ3 0xA4480084 -#define EPSZ6 0xA4480088 -#define EPSZ9 0xA448008C -#define TRG 0xA44800A0 -#define DASTS 0xA44800A4 -#define FCLR 0xA44800AA -#define DMA 0xA44800AC -#define EPSTL 0xA44800B2 -#define CVR 0xA44800B4 -#define TSR 0xA44800B8 -#define CTLR 0xA44800BC -#define EPIR 0xA44800C0 -#define XVERCR 0xA44800D0 -#define STLMR 0xA44800D4 - -/* KEYSC */ -#define KYCR1 0xA44B0000 -#define KYCR2 0xA44B0004 -#define KYINDR 0xA44B0008 -#define KYOUTDR 0xA44B000C - -/* MMCIF */ -#define CMDR0 0xA4448000 -#define CMDR1 0xA4448001 -#define CMDR2 0xA4448002 -#define CMDR3 0xA4448003 -#define CMDR4 0xA4448004 -#define CMDR5 0xA4448005 -#define CMDSTRT 0xA4448006 -#define OPCR 0xA444800A -#define CSTR 0xA444800B -#define INTCR0 0xA444800C -#define INTCR1 0xA444800D -#define INTSTR0 0xA444800E -#define INTSTR1 0xA444800F -#define CLKON 0xA4448010 -#define CTOCR 0xA4448011 -#define VDCNT 0xA4448012 -#define TBCR 0xA4448014 -#define MODER 0xA4448016 -#define CMDTYR 0xA4448018 -#define RSPTYR 0xA4448019 -#define TBNCR 0xA444801A -#define RSPR0 0xA4448020 -#define RSPR1 0xA4448021 -#define RSPR2 0xA4448022 -#define RSPR3 0xA4448023 -#define RSPR4 0xA4448024 -#define RSPR5 0xA4448025 -#define RSPR6 0xA4448026 -#define RSPR7 0xA4448027 -#define RSPR8 0xA4448028 -#define RSPR9 0xA4448029 -#define RSPR10 0xA444802A -#define RSPR11 0xA444802B -#define RSPR12 0xA444802C -#define RSPR13 0xA444802D -#define RSPR14 0xA444802E -#define RSPR15 0xA444802F -#define RSPR16 0xA4448030 -#define RSPRD 0xA4448031 -#define DTOUTR 0xA4448032 -#define DR 0xA4448040 -#define FIFOCLR 0xA4448042 -#define DMACR 0xA4448044 -#define INTCR2 0xA4448046 -#define INTSTR2 0xA4448048 - -/* Z3D3 */ -#define DLBI 0xFD980000 -#define DLBD0 0xFD980080 -#define DLBD1 0xFD980100 -#define GEWM 0xFD984000 -#define ICD0 0xFD988000 -#define ICD1 0xFD989000 -#define ICT 0xFD98A000 -#define ILM 0xFD98C000 -#define FLM0 0xFD98C800 -#define FLM1 0xFD98D000 -#define FLUT 0xFD98D800 -#define Z3D_PC 0xFD98E400 -#define Z3D_PCSP 0xFD98E404 -#define Z3D_PAR 0xFD98E408 -#define Z3D_IMADR 0xFD98E40C -#define Z3D_BTR0 0xFD98E410 -#define Z3D_BTR1 0xFD98E414 -#define Z3D_BTR2 0xFD98E418 -#define Z3D_BTR3 0xFD98E41C -#define Z3D_LC0 0xFD98E420 -#define Z3D_LC1 0xFD98E424 -#define Z3D_LC2 0xFD98E428 -#define Z3D_LC3 0xFD98E42C -#define Z3D_FR0 0xFD98E430 -#define Z3D_FR1 0xFD98E434 -#define Z3D_FR2 0xFD98E438 -#define Z3D_SR 0xFD98E440 -#define Z3D_SMDR 0xFD98E444 -#define Z3D_PBIR 0xFD98E448 -#define Z3D_DMDR 0xFD98E44C -#define Z3D_IREG 0xFD98E460 -#define Z3D_AR00 0xFD98E480 -#define Z3D_AR01 0xFD98E484 -#define Z3D_AR02 0xFD98E488 -#define Z3D_AR03 0xFD98E48C -#define Z3D_BR00 0xFD98E490 -#define Z3D_BR01 0xFD98E494 -#define Z3D_IXR00 0xFD98E4A0 -#define Z3D_IXR01 0xFD98E4A4 -#define Z3D_IXR02 0xFD98E4A8 -#define Z3D_IXR03 0xFD98E4AC -#define Z3D_AR10 0xFD98E4C0 -#define Z3D_AR11 0xFD98E4C4 -#define Z3D_AR12 0xFD98E4C8 -#define Z3D_AR13 0xFD98E4CC -#define Z3D_BR10 0xFD98E4D0 -#define Z3D_BR11 0xFD98E4D4 -#define Z3D_IXR10 0xFD98E4E0 -#define Z3D_IXR11 0xFD98E4E4 -#define Z3D_IXR12 0xFD98E4E8 -#define Z3D_IXR13 0xFD98E4EC -#define Z3D_AR20 0xFD98E500 -#define Z3D_AR21 0xFD98E504 -#define Z3D_AR22 0xFD98E508 -#define Z3D_AR23 0xFD98E50C -#define Z3D_BR20 0xFD98E510 -#define Z3D_BR21 0xFD98E514 -#define Z3D_IXR20 0xFD98E520 -#define Z3D_IXR21 0xFD98E524 -#define Z3D_IXR22 0xFD98E528 -#define Z3D_IXR23 0xFD98E52C -#define Z3D_MR0 0xFD98E540 -#define Z3D_MR1 0xFD98E544 -#define Z3D_MR2 0xFD98E548 -#define Z3D_MR3 0xFD98E54C -#define Z3D_WORKRST 0xFD98E558 -#define Z3D_WORKWST 0xFD98E55C -#define Z3D_DBADR 0xFD98E560 -#define Z3D_DLBPRST 0xFD98E564 -#define Z3D_DLBRST 0xFD98E568 -#define Z3D_DLBWST 0xFD98E56C -#define Z3D_UDR0 0xFD98E570 -#define Z3D_UDR1 0xFD98E574 -#define Z3D_UDR2 0xFD98E578 -#define Z3D_UDR3 0xFD98E57C -#define Z3D_CCR0 0xFD98E580 -#define Z3D_CCR1 0xFD98E584 -#define Z3D_EXPR 0xFD98E588 -#define Z3D_V0_X 0xFD9A0000 -#define Z3D_V0_Y 0xFD9A0004 -#define Z3D_V0_Z 0xFD9A0008 -#define Z3D_V0_W 0xFD9A000C -#define Z3D_V0_A 0xFD9A0010 -#define Z3D_V0_R 0xFD9A0014 -#define Z3D_V0_G 0xFD9A0018 -#define Z3D_V0_B 0xFD9A001C -#define Z3D_V0_F 0xFD9A0020 -#define Z3D_V0_SR 0xFD9A0024 -#define Z3D_V0_SG 0xFD9A0028 -#define Z3D_V0_SB 0xFD9A002C -#define Z3D_V0_U0 0xFD9A0030 -#define Z3D_V0_V0 0xFD9A0034 -#define Z3D_V0_U1 0xFD9A0038 -#define Z3D_V0_V1 0xFD9A003C -#define Z3D_V1_X 0xFD9A0080 -#define Z3D_V1_Y 0xFD9A0084 -#define Z3D_V1_Z 0xFD9A0088 -#define Z3D_V1_W 0xFD9A008C -#define Z3D_V1_A 0xFD9A0090 -#define Z3D_V1_R 0xFD9A0094 -#define Z3D_V1_G 0xFD9A0098 -#define Z3D_V1_B 0xFD9A009C -#define Z3D_V1_F 0xFD9A00A0 -#define Z3D_V1_SR 0xFD9A00A4 -#define Z3D_V1_SG 0xFD9A00A8 -#define Z3D_V1_SB 0xFD9A00AC -#define Z3D_V1_U0 0xFD9A00B0 -#define Z3D_V1_V0 0xFD9A00B4 -#define Z3D_V1_U1 0xFD9A00B8 -#define Z3D_V1_V1 0xFD9A00BC -#define Z3D_V2_X 0xFD9A0100 -#define Z3D_V2_Y 0xFD9A0104 -#define Z3D_V2_Z 0xFD9A0108 -#define Z3D_V2_W 0xFD9A010C -#define Z3D_V2_A 0xFD9A0110 -#define Z3D_V2_R 0xFD9A0114 -#define Z3D_V2_G 0xFD9A0118 -#define Z3D_V2_B 0xFD9A011C -#define Z3D_V2_F 0xFD9A0120 -#define Z3D_V2_SR 0xFD9A0124 -#define Z3D_V2_SG 0xFD9A0128 -#define Z3D_V2_SB 0xFD9A012C -#define Z3D_V2_U0 0xFD9A0130 -#define Z3D_V2_V0 0xFD9A0134 -#define Z3D_V2_U1 0xFD9A0138 -#define Z3D_V2_V1 0xFD9A013C -#define Z3D_RENDER 0xFD9A0180 -#define Z3D_POLYGON_OFFSET 0xFD9A0184 -#define Z3D_VERTEX_CONTROL 0xFD9A0200 -#define Z3D_STATE_MODE 0xFD9A0204 -#define Z3D_FPU_MODE 0xFD9A0318 -#define Z3D_SCISSOR_MIN 0xFD9A0400 -#define Z3D_SCISSOR_MAX 0xFD9A0404 -#define Z3D_TEXTURE_MODE_A 0xFD9A0408 -#define Z3D_TEXTURE_MODE_B 0xFD9A040C -#define Z3D_TEXTURE_BASE_HI_A 0xFD9A0418 -#define Z3D_TEXTURE_BASE_LO_A 0xFD9A041C -#define Z3D_TEXTURE_BASE_HI_B 0xFD9A0420 -#define Z3D_TEXTURE_BASE_LO_B 0xFD9A0424 -#define Z3D_TEXTURE_ALPHA_A0 0xFD9A0438 -#define Z3D_TEXTURE_ALPHA_A1 0xFD9A043C -#define Z3D_TEXTURE_ALPHA_A2 0xFD9A0440 -#define Z3D_TEXTURE_ALPHA_A3 0xFD9A0444 -#define Z3D_TEXTURE_ALPHA_A4 0xFD9A0448 -#define Z3D_TEXTURE_ALPHA_A5 0xFD9A044C -#define Z3D_TEXTURE_ALPHA_B0 0xFD9A0450 -#define Z3D_TEXTURE_ALPHA_B1 0xFD9A0454 -#define Z3D_TEXTURE_ALPHA_B2 0xFD9A0458 -#define Z3D_TEXTURE_ALPHA_B3 0xFD9A045C -#define Z3D_TEXTURE_ALPHA_B4 0xFD9A0460 -#define Z3D_TEXTURE_ALPHA_B5 0xFD9A0464 -#define Z3D_TEXTURE_FLUSH 0xFD9A0498 -#define Z3D_GAMMA_TABLE0 0xFD9A049C -#define Z3D_GAMMA_TABLE1 0xFD9A04A0 -#define Z3D_GAMMA_TABLE2 0xFD9A04A4 -#define Z3D_ALPHA_TEST 0xFD9A0800 -#define Z3D_STENCIL_TEST 0xFD9A0804 -#define Z3D_DEPTH_ROP_BLEND_DITHER 0xFD9A0808 -#define Z3D_MASK 0xFD9A080C -#define Z3D_FBUS_MODE 0xFD9A0810 -#define Z3D_GNT_SET 0xFD9A0814 -#define Z3D_BETWEEN_TEST 0xFD9A0818 -#define Z3D_FB_BASE 0xFD9A081C -#define Z3D_LCD_SIZE 0xFD9A0820 -#define Z3D_FB_FLUSH 0xFD9A0824 -#define Z3D_CACHE_INVALID 0xFD9A0828 -#define Z3D_SC_MODE 0xFD9A0830 -#define Z3D_SC0_MIN 0xFD9A0834 -#define Z3D_SC0_MAX 0xFD9A0838 -#define Z3D_SC1_MIN 0xFD9A083C -#define Z3D_SC1_MAX 0xFD9A0840 -#define Z3D_SC2_MIN 0xFD9A0844 -#define Z3D_SC2_MAX 0xFD9A0848 -#define Z3D_SC3_MIN 0xFD9A084C -#define Z3D_SC3_MAX 0xFD9A0850 -#define Z3D_READRESET 0xFD9A0854 -#define Z3D_DET_MIN 0xFD9A0858 -#define Z3D_DET_MAX 0xFD9A085C -#define Z3D_FB_BASE_SR 0xFD9A0860 -#define Z3D_LCD_SIZE_SR 0xFD9A0864 -#define Z3D_2D_CTRL_STATUS 0xFD9A0C00 -#define Z3D_2D_SIZE 0xFD9A0C04 -#define Z3D_2D_SRCLOC 0xFD9A0C08 -#define Z3D_2D_DSTLOC 0xFD9A0C0C -#define Z3D_2D_DMAPORT 0xFD9A0C10 -#define Z3D_2D_CONSTANT_SOURCE0 0xFD9A0C14 -#define Z3D_2D_CONSTANT_SOURCE1 0xFD9A0C18 -#define Z3D_2D_STPCOLOR0 0xFD9A0C1C -#define Z3D_2D_STPCOLOR1 0xFD9A0C20 -#define Z3D_2D_STPPARAMETER_SET0 0xFD9A0C24 -#define Z3D_2D_STPPARAMETER_SET1 0xFD9A0C28 -#define Z3D_2D_STPPAT_0 0xFD9A0C40 -#define Z3D_2D_STPPAT_1 0xFD9A0C44 -#define Z3D_2D_STPPAT_2 0xFD9A0C48 -#define Z3D_2D_STPPAT_3 0xFD9A0C4C -#define Z3D_2D_STPPAT_4 0xFD9A0C50 -#define Z3D_2D_STPPAT_5 0xFD9A0C54 -#define Z3D_2D_STPPAT_6 0xFD9A0C58 -#define Z3D_2D_STPPAT_7 0xFD9A0C5C -#define Z3D_2D_STPPAT_8 0xFD9A0C60 -#define Z3D_2D_STPPAT_9 0xFD9A0C64 -#define Z3D_2D_STPPAT_10 0xFD9A0C68 -#define Z3D_2D_STPPAT_11 0xFD9A0C6C -#define Z3D_2D_STPPAT_12 0xFD9A0C70 -#define Z3D_2D_STPPAT_13 0xFD9A0C74 -#define Z3D_2D_STPPAT_14 0xFD9A0C78 -#define Z3D_2D_STPPAT_15 0xFD9A0C7C -#define Z3D_2D_STPPAT_16 0xFD9A0C80 -#define Z3D_2D_STPPAT_17 0xFD9A0C84 -#define Z3D_2D_STPPAT_18 0xFD9A0C88 -#define Z3D_2D_STPPAT_19 0xFD9A0C8C -#define Z3D_2D_STPPAT_20 0xFD9A0C90 -#define Z3D_2D_STPPAT_21 0xFD9A0C94 -#define Z3D_2D_STPPAT_22 0xFD9A0C98 -#define Z3D_2D_STPPAT_23 0xFD9A0C9C -#define Z3D_2D_STPPAT_24 0xFD9A0CA0 -#define Z3D_2D_STPPAT_25 0xFD9A0CA4 -#define Z3D_2D_STPPAT_26 0xFD9A0CA8 -#define Z3D_2D_STPPAT_27 0xFD9A0CAC -#define Z3D_2D_STPPAT_28 0xFD9A0CB0 -#define Z3D_2D_STPPAT_29 0xFD9A0CB4 -#define Z3D_2D_STPPAT_30 0xFD9A0CB8 -#define Z3D_2D_STPPAT_31 0xFD9A0CBC -#define Z3D_WR_CTRL 0xFD9A1000 -#define Z3D_WR_P0 0xFD9A1004 -#define Z3D_WR_P1 0xFD9A1008 -#define Z3D_WR_P2 0xFD9A100C -#define Z3D_WR_FGC 0xFD9A1010 -#define Z3D_WR_BGC 0xFD9A1014 -#define Z3D_WR_SZ 0xFD9A1018 -#define Z3D_WR_PATPARAM 0xFD9A101C -#define Z3D_WR_PAT 0xFD9A1020 -#define Z3D_SYS_STATUS 0xFD9A1400 -#define Z3D_SYS_RESET 0xFD9A1404 -#define Z3D_SYS_CLK 0xFD9A1408 -#define Z3D_SYS_CONF 0xFD9A140C -#define Z3D_SYS_VERSION 0xFD9A1410 -#define Z3D_SYS_DBINV 0xFD9A1418 -#define Z3D_SYS_I2F_FMT 0xFD9A1420 -#define Z3D_SYS_I2F_SRC 0xFD9A1424 -#define Z3D_SYS_I2F_DST 0xFD9A1428 -#define Z3D_SYS_GBCNT 0xFD9A1430 -#define Z3D_SYS_BSYCNT 0xFD9A1434 -#define Z3D_SYS_INT_STATUS 0xFD9A1450 -#define Z3D_SYS_INT_MASK 0xFD9A1454 -#define Z3D_SYS_INT_CLEAR 0xFD9A1458 -#define TCD0 0xFD9C0000 -#define TCD1 0xFD9C0400 -#define TCD2 0xFD9C0800 -#define TCD3 0xFD9C0C00 -#define TCT0 0xFD9C1000 -#define TCT1 0xFD9C1400 -#define TCT2 0xFD9C1800 -#define TCT3 0xFD9C1C00 - -/* PFC */ -#define PACR 0xA4050100 -#define PBCR 0xA4050102 -#define PCCR 0xA4050104 -#define PDCR 0xA4050106 -#define PECR 0xA4050108 -#define PFCR 0xA405010A -#define PGCR 0xA405010C -#define PHCR 0xA405010E -#define PJCR 0xA4050110 -#define PKCR 0xA4050112 -#define PLCR 0xA4050114 -#define PMCR 0xA4050116 -#define PNCR 0xA4050118 -#define PQCR 0xA405011A -#define PRCR 0xA405011C -#define PSCR 0xA405011E -#define PTCR 0xA4050140 -#define PUCR 0xA4050142 -#define PVCR 0xA4050144 -#define PWCR 0xA4050146 -#define PXCR 0xA4050148 -#define PYCR 0xA405014A -#define PZCR 0xA405014C -#define PSELA 0xA405014E -#define PSELB 0xA4050150 -#define PSELC 0xA4050152 -#define PSELD 0xA4050154 -#define PSELE 0xA4050156 -#define HIZCRA 0xA4050158 -#define HIZCRB 0xA405015A -#define HIZCRC 0xA405015C -#define HIZCRC 0xA405015C -#define MSELCRA 0xA4050180 -#define MSELCRB 0xA4050182 -#define PULCR 0xA4050184 -#define SBSCR 0xA4050186 -#define DRVCR 0xA405018A - -/* I/O Port */ -#define PADR 0xA4050120 -#define PBDR 0xA4050122 -#define PCDR 0xA4050124 -#define PDDR 0xA4050126 -#define PEDR 0xA4050128 -#define PFDR 0xA405012A -#define PGDR 0xA405012C -#define PHDR 0xA405012E -#define PJDR 0xA4050130 -#define PKDR 0xA4050132 -#define PLDR 0xA4050134 -#define PMDR 0xA4050136 -#define PNDR 0xA4050138 -#define PQDR 0xA405013A -#define PRDR 0xA405013C -#define PSDR 0xA405013E -#define PTDR 0xA4050160 -#define PUDR 0xA4050162 -#define PVDR 0xA4050164 -#define PWDR 0xA4050166 -#define PYDR 0xA4050168 -#define PZDR 0xA405016A - -/* UBC */ -#define CBR0 0xFF200000 -#define CRR0 0xFF200004 -#define CAR0 0xFF200008 -#define CAMR0 0xFF20000C -#define CBR1 0xFF200020 -#define CRR1 0xFF200024 -#define CAR1 0xFF200028 -#define CAMR1 0xFF20002C -#define CDR1 0xFF200030 -#define CDMR1 0xFF200034 -#define CETR1 0xFF200038 -#define CCMFR 0xFF200600 -#define CBCR 0xFF200620 - -/* H-UDI */ -#define SDIR 0xFC110000 -#define SDDRH 0xFC110008 -#define SDDRL 0xFC11000A -#define SDINT 0xFC110018 - -#endif /* _ASM_CPU_SH7722_H_ */ diff --git a/include/asm-sh/cpu_sh7723.h b/include/asm-sh/cpu_sh7723.h deleted file mode 100644 index 6dac6e9a01..0000000000 --- a/include/asm-sh/cpu_sh7723.h +++ /dev/null @@ -1,209 +0,0 @@ -/* - * (C) Copyright 2008 Renesas Solutions Corp. - * - * SH7723 Internal I/O register - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ASM_CPU_SH7723_H_ -#define _ASM_CPU_SH7723_H_ - -#define CACHE_OC_NUM_WAYS 4 -#define CCR_CACHE_INIT 0x0000090d - -/* EXP */ -#define TRA 0xFF000020 -#define EXPEVT 0xFF000024 -#define INTEVT 0xFF000028 - -/* MMU */ -#define PTEH 0xFF000000 -#define PTEL 0xFF000004 -#define TTB 0xFF000008 -#define TEA 0xFF00000C -#define MMUCR 0xFF000010 -#define PASCR 0xFF000070 -#define IRMCR 0xFF000078 - -/* CACHE */ -#define CCR 0xFF00001C -#define RAMCR 0xFF000074 - -/* INTC */ - -/* BSC */ -#define CMNCR 0xFEC10000 -#define CS0BCR 0xFEC10004 -#define CS2BCR 0xFEC10008 -#define CS4BCR 0xFEC10010 -#define CS5ABCR 0xFEC10014 -#define CS5BBCR 0xFEC10018 -#define CS6ABCR 0xFEC1001C -#define CS6BBCR 0xFEC10020 -#define CS0WCR 0xFEC10024 -#define CS2WCR 0xFEC10028 -#define CS4WCR 0xFEC10030 -#define CS5AWCR 0xFEC10034 -#define CS5BWCR 0xFEC10038 -#define CS6AWCR 0xFEC1003C -#define CS6BWCR 0xFEC10040 -#define RBWTCNT 0xFEC10054 - -/* SBSC */ -#define SBSC_SDCR 0xFE400008 -#define SBSC_SDWCR 0xFE40000C -#define SBSC_SDPCR 0xFE400010 -#define SBSC_RTCSR 0xFE400014 -#define SBSC_RTCNT 0xFE400018 -#define SBSC_RTCOR 0xFE40001C -#define SBSC_RFCR 0xFE400020 - -/* DMAC */ - -/* CPG */ -#define FRQCR 0xA4150000 -#define VCLKCR 0xA4150004 -#define SCLKACR 0xA4150008 -#define SCLKBCR 0xA415000C -#define IRDACLKCR 0xA4150018 -#define PLLCR 0xA4150024 -#define DLLFRQ 0xA4150050 - -/* LOW POWER MODE */ -#define STBCR 0xA4150020 -#define MSTPCR0 0xA4150030 -#define MSTPCR1 0xA4150034 -#define MSTPCR2 0xA4150038 - -/* RWDT */ -#define RWTCNT 0xA4520000 -#define RWTCSR 0xA4520004 -#define WTCNT RWTCNT - -/* TMU */ -#define TSTR 0xFFD80004 -#define TCOR0 0xFFD80008 -#define TCNT0 0xFFD8000C -#define TCR0 0xFFD80010 -#define TCOR1 0xFFD80014 -#define TCNT1 0xFFD80018 -#define TCR1 0xFFD8001C -#define TCOR2 0xFFD80020 -#define TCNT2 0xFFD80024 -#define TCR2 0xFFD80028 - -/* TPU */ - -/* CMT */ -#define CMSTR 0xA44A0000 -#define CMCSR 0xA44A0060 -#define CMCNT 0xA44A0064 -#define CMCOR 0xA44A0068 - -/* MSIOF */ - -/* SCIF */ -#define SCIF0_BASE 0xFFE00000 -#define SCIF1_BASE 0xFFE10000 -#define SCIF2_BASE 0xFFE20000 -#define SCIF3_BASE 0xa4e30000 -#define SCIF4_BASE 0xa4e40000 -#define SCIF5_BASE 0xa4e50000 - -/* RTC */ -/* IrDA */ -/* KEYSC */ -/* USB */ -/* IIC */ -/* FLCTL */ -/* VPU */ -/* VIO(CEU) */ -/* VIO(VEU) */ -/* VIO(BEU) */ -/* 2DG */ -/* LCDC */ -/* VOU */ -/* TSIF */ -/* SIU */ -/* ATAPI */ - -/* PFC */ -#define PACR 0xA4050100 -#define PBCR 0xA4050102 -#define PCCR 0xA4050104 -#define PDCR 0xA4050106 -#define PECR 0xA4050108 -#define PFCR 0xA405010A -#define PGCR 0xA405010C -#define PHCR 0xA405010E -#define PJCR 0xA4050110 -#define PKCR 0xA4050112 -#define PLCR 0xA4050114 -#define PMCR 0xA4050116 -#define PNCR 0xA4050118 -#define PQCR 0xA405011A -#define PRCR 0xA405011C -#define PSCR 0xA405011E -#define PTCR 0xA4050140 -#define PUCR 0xA4050142 -#define PVCR 0xA4050144 -#define PWCR 0xA4050146 -#define PXCR 0xA4050148 -#define PYCR 0xA405014A -#define PZCR 0xA405014C -#define PSELA 0xA405014E -#define PSELB 0xA4050150 -#define PSELC 0xA4050152 -#define PSELD 0xA4050154 -#define HIZCRA 0xA4050158 -#define HIZCRB 0xA405015A -#define HIZCRC 0xA405015C -#define HIZCRD 0xA405015E -#define MSELCRA 0xA4050180 -#define MSELCRB 0xA4050182 -#define PULCR 0xA4050184 -#define DRVCRA 0xA405018A -#define DRVCRB 0xA405018C - -/* I/O Port */ -#define PADR 0xA4050120 -#define PBDR 0xA4050122 -#define PCDR 0xA4050124 -#define PDDR 0xA4050126 -#define PEDR 0xA4050128 -#define PFDR 0xA405012A -#define PGDR 0xA405012C -#define PHDR 0xA405012E -#define PJDR 0xA4050130 -#define PKDR 0xA4050132 -#define PLDR 0xA4050134 -#define PMDR 0xA4050136 -#define PNDR 0xA4050138 -#define PQDR 0xA405013A -#define PRDR 0xA405013C -#define PSDR 0xA405013E -#define PTDR 0xA4050160 -#define PUDR 0xA4050162 -#define PVDR 0xA4050164 -#define PWDR 0xA4050166 -#define PYDR 0xA4050168 -#define PZDR 0xA405016A - -/* UBC */ -/* H-UDI */ - -#endif /* _ASM_CPU_SH7723_H_ */ diff --git a/include/asm-sh/cpu_sh7750.h b/include/asm-sh/cpu_sh7750.h deleted file mode 100644 index 4e43a465e6..0000000000 --- a/include/asm-sh/cpu_sh7750.h +++ /dev/null @@ -1,196 +0,0 @@ -/* - * (C) Copyright 2007 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * - * SH7750/SH7750S/SH7750R/SH7751/SH7751R - * Internal I/O register - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef _ASM_CPU_SH7750_H_ -#define _ASM_CPU_SH7750_H_ - -#ifdef CONFIG_CPU_TYPE_R -#define CACHE_OC_NUM_WAYS 2 -#define CCR_CACHE_INIT 0x8000090D /* EMODE,ICI,ICE(16k),OCI,P1-wb,OCE(32k) */ -#else -#define CACHE_OC_NUM_WAYS 1 -#define CCR_CACHE_INIT 0x0000090B -#endif - -/* OCN */ -#define PTEH 0xFF000000 -#define PTEL 0xFF000004 -#define TTB 0xFF000008 -#define TEA 0xFF00000C -#define MMUCR 0xFF000010 -#define BASRA 0xFF000014 -#define BASRB 0xFF000018 -#define CCR 0xFF00001C -#define TRA 0xFF000020 -#define EXPEVT 0xFF000024 -#define INTEVT 0xFF000028 -#define PTEA 0xFF000034 -#define QACR0 0xFF000038 -#define QACR1 0xFF00003C - -/* UBC */ -#define BARA 0xFF200000 -#define BAMRA 0xFF200004 -#define BBRA 0xFF200008 -#define BARB 0xFF20000C -#define BAMRB 0xFF200010 -#define BBRB 0xFF200014 -#define BDRB 0xFF200018 -#define BDMRB 0xFF20001C -#define BRCR 0xFF200020 - -/* BSC */ -#define BCR1 0xFF800000 -#define BCR2 0xFF800004 -#define BCR3 0xFF800050 -#define BCR4 0xFE0A00F0 -#define WCR1 0xFF800008 -#define WCR2 0xFF80000C -#define WCR3 0xFF800010 -#define MCR 0xFF800014 -#define PCR 0xFF800018 -#define RTCSR 0xFF80001C -#define RTCNT 0xFF800020 -#define RTCOR 0xFF800024 -#define RFCR 0xFF800028 -#define PCTRA 0xFF80002C -#define PDTRA 0xFF800030 -#define PCTRB 0xFF800040 -#define PDTRB 0xFF800044 -#define GPIOIC 0xFF800048 - -/* DMAC */ -#define SAR0 0xFFA00000 -#define DAR0 0xFFA00004 -#define DMATCR0 0xFFA00008 -#define CHCR0 0xFFA0000C -#define SAR1 0xFFA00010 -#define DAR1 0xFFA00014 -#define DMATCR1 0xFFA00018 -#define CHCR1 0xFFA0001C -#define SAR2 0xFFA00020 -#define DAR2 0xFFA00024 -#define DMATCR2 0xFFA00028 -#define CHCR2 0xFFA0002C -#define SAR3 0xFFA00030 -#define DAR3 0xFFA00034 -#define DMATCR3 0xFFA00038 -#define CHCR3 0xFFA0003C -#define DMAOR 0xFFA00040 -#define SAR4 0xFFA00050 -#define DAR4 0xFFA00054 -#define DMATCR4 0xFFA00058 - -/* CPG */ -#define FRQCR 0xFFC00000 -#define STBCR 0xFFC00004 -#define WTCNT 0xFFC00008 -#define WTCSR 0xFFC0000C -#define STBCR2 0xFFC00010 - -/* RTC */ -#define R64CNT 0xFFC80000 -#define RSECCNT 0xFFC80004 -#define RMINCNT 0xFFC80008 -#define RHRCNT 0xFFC8000C -#define RWKCNT 0xFFC80010 -#define RDAYCNT 0xFFC80014 -#define RMONCNT 0xFFC80018 -#define RYRCNT 0xFFC8001C -#define RSECAR 0xFFC80020 -#define RMINAR 0xFFC80024 -#define RHRAR 0xFFC80028 -#define RWKAR 0xFFC8002C -#define RDAYAR 0xFFC80030 -#define RMONAR 0xFFC80034 -#define RCR1 0xFFC80038 -#define RCR2 0xFFC8003C -#define RCR3 0xFFC80050 -#define RYRAR 0xFFC80054 - -/* ICR */ -#define ICR 0xFFD00000 -#define IPRA 0xFFD00004 -#define IPRB 0xFFD00008 -#define IPRC 0xFFD0000C -#define IPRD 0xFFD00010 -#define INTPRI 0xFE080000 -#define INTREQ 0xFE080020 -#define INTMSK 0xFE080040 -#define INTMSKCL 0xFE080060 - -/* CPG */ -#define CLKSTP 0xFE0A0000 -#define CLKSTPCLR 0xFE0A0008 - -/* TMU */ -#define TSTR2 0xFE100004 -#define TCOR3 0xFE100008 -#define TCNT3 0xFE10000C -#define TCR3 0xFE100010 -#define TCOR4 0xFE100014 -#define TCNT4 0xFE100018 -#define TCR4 0xFE10001C -#define TOCR 0xFFD80000 -#define TSTR0 0xFFD80004 -#define TCOR0 0xFFD80008 -#define TCNT0 0xFFD8000C -#define TCR0 0xFFD80010 -#define TCOR1 0xFFD80014 -#define TCNT1 0xFFD80018 -#define TCR1 0xFFD8001C -#define TCOR2 0xFFD80020 -#define TCNT2 0xFFD80024 -#define TCR2 0xFFD80028 -#define TCPR2 0xFFD8002C -#define TSTR TSTR0 - -/* SCI */ -#define SCSMR1 0xFFE00000 -#define SCBRR1 0xFFE00004 -#define SCSCR1 0xFFE00008 -#define SCTDR1 0xFFE0000C -#define SCSSR1 0xFFE00010 -#define SCRDR1 0xFFE00014 -#define SCSCMR1 0xFFE00018 -#define SCSPTR1 0xFFE0001C -#define SCF0_BASE SCSMR1 - -/* SCIF */ -#define SCSMR2 0xFFE80000 -#define SCBRR2 0xFFE80004 -#define SCSCR2 0xFFE80008 -#define SCFTDR2 0xFFE8000C -#define SCFSR2 0xFFE80010 -#define SCFRDR2 0xFFE80014 -#define SCFCR2 0xFFE80018 -#define SCFDR2 0xFFE8001C -#define SCSPTR2 0xFFE80020 -#define SCLSR2 0xFFE80024 -#define SCIF1_BASE SCSMR2 - -/* H-UDI */ -#define SDIR 0xFFF00000 -#define SDDR 0xFFF00008 -#define SDINT 0xFFF00014 - -#endif /* _ASM_CPU_SH7750_H_ */ diff --git a/include/asm-sh/cpu_sh7763.h b/include/asm-sh/cpu_sh7763.h deleted file mode 100644 index 78b456b4b2..0000000000 --- a/include/asm-sh/cpu_sh7763.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (C) 2007,2008 Nobuhiro Iwamatsu - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _ASM_CPU_SH7763_H_ -#define _ASM_CPU_SH7763_H_ - -/* CACHE */ -#define CACHE_OC_NUM_WAYS 1 -#define CCR 0xFF00001C -#define CCR_CACHE_INIT 0x0000090b - -/* SCIF */ -/* SCIF0 */ -#define SCIF0_BASE SCSMR0 -#define SCSMR0 0xFFE00000 - -/* SCIF1 */ -#define SCIF1_BASE SCSMR1 -#define SCSMR1 0xFFE08000 - -/* SCIF2 */ -#define SCIF2_BASE SCSMR2 -#define SCSMR2 0xFFE10000 - -/* Watchdog Timer */ -#define WTCNT WDTST -#define WDTST 0xFFCC0000 - -/* TMU */ -#define TSTR 0xFFD80004 -#define TCOR0 0xFFD80008 -#define TCNT0 0xFFD8000C -#define TCR0 0xFFD80010 - -#endif /* _ASM_CPU_SH7763_H_ */ diff --git a/include/asm-sh/cpu_sh7780.h b/include/asm-sh/cpu_sh7780.h deleted file mode 100644 index d4f824e715..0000000000 --- a/include/asm-sh/cpu_sh7780.h +++ /dev/null @@ -1,503 +0,0 @@ -#ifndef _ASM_CPU_SH7780_H_ -#define _ASM_CPU_SH7780_H_ - -/* - * Copyright (c) 2007,2008 Nobuhiro Iwamatsu - * Copyright (c) 2008 Yusuke Goda <goda.yusuke@renesas.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#define CACHE_OC_NUM_WAYS 1 -#define CCR_CACHE_INIT 0x0000090b - -/* Exceptions */ -#define TRA 0xFF000020 -#define EXPEVT 0xFF000024 -#define INTEVT 0xFF000028 - -/* Memory Management Unit */ -#define PTEH 0xFF000000 -#define PTEL 0xFF000004 -#define TTB 0xFF000008 -#define TEA 0xFF00000C -#define MMUCR 0xFF000010 -#define PASCR 0xFF000070 -#define IRMCR 0xFF000078 - -/* Cache Controller */ -#define CCR 0xFF00001C -#define QACR0 0xFF000038 -#define QACR1 0xFF00003C -#define RAMCR 0xFF000074 - -/* L Memory */ -#define RAMCR 0xFF000074 -#define LSA0 0xFF000050 -#define LSA1 0xFF000054 -#define LDA0 0xFF000058 -#define LDA1 0xFF00005C - -/* Interrupt Controller */ -#define ICR0 0xFFD00000 -#define ICR1 0xFFD0001C -#define INTPRI 0xFFD00010 -#define INTREQ 0xFFD00024 -#define INTMSK0 0xFFD00044 -#define INTMSK1 0xFFD00048 -#define INTMSK2 0xFFD40080 -#define INTMSKCLR0 0xFFD00064 -#define INTMSKCLR1 0xFFD00068 -#define INTMSKCLR2 0xFFD40084 -#define NMIFCR 0xFFD000C0 -#define USERIMASK 0xFFD30000 -#define INT2PRI0 0xFFD40000 -#define INT2PRI1 0xFFD40004 -#define INT2PRI2 0xFFD40008 -#define INT2PRI3 0xFFD4000C -#define INT2PRI4 0xFFD40010 -#define INT2PRI5 0xFFD40014 -#define INT2PRI6 0xFFD40018 -#define INT2PRI7 0xFFD4001C -#define INT2A0 0xFFD40030 -#define INT2A1 0xFFD40034 -#define INT2MSKR 0xFFD40038 -#define INT2MSKCR 0xFFD4003C -#define INT2B0 0xFFD40040 -#define INT2B1 0xFFD40044 -#define INT2B2 0xFFD40048 -#define INT2B3 0xFFD4004C -#define INT2B4 0xFFD40050 -#define INT2B5 0xFFD40054 -#define INT2B6 0xFFD40058 -#define INT2B7 0xFFD4005C -#define INT2GPIC 0xFFD40090 - -/* local Bus State Controller */ -#define MMSELR 0xFF400020 -#define BCR 0xFF801000 -#define CS0BCR 0xFF802000 -#define CS1BCR 0xFF802010 -#define CS2BCR 0xFF802020 -#define CS4BCR 0xFF802040 -#define CS5BCR 0xFF802050 -#define CS6BCR 0xFF802060 -#define CS0WCR 0xFF802008 -#define CS1WCR 0xFF802018 -#define CS2WCR 0xFF802028 -#define CS4WCR 0xFF802048 -#define CS5WCR 0xFF802058 -#define CS6WCR 0xFF802068 -#define CS5PCR 0xFF802070 -#define CS6PCR 0xFF802080 - -/* DDR-SDRAM I/F */ -#define MIM_1 0xFE800008 -#define MIM_2 0xFE80000C -#define SCR_1 0xFE800010 -#define SCR_2 0xFE800014 -#define STR_1 0xFE800018 -#define STR_2 0xFE80001C -#define SDR_1 0xFE800030 -#define SDR_2 0xFE800034 -#define DBK_1 0xFE800400 -#define DBK_2 0xFE800404 - -/* PCI Controller */ -#define SH7780_PCIECR 0xFE000008 -#define SH7780_PCIVID 0xFE040000 -#define SH7780_PCIDID 0xFE040002 -#define SH7780_PCICMD 0xFE040004 -#define SH7780_PCISTATUS 0xFE040006 -#define SH7780_PCIRID 0xFE040008 -#define SH7780_PCIPIF 0xFE040009 -#define SH7780_PCISUB 0xFE04000A -#define SH7780_PCIBCC 0xFE04000B -#define SH7780_PCICLS 0xFE04000C -#define SH7780_PCILTM 0xFE04000D -#define SH7780_PCIHDR 0xFE04000E -#define SH7780_PCIBIST 0xFE04000F -#define SH7780_PCIIBAR 0xFE040010 -#define SH7780_PCIMBAR0 0xFE040014 -#define SH7780_PCIMBAR1 0xFE040018 -#define SH7780_PCISVID 0xFE04002C -#define SH7780_PCISID 0xFE04002E -#define SH7780_PCICP 0xFE040034 -#define SH7780_PCIINTLINE 0xFE04003C -#define SH7780_PCIINTPIN 0xFE04003D -#define SH7780_PCIMINGNT 0xFE04003E -#define SH7780_PCIMAXLAT 0xFE04003F -#define SH7780_PCICID 0xFE040040 -#define SH7780_PCINIP 0xFE040041 -#define SH7780_PCIPMC 0xFE040042 -#define SH7780_PCIPMCSR 0xFE040044 -#define SH7780_PCIPMCSRBSE 0xFE040046 -#define SH7780_PCI_CDD 0xFE040047 -#define SH7780_PCICR 0xFE040100 -#define SH7780_PCILSR0 0xFE040104 -#define SH7780_PCILSR1 0xFE040108 -#define SH7780_PCILAR0 0xFE04010C -#define SH7780_PCILAR1 0xFE040110 -#define SH7780_PCIIR 0xFE040114 -#define SH7780_PCIIMR 0xFE040118 -#define SH7780_PCIAIR 0xFE04011C -#define SH7780_PCICIR 0xFE040120 -#define SH7780_PCIAINT 0xFE040130 -#define SH7780_PCIAINTM 0xFE040134 -#define SH7780_PCIBMIR 0xFE040138 -#define SH7780_PCIPAR 0xFE0401C0 -#define SH7780_PCIPINT 0xFE0401CC -#define SH7780_PCIPINTM 0xFE0401D0 -#define SH7780_PCIMBR0 0xFE0401E0 -#define SH7780_PCIMBMR0 0xFE0401E4 -#define SH7780_PCIMBR1 0xFE0401E8 -#define SH7780_PCIMBMR1 0xFE0401EC -#define SH7780_PCIMBR2 0xFE0401F0 -#define SH7780_PCIMBMR2 0xFE0401F4 -#define SH7780_PCIIOBR 0xFE0401F8 -#define SH7780_PCIIOBMR 0xFE0401FC -#define SH7780_PCICSCR0 0xFE040210 -#define SH7780_PCICSCR1 0xFE040214 -#define SH7780_PCICSAR0 0xFE040218 -#define SH7780_PCICSAR1 0xFE04021C -#define SH7780_PCIPDR 0xFE040220 - -/* DMAC */ -#define DMAC_SAR0 0xFC808020 -#define DMAC_DAR0 0xFC808024 -#define DMAC_TCR0 0xFC808028 -#define DMAC_CHCR0 0xFC80802C -#define DMAC_SAR1 0xFC808030 -#define DMAC_DAR1 0xFC808034 -#define DMAC_TCR1 0xFC808038 -#define DMAC_CHCR1 0xFC80803C -#define DMAC_SAR2 0xFC808040 -#define DMAC_DAR2 0xFC808044 -#define DMAC_TCR2 0xFC808048 -#define DMAC_CHCR2 0xFC80804C -#define DMAC_SAR3 0xFC808050 -#define DMAC_DAR3 0xFC808054 -#define DMAC_TCR3 0xFC808058 -#define DMAC_CHCR3 0xFC80805C -#define DMAC_DMAOR0 0xFC808060 -#define DMAC_SAR4 0xFC808070 -#define DMAC_DAR4 0xFC808074 -#define DMAC_TCR4 0xFC808078 -#define DMAC_CHCR4 0xFC80807C -#define DMAC_SAR5 0xFC808080 -#define DMAC_DAR5 0xFC808084 -#define DMAC_TCR5 0xFC808088 -#define DMAC_CHCR5 0xFC80808C -#define DMAC_SARB0 0xFC808120 -#define DMAC_DARB0 0xFC808124 -#define DMAC_TCRB0 0xFC808128 -#define DMAC_SARB1 0xFC808130 -#define DMAC_DARB1 0xFC808134 -#define DMAC_TCRB1 0xFC808138 -#define DMAC_SARB2 0xFC808140 -#define DMAC_DARB2 0xFC808144 -#define DMAC_TCRB2 0xFC808148 -#define DMAC_SARB3 0xFC808150 -#define DMAC_DARB3 0xFC808154 -#define DMAC_TCRB3 0xFC808158 -#define DMAC_DMARS0 0xFC809000 -#define DMAC_DMARS1 0xFC809004 -#define DMAC_DMARS2 0xFC809008 -#define DMAC_SAR6 0xFC818020 -#define DMAC_DAR6 0xFC818024 -#define DMAC_TCR6 0xFC818028 -#define DMAC_CHCR6 0xFC81802C -#define DMAC_SAR7 0xFC818030 -#define DMAC_DAR7 0xFC818034 -#define DMAC_TCR7 0xFC818038 -#define DMAC_CHCR7 0xFC81803C -#define DMAC_SAR8 0xFC818040 -#define DMAC_DAR8 0xFC818044 -#define DMAC_TCR8 0xFC818048 -#define DMAC_CHCR8 0xFC81804C -#define DMAC_SAR9 0xFC818050 -#define DMAC_DAR9 0xFC818054 -#define DMAC_TCR9 0xFC818058 -#define DMAC_CHCR9 0xFC81805C -#define DMAC_DMAOR1 0xFC818060 -#define DMAC_SAR10 0xFC818070 -#define DMAC_DAR10 0xFC818074 -#define DMAC_TCR10 0xFC818078 -#define DMAC_CHCR10 0xFC81807C -#define DMAC_SAR11 0xFC818080 -#define DMAC_DAR11 0xFC818084 -#define DMAC_TCR11 0xFC818088 -#define DMAC_CHCR11 0xFC81808C -#define DMAC_SARB6 0xFC818120 -#define DMAC_DARB6 0xFC818124 -#define DMAC_TCRB6 0xFC818128 -#define DMAC_SARB7 0xFC818130 -#define DMAC_DARB7 0xFC818134 -#define DMAC_TCRB7 0xFC818138 -#define DMAC_SARB8 0xFC818140 -#define DMAC_DARB8 0xFC818144 -#define DMAC_TCRB8 0xFC818148 -#define DMAC_SARB9 0xFC818150 -#define DMAC_DARB9 0xFC818154 -#define DMAC_TCRB9 0xFC818158 - -/* Clock Pulse Generator */ -#define FRQCR 0xFFC80000 -#define PLLCR 0xFFC80024 -#define MSTPCR 0xFFC80030 - -/* Watchdog Timer and Reset */ -#define WTCNT WDTCNT -#define WDTST 0xFFCC0000 -#define WDTCSR 0xFFCC0004 -#define WDTBST 0xFFCC0008 -#define WDTCNT 0xFFCC0010 -#define WDTBCNT 0xFFCC0018 - -/* System Control */ -#define MSTPCR 0xFFC80030 - -/* Timer Unit */ -#define TSTR TSTR0 -#define TOCR 0xFFD80000 -#define TSTR0 0xFFD80004 -#define TCOR0 0xFFD80008 -#define TCNT0 0xFFD8000C -#define TCR0 0xFFD80010 -#define TCOR1 0xFFD80014 -#define TCNT1 0xFFD80018 -#define TCR1 0xFFD8001C -#define TCOR2 0xFFD80020 -#define TCNT2 0xFFD80024 -#define TCR2 0xFFD80028 -#define TCPR2 0xFFD8002C -#define TSTR1 0xFFDC0004 -#define TCOR3 0xFFDC0008 -#define TCNT3 0xFFDC000C -#define TCR3 0xFFDC0010 -#define TCOR4 0xFFDC0014 -#define TCNT4 0xFFDC0018 -#define TCR4 0xFFDC001C -#define TCOR5 0xFFDC0020 -#define TCNT5 0xFFDC0024 -#define TCR5 0xFFDC0028 - -/* Timer/Counter */ -#define CMTCFG 0xFFE30000 -#define CMTFRT 0xFFE30004 -#define CMTCTL 0xFFE30008 -#define CMTIRQS 0xFFE3000C -#define CMTCH0T 0xFFE30010 -#define CMTCH0ST 0xFFE30020 -#define CMTCH0C 0xFFE30030 -#define CMTCH1T 0xFFE30014 -#define CMTCH1ST 0xFFE30024 -#define CMTCH1C 0xFFE30034 -#define CMTCH2T 0xFFE30018 -#define CMTCH2C 0xFFE30038 -#define CMTCH3T 0xFFE3001C -#define CMTCH3C 0xFFE3003C - -/* Realtime Clock */ -#define R64CNT 0xFFE80000 -#define RSECCNT 0xFFE80004 -#define RMINCNT 0xFFE80008 -#define RHRCNT 0xFFE8000C -#define RWKCNT 0xFFE80010 -#define RDAYCNT 0xFFE80014 -#define RMONCNT 0xFFE80018 -#define RYRCNT 0xFFE8001C -#define RSECAR 0xFFE80020 -#define RMINAR 0xFFE80024 -#define RHRAR 0xFFE80028 -#define RWKAR 0xFFE8002C -#define RDAYAR 0xFFE80030 -#define RMONAR 0xFFE80034 -#define RCR1 0xFFE80038 -#define RCR2 0xFFE8003C -#define RCR3 0xFFE80050 -#define RYRAR 0xFFE80054 - -/* Serial Communication Interface with FIFO */ -#define SCIF0_BASE SCSMR0 -#define SCSMR0 0xFFE00000 -#define SCBRR0 0xFFE00004 -#define SCSCR0 0xFFE00008 -#define SCFSR0 0xFFE00010 -#define SCFCR0 0xFFE00018 -#define SCTFDR0 0xFFE0001C -#define SCRFDR0 0xFFE00020 -#define SCSPTR0 0xFFE00024 -#define SCLSR0 0xFFE00028 -#define SCRER0 0xFFE0002C -#define SCSMR1 0xFFE10000 -#define SCBRR1 0xFFE10004 -#define SCSCR1 0xFFE10008 -#define SCFSR1 0xFFE10010 -#define SCFCR1 0xFFE10018 -#define SCTFDR1 0xFFE1001C -#define SCRFDR1 0xFFE10020 -#define SCSPTR1 0xFFE10024 -#define SCLSR1 0xFFE10028 -#define SCRER1 0xFFE1002C - -/* Serial I/O with FIFO */ -#define SIMDR 0xFFE20000 -#define SISCR 0xFFE20002 -#define SITDAR 0xFFE20004 -#define SIRDAR 0xFFE20006 -#define SICDAR 0xFFE20008 -#define SICTR 0xFFE2000C -#define SIFCTR 0xFFE20010 -#define SISTR 0xFFE20014 -#define SIIER 0xFFE20016 -#define SITCR 0xFFE20028 -#define SIRCR 0xFFE2002C -#define SPICR 0xFFE20030 - -/* Serial Protocol Interface */ -#define SPCR 0xFFE50000 -#define SPSR 0xFFE50004 -#define SPSCR 0xFFE50008 -#define SPTBR 0xFFE5000C -#define SPRBR 0xFFE50010 - -/* Multimedia Card Interface */ -#define CMDR0 0xFFE60000 -#define CMDR1 0xFFE60001 -#define CMDR2 0xFFE60002 -#define CMDR3 0xFFE60003 -#define CMDR4 0xFFE60004 -#define CMDR5 0xFFE60005 -#define CMDSTRT 0xFFE60006 -#define OPCR 0xFFE6000A -#define CSTR 0xFFE6000B -#define INTCR0 0xFFE6000C -#define INTCR1 0xFFE6000D -#define INTSTR0 0xFFE6000E -#define INTSTR1 0xFFE6000F -#define CLKON 0xFFE60010 -#define CTOCR 0xFFE60011 -#define TBCR 0xFFE60014 -#define MODER 0xFFE60016 -#define CMDTYR 0xFFE60018 -#define RSPTYR 0xFFE60019 -#define TBNCR 0xFFE6001A -#define RSPR0 0xFFE60020 -#define RSPR1 0xFFE60021 -#define RSPR2 0xFFE60022 -#define RSPR3 0xFFE60023 -#define RSPR4 0xFFE60024 -#define RSPR5 0xFFE60025 -#define RSPR6 0xFFE60026 -#define RSPR7 0xFFE60027 -#define RSPR8 0xFFE60028 -#define RSPR9 0xFFE60029 -#define RSPR10 0xFFE6002A -#define RSPR11 0xFFE6002B -#define RSPR12 0xFFE6002C -#define RSPR13 0xFFE6002D -#define RSPR14 0xFFE6002E -#define RSPR15 0xFFE6002F -#define RSPR16 0xFFE60030 -#define RSPRD 0xFFE60031 -#define DTOUTR 0xFFE60032 -#define DR 0xFFE60040 -#define DMACR 0xFFE60044 -#define INTCR2 0xFFE60046 -#define INTSTR2 0xFFE60048 - -/* Audio Codec Interface */ -#define HACCR 0xFFE40008 -#define HACCSAR 0xFFE40020 -#define HACCSDR 0xFFE40024 -#define HACPCML 0xFFE40028 -#define HACPCMR 0xFFE4002C -#define HACTIER 0xFFE40050 -#define HACTSR 0xFFE40054 -#define HACRIER 0xFFE40058 -#define HACRSR 0xFFE4005C -#define HACACR 0xFFE40060 - -/* Serial Sound Interface */ -#define SSICR 0xFFE70000 -#define SSISR 0xFFE70004 -#define SSITDR 0xFFE70008 -#define SSIRDR 0xFFE7000C - -/* Flash memory Controller */ -#define FLCMNCR 0xFFE90000 -#define FLCMDCR 0xFFE90004 -#define FLCMCDR 0xFFE90008 -#define FLADR 0xFFE9000C -#define FLDATAR 0xFFE90010 -#define FLDTCNTR 0xFFE90014 -#define FLINTDMACR 0xFFE90018 -#define FLBSYTMR 0xFFE9001C -#define FLBSYCNT 0xFFE90020 -#define FLTRCR 0xFFE9002C - -/* General Purpose I/O */ -#define PACR 0xFFEA0000 -#define PBCR 0xFFEA0002 -#define PCCR 0xFFEA0004 -#define PDCR 0xFFEA0006 -#define PECR 0xFFEA0008 -#define PFCR 0xFFEA000A -#define PGCR 0xFFEA000C -#define PHCR 0xFFEA000E -#define PJCR 0xFFEA0010 -#define PKCR 0xFFEA0012 -#define PLCR 0xFFEA0014 -#define PMCR 0xFFEA0016 -#define PADR 0xFFEA0020 -#define PBDR 0xFFEA0022 -#define PCDR 0xFFEA0024 -#define PDDR 0xFFEA0026 -#define PEDR 0xFFEA0028 -#define PFDR 0xFFEA002A -#define PGDR 0xFFEA002C -#define PHDR 0xFFEA002E -#define PJDR 0xFFEA0030 -#define PKDR 0xFFEA0032 -#define PLDR 0xFFEA0034 -#define PMDR 0xFFEA0036 -#define PEPUPR 0xFFEA0048 -#define PHPUPR 0xFFEA004E -#define PJPUPR 0xFFEA0050 -#define PKPUPR 0xFFEA0052 -#define PMPUPR 0xFFEA0056 -#define PPUPR1 0xFFEA0060 -#define PPUPR2 0xFFEA0062 -#define PMSELR 0xFFEA0080 - -/* User Break Controller */ -#define CBR0 0xFF200000 -#define CRR0 0xFF200004 -#define CAR0 0xFF200008 -#define CAMR0 0xFF20000C -#define CBR1 0xFF200020 -#define CRR1 0xFF200024 -#define CAR1 0xFF200028 -#define CAMR1 0xFF20002C -#define CDR1 0xFF200030 -#define CDMR1 0xFF200034 -#define CETR1 0xFF200038 -#define CCMFR 0xFF200600 -#define CBCR 0xFF200620 - -#endif /* _ASM_CPU_SH7780_H_ */ diff --git a/include/asm-sh/cpu_sh7785.h b/include/asm-sh/cpu_sh7785.h deleted file mode 100644 index 4a4dfc9042..0000000000 --- a/include/asm-sh/cpu_sh7785.h +++ /dev/null @@ -1,156 +0,0 @@ -#ifndef _ASM_CPU_SH7785_H_ -#define _ASM_CPU_SH7785_H_ - -/* - * Copyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * Copyright (c) 2008 Yusuke Goda <goda.yusuke@renesas.com> - * Copyright (c) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - */ - -#define CACHE_OC_NUM_WAYS 1 -#define CCR_CACHE_INIT 0x0000090b - -/* Exceptions */ -#define TRA 0xFF000020 -#define EXPEVT 0xFF000024 -#define INTEVT 0xFF000028 - -/* Cache Controller */ -#define CCR 0xFF00001C -#define QACR0 0xFF000038 -#define QACR1 0xFF00003C -#define RAMCR 0xFF000074 - -/* Watchdog Timer and Reset */ -#define WTCNT WDTCNT -#define WDTST 0xFFCC0000 -#define WDTCSR 0xFFCC0004 -#define WDTBST 0xFFCC0008 -#define WDTCNT 0xFFCC0010 -#define WDTBCNT 0xFFCC0018 - -/* Timer Unit */ -#define TSTR TSTR0 -#define TOCR 0xFFD80000 -#define TSTR0 0xFFD80004 -#define TCOR0 0xFFD80008 -#define TCNT0 0xFFD8000C -#define TCR0 0xFFD80010 -#define TCOR1 0xFFD80014 -#define TCNT1 0xFFD80018 -#define TCR1 0xFFD8001C -#define TCOR2 0xFFD80020 -#define TCNT2 0xFFD80024 -#define TCR2 0xFFD80028 -#define TCPR2 0xFFD8002C -#define TSTR1 0xFFDC0004 -#define TCOR3 0xFFDC0008 -#define TCNT3 0xFFDC000C -#define TCR3 0xFFDC0010 -#define TCOR4 0xFFDC0014 -#define TCNT4 0xFFDC0018 -#define TCR4 0xFFDC001C -#define TCOR5 0xFFDC0020 -#define TCNT5 0xFFDC0024 -#define TCR5 0xFFDC0028 - -/* Serial Communication Interface with FIFO */ -#define SCIF1_BASE 0xffeb0000 - -/* LBSC */ -#define MMSELR 0xfc400020 -#define LBSC_BASE 0xff800000 -#define BCR (LBSC_BASE + 0x1000) -#define CS0BCR (LBSC_BASE + 0x2000) -#define CS1BCR (LBSC_BASE + 0x2010) -#define CS2BCR (LBSC_BASE + 0x2020) -#define CS3BCR (LBSC_BASE + 0x2030) -#define CS4BCR (LBSC_BASE + 0x2040) -#define CS5BCR (LBSC_BASE + 0x2050) -#define CS6BCR (LBSC_BASE + 0x2060) -#define CS0WCR (LBSC_BASE + 0x2008) -#define CS1WCR (LBSC_BASE + 0x2018) -#define CS2WCR (LBSC_BASE + 0x2028) -#define CS3WCR (LBSC_BASE + 0x2038) -#define CS4WCR (LBSC_BASE + 0x2048) -#define CS5WCR (LBSC_BASE + 0x2058) -#define CS6WCR (LBSC_BASE + 0x2068) -#define CS5PCR (LBSC_BASE + 0x2070) -#define CS6PCR (LBSC_BASE + 0x2080) - -/* PCI Controller */ -#define SH7780_PCIECR 0xFE000008 -#define SH7780_PCIVID 0xFE040000 -#define SH7780_PCIDID 0xFE040002 -#define SH7780_PCICMD 0xFE040004 -#define SH7780_PCISTATUS 0xFE040006 -#define SH7780_PCIRID 0xFE040008 -#define SH7780_PCIPIF 0xFE040009 -#define SH7780_PCISUB 0xFE04000A -#define SH7780_PCIBCC 0xFE04000B -#define SH7780_PCICLS 0xFE04000C -#define SH7780_PCILTM 0xFE04000D -#define SH7780_PCIHDR 0xFE04000E -#define SH7780_PCIBIST 0xFE04000F -#define SH7780_PCIIBAR 0xFE040010 -#define SH7780_PCIMBAR0 0xFE040014 -#define SH7780_PCIMBAR1 0xFE040018 -#define SH7780_PCISVID 0xFE04002C -#define SH7780_PCISID 0xFE04002E -#define SH7780_PCICP 0xFE040034 -#define SH7780_PCIINTLINE 0xFE04003C -#define SH7780_PCIINTPIN 0xFE04003D -#define SH7780_PCIMINGNT 0xFE04003E -#define SH7780_PCIMAXLAT 0xFE04003F -#define SH7780_PCICID 0xFE040040 -#define SH7780_PCINIP 0xFE040041 -#define SH7780_PCIPMC 0xFE040042 -#define SH7780_PCIPMCSR 0xFE040044 -#define SH7780_PCIPMCSRBSE 0xFE040046 -#define SH7780_PCI_CDD 0xFE040047 -#define SH7780_PCICR 0xFE040100 -#define SH7780_PCILSR0 0xFE040104 -#define SH7780_PCILSR1 0xFE040108 -#define SH7780_PCILAR0 0xFE04010C -#define SH7780_PCILAR1 0xFE040110 -#define SH7780_PCIIR 0xFE040114 -#define SH7780_PCIIMR 0xFE040118 -#define SH7780_PCIAIR 0xFE04011C -#define SH7780_PCICIR 0xFE040120 -#define SH7780_PCIAINT 0xFE040130 -#define SH7780_PCIAINTM 0xFE040134 -#define SH7780_PCIBMIR 0xFE040138 -#define SH7780_PCIPAR 0xFE0401C0 -#define SH7780_PCIPINT 0xFE0401CC -#define SH7780_PCIPINTM 0xFE0401D0 -#define SH7780_PCIMBR0 0xFE0401E0 -#define SH7780_PCIMBMR0 0xFE0401E4 -#define SH7780_PCIMBR1 0xFE0401E8 -#define SH7780_PCIMBMR1 0xFE0401EC -#define SH7780_PCIMBR2 0xFE0401F0 -#define SH7780_PCIMBMR2 0xFE0401F4 -#define SH7780_PCIIOBR 0xFE0401F8 -#define SH7780_PCIIOBMR 0xFE0401FC -#define SH7780_PCICSCR0 0xFE040210 -#define SH7780_PCICSCR1 0xFE040214 -#define SH7780_PCICSAR0 0xFE040218 -#define SH7780_PCICSAR1 0xFE04021C -#define SH7780_PCIPDR 0xFE040220 - -#endif /* _ASM_CPU_SH7780_H_ */ diff --git a/include/asm-sh/errno.h b/include/asm-sh/errno.h deleted file mode 100644 index 4c82b503d9..0000000000 --- a/include/asm-sh/errno.h +++ /dev/null @@ -1 +0,0 @@ -#include <asm-generic/errno.h> diff --git a/include/asm-sh/global_data.h b/include/asm-sh/global_data.h deleted file mode 100644 index c12b8558ec..0000000000 --- a/include/asm-sh/global_data.h +++ /dev/null @@ -1,53 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2007 - * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __ASM_SH_GLOBALDATA_H_ -#define __ASM_SH_GLOBALDATA_H_ - -typedef struct global_data -{ - bd_t *bd; - unsigned long flags; - unsigned long baudrate; - unsigned long cpu_clk; /* CPU clock in Hz! */ - unsigned long have_console; /* serial_init() was called */ - phys_size_t ram_size; /* RAM size */ - unsigned long env_addr; /* Address of Environment struct */ - unsigned long env_valid; /* Checksum of Environment valid */ - void **jt; /* Standalone app jump table */ -}gd_t; - -#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ -#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ -#define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ -#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ - -#define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("r13") - -#endif /* __ASM_SH_GLOBALDATA_H_ */ diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h deleted file mode 100644 index ca598a60f3..0000000000 --- a/include/asm-sh/io.h +++ /dev/null @@ -1,270 +0,0 @@ -/* - * linux/include/asm-sh/io.h - * - * Copyright (C) 1996-2000 Russell King - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * Modifications: - * 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both - * constant addresses and variable addresses. - * 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture - * specific IO header files. - * 27-Mar-1999 PJB Second parameter of memcpy_toio is const.. - * 04-Apr-1999 PJB Added check_signature. - * 12-Dec-1999 RMK More cleanups - * 18-Jun-2000 RMK Removed virt_to_* and friends definitions - */ -#ifndef __ASM_SH_IO_H -#define __ASM_SH_IO_H - -#ifdef __KERNEL__ - -#include <linux/types.h> -#include <asm/byteorder.h> - -/* - * Generic virtual read/write. Note that we don't support half-word - * read/writes. We define __arch_*[bl] here, and leave __arch_*w - * to the architecture specific code. - */ -#define __arch_getb(a) (*(volatile unsigned char *)(a)) -#define __arch_getw(a) (*(volatile unsigned short *)(a)) -#define __arch_getl(a) (*(volatile unsigned int *)(a)) - -#define __arch_putb(v, a) (*(volatile unsigned char *)(a) = (v)) -#define __arch_putw(v, a) (*(volatile unsigned short *)(a) = (v)) -#define __arch_putl(v, a) (*(volatile unsigned int *)(a) = (v)) - -extern void __raw_writesb(unsigned int addr, const void *data, int bytelen); -extern void __raw_writesw(unsigned int addr, const void *data, int wordlen); -extern void __raw_writesl(unsigned int addr, const void *data, int longlen); - -extern void __raw_readsb(unsigned int addr, void *data, int bytelen); -extern void __raw_readsw(unsigned int addr, void *data, int wordlen); -extern void __raw_readsl(unsigned int addr, void *data, int longlen); - -#define __raw_writeb(v, a) __arch_putb(v, a) -#define __raw_writew(v, a) __arch_putw(v, a) -#define __raw_writel(v, a) __arch_putl(v, a) - -#define __raw_readb(a) __arch_getb(a) -#define __raw_readw(a) __arch_getw(a) -#define __raw_readl(a) __arch_getl(a) - -/* - * The compiler seems to be incapable of optimising constants - * properly. Spell it out to the compiler in some cases. - * These are only valid for small values of "off" (< 1<<12) - */ -#define __raw_base_writeb(val, base, off) __arch_base_putb(val, base, off) -#define __raw_base_writew(val, base, off) __arch_base_putw(val, base, off) -#define __raw_base_writel(val, base, off) __arch_base_putl(val, base, off) - -#define __raw_base_readb(base, off) __arch_base_getb(base, off) -#define __raw_base_readw(base, off) __arch_base_getw(base, off) -#define __raw_base_readl(base, off) __arch_base_getl(base, off) - -/* - * Now, pick up the machine-defined IO definitions - */ -#if 0 /* XXX###XXX */ -#include <asm/arch/io.h> -#endif /* XXX###XXX */ - -/* - * IO port access primitives - * ------------------------- - * - * The SH doesn't have special IO access instructions; all IO is memory - * mapped. Note that these are defined to perform little endian accesses - * only. Their primary purpose is to access PCI and ISA peripherals. - * - * The machine specific io.h include defines __io to translate an "IO" - * address to a memory address. - * - * Note that we prevent GCC re-ordering or caching values in expressions - * by introducing sequence points into the in*() definitions. Note that - * __raw_* do not guarantee this behaviour. - * - * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space. - */ -#define outb(v, p) __raw_writeb(v, p) -#define outw(v, p) __raw_writew(cpu_to_le16(v), p) -#define outl(v, p) __raw_writel(cpu_to_le32(v), p) - -#define inb(p) ({ unsigned int __v = __raw_readb(p); __v; }) -#define inw(p) ({ unsigned int __v = __le16_to_cpu(__raw_readw(p)); __v; }) -#define inl(p) ({ unsigned int __v = __le32_to_cpu(__raw_readl(p)); __v; }) - -#define outsb(p, d, l) __raw_writesb(p, d, l) -#define outsw(p, d, l) __raw_writesw(p, d, l) -#define outsl(p, d, l) __raw_writesl(p, d, l) - -#define insb(p, d, l) __raw_readsb(p, d, l) -#define insw(p, d, l) __raw_readsw(p, d, l) -#define insl(p, d, l) __raw_readsl(p, d, l) - -#define outb_p(val, port) outb((val), (port)) -#define outw_p(val, port) outw((val), (port)) -#define outl_p(val, port) outl((val), (port)) -#define inb_p(port) inb((port)) -#define inw_p(port) inw((port)) -#define inl_p(port) inl((port)) - -#define outsb_p(port, from, len) outsb(port, from, len) -#define outsw_p(port, from, len) outsw(port, from, len) -#define outsl_p(port, from, len) outsl(port, from, len) -#define insb_p(port, to, len) insb(port, to, len) -#define insw_p(port, to, len) insw(port, to, len) -#define insl_p(port, to, len) insl(port, to, len) - -/* for U-Boot PCI */ -#define out_8(port, val) outb(val, port) -#define out_le16(port, val) outw(val, port) -#define out_le32(port, val) outl(val, port) -#define in_8(port) inb(port) -#define in_le16(port) inw(port) -#define in_le32(port) inl(port) -/* - * ioremap and friends. - * - * ioremap takes a PCI memory address, as specified in - * linux/Documentation/IO-mapping.txt. If you want a - * physical address, use __ioremap instead. - */ -extern void *__ioremap(unsigned long offset, size_t size, unsigned long flags); -extern void __iounmap(void *addr); - -/* - * Generic ioremap support. - * - * Define: - * iomem_valid_addr(off,size) - * iomem_to_phys(off) - */ -#ifdef iomem_valid_addr -#define __arch_ioremap(off, sz, nocache) \ - ({ \ - unsigned long _off = (off), _size = (sz); \ - void *_ret = (void *)0; \ - if (iomem_valid_addr(_off, _size)) \ - _ret = __ioremap(iomem_to_phys(_off), _size, 0); \ - _ret; \ - }) - -#define __arch_iounmap __iounmap -#endif - -#define ioremap(off, sz) __arch_ioremap((off), (sz), 0) -#define ioremap_nocache(off, sz) __arch_ioremap((off), (sz), 1) -#define iounmap(_addr) __arch_iounmap(_addr) - -/* - * DMA-consistent mapping functions. These allocate/free a region of - * uncached, unwrite-buffered mapped memory space for use with DMA - * devices. This is the "generic" version. The PCI specific version - * is in pci.h - */ -extern void *consistent_alloc(int gfp, size_t size, dma_addr_t *handle); -extern void consistent_free(void *vaddr, size_t size, dma_addr_t handle); -extern void consistent_sync(void *vaddr, size_t size, int rw); - -/* - * String version of IO memory access ops: - */ -extern void _memcpy_fromio(void *, unsigned long, size_t); -extern void _memcpy_toio(unsigned long, const void *, size_t); -extern void _memset_io(unsigned long, int, size_t); - -/* - * If this architecture has PCI memory IO, then define the read/write - * macros. These should only be used with the cookie passed from - * ioremap. - */ -#ifdef __mem_pci - -#define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; }) -#define readw(c)\ - ({ unsigned int __v = le16_to_cpu(__raw_readw(__mem_pci(c))); __v; }) -#define readl(c)\ - ({ unsigned int __v = le32_to_cpu(__raw_readl(__mem_pci(c))); __v; }) - -#define writeb(v, c) __raw_writeb(v, __mem_pci(c)) -#define writew(v, c) __raw_writew(cpu_to_le16(v), __mem_pci(c)) -#define writel(v, c) __raw_writel(cpu_to_le32(v), __mem_pci(c)) - -#define memset_io(c, v, l) _memset_io(__mem_pci(c), (v), (l)) -#define memcpy_fromio(a, c, l) _memcpy_fromio((a), __mem_pci(c), (l)) -#define memcpy_toio(c, a, l) _memcpy_toio(__mem_pci(c), (a), (l)) - -#define eth_io_copy_and_sum(s, c, l, b) \ - eth_copy_and_sum((s), __mem_pci(c), (l), (b)) - -static inline int -check_signature(unsigned long io_addr, const unsigned char *signature, - int length) -{ - int retval = 0; - do { - if (readb(io_addr) != *signature) - goto out; - io_addr++; - signature++; - length--; - } while (length); - retval = 1; -out: - return retval; -} - -#elif !defined(readb) - -#define readb(addr) __raw_readb(addr) -#define readw(addr) __raw_readw(addr) -#define readl(addr) __raw_readl(addr) -#define writeb(v, addr) __raw_writeb(v, addr) -#define writew(v, addr) __raw_writew(v, addr) -#define writel(v, addr) __raw_writel(v, addr) - -#define check_signature(io, sig, len) (0) - -#endif /* __mem_pci */ - -static inline void sync(void) -{ -} - -/* - * Given a physical address and a length, return a virtual address - * that can be used to access the memory range with the caching - * properties specified by "flags". - */ -#define MAP_NOCACHE (0) -#define MAP_WRCOMBINE (0) -#define MAP_WRBACK (0) -#define MAP_WRTHROUGH (0) - -static inline void * -map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags) -{ - return (void *)paddr; -} - -/* - * Take down a mapping set up by map_physmem(). - */ -static inline void unmap_physmem(void *vaddr, unsigned long flags) -{ - -} - -static inline phys_addr_t virt_to_phys(void * vaddr) -{ - return (phys_addr_t)(vaddr); -} - -#endif /* __KERNEL__ */ -#endif /* __ASM_SH_IO_H */ diff --git a/include/asm-sh/irqflags.h b/include/asm-sh/irqflags.h deleted file mode 100644 index 830e5486ac..0000000000 --- a/include/asm-sh/irqflags.h +++ /dev/null @@ -1,126 +0,0 @@ -#ifndef __ASM_SH_IRQFLAGS_H -#define __ASM_SH_IRQFLAGS_H - -static inline void raw_local_irq_enable(void) -{ - unsigned long __dummy0, __dummy1; - - __asm__ __volatile__ ( - "stc sr, %0\n\t" - "and %1, %0\n\t" -#ifdef CONFIG_CPU_HAS_SR_RB - "stc r6_bank, %1\n\t" - "or %1, %0\n\t" -#endif - "ldc %0, sr\n\t" - : "=&r" (__dummy0), "=r" (__dummy1) - : "1" (~0x000000f0) - : "memory" - ); -} - -static inline void raw_local_irq_disable(void) -{ - unsigned long flags; - - __asm__ __volatile__ ( - "stc sr, %0\n\t" - "or #0xf0, %0\n\t" - "ldc %0, sr\n\t" - : "=&z" (flags) - : /* no inputs */ - : "memory" - ); -} - -static inline void set_bl_bit(void) -{ - unsigned long __dummy0, __dummy1; - - __asm__ __volatile__ ( - "stc sr, %0\n\t" - "or %2, %0\n\t" - "and %3, %0\n\t" - "ldc %0, sr\n\t" - : "=&r" (__dummy0), "=r" (__dummy1) - : "r" (0x10000000), "r" (0xffffff0f) - : "memory" - ); -} - -static inline void clear_bl_bit(void) -{ - unsigned long __dummy0, __dummy1; - - __asm__ __volatile__ ( - "stc sr, %0\n\t" - "and %2, %0\n\t" - "ldc %0, sr\n\t" - : "=&r" (__dummy0), "=r" (__dummy1) - : "1" (~0x10000000) - : "memory" - ); -} - -static inline unsigned long __raw_local_save_flags(void) -{ - unsigned long flags; - - __asm__ __volatile__ ( - "stc sr, %0\n\t" - "and #0xf0, %0\n\t" - : "=&z" (flags) - : /* no inputs */ - : "memory" - ); - - return flags; -} - -#define raw_local_save_flags(flags) \ - do { (flags) = __raw_local_save_flags(); } while (0) - -static inline int raw_irqs_disabled_flags(unsigned long flags) -{ - return (flags != 0); -} - -static inline int raw_irqs_disabled(void) -{ - unsigned long flags = __raw_local_save_flags(); - - return raw_irqs_disabled_flags(flags); -} - -static inline unsigned long __raw_local_irq_save(void) -{ - unsigned long flags, __dummy; - - __asm__ __volatile__ ( - "stc sr, %1\n\t" - "mov %1, %0\n\t" - "or #0xf0, %0\n\t" - "ldc %0, sr\n\t" - "mov %1, %0\n\t" - "and #0xf0, %0\n\t" - : "=&z" (flags), "=&r" (__dummy) - : /* no inputs */ - : "memory" - ); - - return flags; -} - -#define raw_local_irq_save(flags) \ - do { (flags) = __raw_local_irq_save(); } while (0) - -#define local_irq_save raw_local_irq_save - -static inline void raw_local_irq_restore(unsigned long flags) -{ - if ((flags & 0xf0) != 0xf0) - raw_local_irq_enable(); -} -#define local_irq_restore raw_local_irq_restore - -#endif /* __ASM_SH_IRQFLAGS_H */ diff --git a/include/asm-sh/macro.h b/include/asm-sh/macro.h deleted file mode 100644 index 2b273c3ef4..0000000000 --- a/include/asm-sh/macro.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __MACRO_H__ -#define __MACRO_H__ -#ifdef __ASSEMBLY__ - -.macro write32, addr, data - mov.l \addr ,r1 - mov.l \data ,r0 - mov.l r0, @r1 -.endm - -.macro write16, addr, data - mov.l \addr ,r1 - mov.w \data ,r0 - mov.w r0, @r1 -.endm - -.macro write8, addr, data - mov.l \addr ,r1 - mov.l \data ,r0 - mov.b r0, @r1 -.endm - -.macro wait_timer, time - mov.l \time ,r3 -1: - nop - tst r3, r3 - bf/s 1b - dt r3 -.endm - -#endif /* __ASSEMBLY__ */ -#endif /* __MACRO_H__ */ diff --git a/include/asm-sh/pci.h b/include/asm-sh/pci.h deleted file mode 100644 index 040c532132..0000000000 --- a/include/asm-sh/pci.h +++ /dev/null @@ -1,48 +0,0 @@ -/* - * SH4 PCI Controller (PCIC) for U-Boot. - * (C) Dustin McIntire (dustin@sensoria.com) - * (C) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> - * (C) 2008 Yusuke Goda <goda.yusuke@renesas.com> - * - * u-boot/include/asm-sh/pci.h - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _ASM_PCI_H_ -#define _ASM_PCI_H_ - -#include <pci.h> -#if defined(CONFIG_SH7751_PCI) -int pci_sh7751_init(struct pci_controller *hose); -#elif defined(CONFIG_SH7780_PCI) -int pci_sh7780_init(struct pci_controller *hose); -#else -#error "Not support PCI." -#endif - -int pci_sh4_init(struct pci_controller *hose); -/* PCI dword read for sh4 */ -int pci_sh4_read_config_dword(struct pci_controller *hose, - pci_dev_t dev, int offset, u32 *value); - -/* PCI dword write for sh4 */ -int pci_sh4_write_config_dword(struct pci_controller *hose, - pci_dev_t dev, int offset, u32 value); - -#endif /* _ASM_PCI_H_ */ diff --git a/include/asm-sh/posix_types.h b/include/asm-sh/posix_types.h deleted file mode 100644 index c9d9fb84f1..0000000000 --- a/include/asm-sh/posix_types.h +++ /dev/null @@ -1,123 +0,0 @@ -#ifndef __ASM_SH_POSIX_TYPES_H -#define __ASM_SH_POSIX_TYPES_H - -/* - * This file is generally used by user-level software, so you need to - * be a little careful about namespace pollution etc. Also, we cannot - * assume GCC is being used. - */ - -typedef unsigned short __kernel_dev_t; -typedef unsigned long __kernel_ino_t; -typedef unsigned short __kernel_mode_t; -typedef unsigned short __kernel_nlink_t; -typedef long __kernel_off_t; -typedef int __kernel_pid_t; -typedef unsigned short __kernel_ipc_pid_t; -typedef unsigned short __kernel_uid_t; -typedef unsigned short __kernel_gid_t; -typedef unsigned int __kernel_size_t; -typedef int __kernel_ssize_t; -typedef int __kernel_ptrdiff_t; -typedef long __kernel_time_t; -typedef long __kernel_suseconds_t; -typedef long __kernel_clock_t; -typedef int __kernel_timer_t; -typedef int __kernel_clockid_t; -typedef int __kernel_daddr_t; -typedef char * __kernel_caddr_t; -typedef unsigned short __kernel_uid16_t; -typedef unsigned short __kernel_gid16_t; -typedef unsigned int __kernel_uid32_t; -typedef unsigned int __kernel_gid32_t; - -typedef unsigned short __kernel_old_uid_t; -typedef unsigned short __kernel_old_gid_t; -typedef unsigned short __kernel_old_dev_t; - -#ifdef __GNUC__ -typedef long long __kernel_loff_t; -#endif - -typedef struct { -#if defined(__KERNEL__) || defined(__USE_ALL) - int val[2]; -#else /* !defined(__KERNEL__) && !defined(__USE_ALL) */ - int __val[2]; -#endif /* !defined(__KERNEL__) && !defined(__USE_ALL) */ -} __kernel_fsid_t; - -#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) - -#undef __FD_SET -static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp) -{ - unsigned long __tmp = __fd / __NFDBITS; - unsigned long __rem = __fd % __NFDBITS; - __fdsetp->fds_bits[__tmp] |= (1UL<<__rem); -} - -#undef __FD_CLR -static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp) -{ - unsigned long __tmp = __fd / __NFDBITS; - unsigned long __rem = __fd % __NFDBITS; - __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem); -} - - -#undef __FD_ISSET -static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p) -{ - unsigned long __tmp = __fd / __NFDBITS; - unsigned long __rem = __fd % __NFDBITS; - return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0; -} - -/* - * This will unroll the loop for the normal constant case (8 ints, - * for a 256-bit fd_set) - */ -#undef __FD_ZERO -static __inline__ void __FD_ZERO(__kernel_fd_set *__p) -{ - unsigned long *__tmp = __p->fds_bits; - int __i; - - if (__builtin_constant_p(__FDSET_LONGS)) { - switch (__FDSET_LONGS) { - case 16: - __tmp[ 0] = 0; __tmp[ 1] = 0; - __tmp[ 2] = 0; __tmp[ 3] = 0; - __tmp[ 4] = 0; __tmp[ 5] = 0; - __tmp[ 6] = 0; __tmp[ 7] = 0; - __tmp[ 8] = 0; __tmp[ 9] = 0; - __tmp[10] = 0; __tmp[11] = 0; - __tmp[12] = 0; __tmp[13] = 0; - __tmp[14] = 0; __tmp[15] = 0; - return; - - case 8: - __tmp[ 0] = 0; __tmp[ 1] = 0; - __tmp[ 2] = 0; __tmp[ 3] = 0; - __tmp[ 4] = 0; __tmp[ 5] = 0; - __tmp[ 6] = 0; __tmp[ 7] = 0; - return; - - case 4: - __tmp[ 0] = 0; __tmp[ 1] = 0; - __tmp[ 2] = 0; __tmp[ 3] = 0; - return; - } - } - __i = __FDSET_LONGS; - while (__i) { - __i--; - *__tmp = 0; - __tmp++; - } -} - -#endif /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */ - -#endif /* __ASM_SH_POSIX_TYPES_H */ diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h deleted file mode 100644 index 938a89cff5..0000000000 --- a/include/asm-sh/processor.h +++ /dev/null @@ -1,12 +0,0 @@ -#ifndef _ASM_SH_PROCESSOR_H_ -#define _ASM_SH_PROCESSOR_H_ -#if defined(CONFIG_SH2) || \ - defined (CONFIG_SH2A) -# include <asm/cpu_sh2.h> -#elif defined (CONFIG_SH3) -# include <asm/cpu_sh3.h> -#elif defined (CONFIG_SH4) || \ - defined (CONFIG_SH4A) -# include <asm/cpu_sh4.h> -#endif -#endif diff --git a/include/asm-sh/ptrace.h b/include/asm-sh/ptrace.h deleted file mode 100644 index 16252cc25b..0000000000 --- a/include/asm-sh/ptrace.h +++ /dev/null @@ -1,112 +0,0 @@ -#ifndef __ASM_SH_PTRACE_H -#define __ASM_SH_PTRACE_H - -/* - * Copyright (C) 1999, 2000 Niibe Yutaka - * from linux kernel code. - */ - -/* - * GCC defines register number like this: - * ----------------------------- - * 0 - 15 are integer registers - * 17 - 22 are control/special registers - * 24 - 39 fp registers - * 40 - 47 xd registers - * 48 - fpscr register - * ----------------------------- - * - * We follows above, except: - * 16 --- program counter (PC) - * 22 --- syscall # - * 23 --- floating point communication register - */ -#define REG_REG0 0 -#define REG_REG15 15 - -#define REG_PC 16 - -#define REG_PR 17 -#define REG_SR 18 -#define REG_GBR 19 -#define REG_MACH 20 -#define REG_MACL 21 - -#define REG_SYSCALL 22 - -#define REG_FPREG0 23 -#define REG_FPREG15 38 -#define REG_XFREG0 39 -#define REG_XFREG15 54 - -#define REG_FPSCR 55 -#define REG_FPUL 56 - -/* options set using PTRACE_SETOPTIONS */ -#define PTRACE_O_TRACESYSGOOD 0x00000001 - -/* - * This struct defines the way the registers are stored on the - * kernel stack during a system call or other kernel entry. - */ -struct pt_regs { - unsigned long regs[16]; - unsigned long pc; - unsigned long pr; - unsigned long sr; - unsigned long gbr; - unsigned long mach; - unsigned long macl; - long tra; -}; - -/* - * This struct defines the way the DSP registers are stored on the - * kernel stack during a system call or other kernel entry. - */ -struct pt_dspregs { - unsigned long a1; - unsigned long a0g; - unsigned long a1g; - unsigned long m0; - unsigned long m1; - unsigned long a0; - unsigned long x0; - unsigned long x1; - unsigned long y0; - unsigned long y1; - unsigned long dsr; - unsigned long rs; - unsigned long re; - unsigned long mod; -}; - -#define PTRACE_GETDSPREGS 55 -#define PTRACE_SETDSPREGS 56 - -#ifdef __KERNEL__ -#define user_mode(regs) (((regs)->sr & 0x40000000)==0) -#define instruction_pointer(regs) ((regs)->pc) -extern void show_regs(struct pt_regs *); - -#ifdef CONFIG_SH_DSP -#define task_pt_regs(task) \ - ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \ - - sizeof(struct pt_dspregs) - sizeof(unsigned long)) - 1) -#else -#define task_pt_regs(task) \ - ((struct pt_regs *) (task_stack_page(task) + THREAD_SIZE \ - - sizeof(unsigned long)) - 1) -#endif - -static inline unsigned long profile_pc(struct pt_regs *regs) -{ - unsigned long pc = instruction_pointer(regs); - - if (pc >= 0xa0000000UL && pc < 0xc0000000UL) - pc -= 0x20000000; - return pc; -} -#endif - -#endif /* __ASM_SH_PTRACE_H */ diff --git a/include/asm-sh/string.h b/include/asm-sh/string.h deleted file mode 100644 index 27d981b79a..0000000000 --- a/include/asm-sh/string.h +++ /dev/null @@ -1,162 +0,0 @@ -#ifndef __ASM_SH_STRING_H -#define __ASM_SH_STRING_H - -/* - * Copyright (C) 1999 Niibe Yutaka - * But consider these trivial functions to be public domain. - * - * from linux kernel code. - */ - -#ifdef __KERNEL__ /* only set these up for kernel code */ - -#define __HAVE_ARCH_STRCPY -static inline char *strcpy(char *__dest, const char *__src) -{ - register char *__xdest = __dest; - unsigned long __dummy; - - __asm__ __volatile__("1:\n\t" - "mov.b @%1+, %2\n\t" - "mov.b %2, @%0\n\t" - "cmp/eq #0, %2\n\t" - "bf/s 1b\n\t" - " add #1, %0\n\t" - : "=r" (__dest), "=r" (__src), "=&z" (__dummy) - : "0" (__dest), "1" (__src) - : "memory", "t"); - - return __xdest; -} - -#define __HAVE_ARCH_STRNCPY -static inline char *strncpy(char *__dest, const char *__src, size_t __n) -{ - register char *__xdest = __dest; - unsigned long __dummy; - - if (__n == 0) - return __xdest; - - __asm__ __volatile__( - "1:\n" - "mov.b @%1+, %2\n\t" - "mov.b %2, @%0\n\t" - "cmp/eq #0, %2\n\t" - "bt/s 2f\n\t" - " cmp/eq %5,%1\n\t" - "bf/s 1b\n\t" - " add #1, %0\n" - "2:" - : "=r" (__dest), "=r" (__src), "=&z" (__dummy) - : "0" (__dest), "1" (__src), "r" (__src+__n) - : "memory", "t"); - - return __xdest; -} - -#define __HAVE_ARCH_STRCMP -static inline int strcmp(const char *__cs, const char *__ct) -{ - register int __res; - unsigned long __dummy; - - __asm__ __volatile__( - "mov.b @%1+, %3\n" - "1:\n\t" - "mov.b @%0+, %2\n\t" - "cmp/eq #0, %3\n\t" - "bt 2f\n\t" - "cmp/eq %2, %3\n\t" - "bt/s 1b\n\t" - " mov.b @%1+, %3\n\t" - "add #-2, %1\n\t" - "mov.b @%1, %3\n\t" - "sub %3, %2\n" - "2:" - : "=r" (__cs), "=r" (__ct), "=&r" (__res), "=&z" (__dummy) - : "0" (__cs), "1" (__ct) - : "t"); - - return __res; -} - -#define __HAVE_ARCH_STRNCMP -static inline int strncmp(const char *__cs, const char *__ct, size_t __n) -{ - register int __res; - unsigned long __dummy; - - if (__n == 0) - return 0; - - __asm__ __volatile__( - "mov.b @%1+, %3\n" - "1:\n\t" - "mov.b @%0+, %2\n\t" - "cmp/eq %6, %0\n\t" - "bt/s 2f\n\t" - " cmp/eq #0, %3\n\t" - "bt/s 3f\n\t" - " cmp/eq %3, %2\n\t" - "bt/s 1b\n\t" - " mov.b @%1+, %3\n\t" - "add #-2, %1\n\t" - "mov.b @%1, %3\n" - "2:\n\t" - "sub %3, %2\n" - "3:" - :"=r" (__cs), "=r" (__ct), "=&r" (__res), "=&z" (__dummy) - : "0" (__cs), "1" (__ct), "r" (__cs+__n) - : "t"); - - return __res; -} - -#undef __HAVE_ARCH_MEMSET -extern void *memset(void *__s, int __c, size_t __count); - -#undef __HAVE_ARCH_MEMCPY -extern void *memcpy(void *__to, __const__ void *__from, size_t __n); - -#undef __HAVE_ARCH_MEMMOVE -extern void *memmove(void *__dest, __const__ void *__src, size_t __n); - -#undef __HAVE_ARCH_MEMCHR -extern void *memchr(const void *__s, int __c, size_t __n); - -#undef __HAVE_ARCH_STRLEN -extern size_t strlen(const char *); - -/* arch/sh/lib/strcasecmp.c */ -extern int strcasecmp(const char *, const char *); - -#else /* KERNEL */ - -/* - * let user libraries deal with these, - * IMHO the kernel has no place defining these functions for user apps - */ - -#define __HAVE_ARCH_STRCPY 1 -#define __HAVE_ARCH_STRNCPY 1 -#define __HAVE_ARCH_STRCAT 1 -#define __HAVE_ARCH_STRNCAT 1 -#define __HAVE_ARCH_STRCMP 1 -#define __HAVE_ARCH_STRNCMP 1 -#define __HAVE_ARCH_STRNICMP 1 -#define __HAVE_ARCH_STRCHR 1 -#define __HAVE_ARCH_STRRCHR 1 -#define __HAVE_ARCH_STRSTR 1 -#define __HAVE_ARCH_STRLEN 1 -#define __HAVE_ARCH_STRNLEN 1 -#define __HAVE_ARCH_MEMSET 1 -#define __HAVE_ARCH_MEMCPY 1 -#define __HAVE_ARCH_MEMMOVE 1 -#define __HAVE_ARCH_MEMSCAN 1 -#define __HAVE_ARCH_MEMCMP 1 -#define __HAVE_ARCH_MEMCHR 1 -#define __HAVE_ARCH_STRTOK 1 - -#endif /* KERNEL */ -#endif /* __ASM_SH_STRING_H */ diff --git a/include/asm-sh/system.h b/include/asm-sh/system.h deleted file mode 100644 index a62c42261d..0000000000 --- a/include/asm-sh/system.h +++ /dev/null @@ -1,275 +0,0 @@ -#ifndef __ASM_SH_SYSTEM_H -#define __ASM_SH_SYSTEM_H - -/* - * Copyright (C) 1999, 2000 Niibe Yutaka & Kaz Kojima - * Copyright (C) 2002 Paul Mundt - * - * from linux kernel code. - */ - -#include <linux/irqflags.h> -#include <asm/types.h> - -/* - * switch_to() should switch tasks to task nr n, first - */ - -#define switch_to(prev, next, last) do { \ - struct task_struct *__last; \ - register unsigned long *__ts1 __asm__ ("r1") = &prev->thread.sp; \ - register unsigned long *__ts2 __asm__ ("r2") = &prev->thread.pc; \ - register unsigned long *__ts4 __asm__ ("r4") = (unsigned long *)prev; \ - register unsigned long *__ts5 __asm__ ("r5") = (unsigned long *)next; \ - register unsigned long *__ts6 __asm__ ("r6") = &next->thread.sp; \ - register unsigned long __ts7 __asm__ ("r7") = next->thread.pc; \ - __asm__ __volatile__ (".balign 4\n\t" \ - "stc.l gbr, @-r15\n\t" \ - "sts.l pr, @-r15\n\t" \ - "mov.l r8, @-r15\n\t" \ - "mov.l r9, @-r15\n\t" \ - "mov.l r10, @-r15\n\t" \ - "mov.l r11, @-r15\n\t" \ - "mov.l r12, @-r15\n\t" \ - "mov.l r13, @-r15\n\t" \ - "mov.l r14, @-r15\n\t" \ - "mov.l r15, @r1 ! save SP\n\t" \ - "mov.l @r6, r15 ! change to new stack\n\t" \ - "mova 1f, %0\n\t" \ - "mov.l %0, @r2 ! save PC\n\t" \ - "mov.l 2f, %0\n\t" \ - "jmp @%0 ! call __switch_to\n\t" \ - " lds r7, pr ! with return to new PC\n\t" \ - ".balign 4\n" \ - "2:\n\t" \ - ".long __switch_to\n" \ - "1:\n\t" \ - "mov.l @r15+, r14\n\t" \ - "mov.l @r15+, r13\n\t" \ - "mov.l @r15+, r12\n\t" \ - "mov.l @r15+, r11\n\t" \ - "mov.l @r15+, r10\n\t" \ - "mov.l @r15+, r9\n\t" \ - "mov.l @r15+, r8\n\t" \ - "lds.l @r15+, pr\n\t" \ - "ldc.l @r15+, gbr\n\t" \ - : "=z" (__last) \ - : "r" (__ts1), "r" (__ts2), "r" (__ts4), \ - "r" (__ts5), "r" (__ts6), "r" (__ts7) \ - : "r3", "t"); \ - last = __last; \ -} while (0) - -/* - * On SMP systems, when the scheduler does migration-cost autodetection, - * it needs a way to flush as much of the CPU's caches as possible. - * - * TODO: fill this in! - */ -static inline void sched_cacheflush(void) -{ -} - -#ifdef CONFIG_CPU_SH4A -#define __icbi() \ -{ \ - unsigned long __addr; \ - __addr = 0xa8000000; \ - __asm__ __volatile__( \ - "icbi %0\n\t" \ - : /* no output */ \ - : "m" (__m(__addr))); \ -} -#endif - -static inline unsigned long tas(volatile int *m) -{ - unsigned long retval; - - __asm__ __volatile__ ("tas.b @%1\n\t" - "movt %0" - : "=r" (retval): "r" (m): "t", "memory"); - return retval; -} - -/* - * A brief note on ctrl_barrier(), the control register write barrier. - * - * Legacy SH cores typically require a sequence of 8 nops after - * modification of a control register in order for the changes to take - * effect. On newer cores (like the sh4a and sh5) this is accomplished - * with icbi. - * - * Also note that on sh4a in the icbi case we can forego a synco for the - * write barrier, as it's not necessary for control registers. - * - * Historically we have only done this type of barrier for the MMUCR, but - * it's also necessary for the CCR, so we make it generic here instead. - */ -#ifdef CONFIG_CPU_SH4A -#define mb() __asm__ __volatile__ ("synco": : :"memory") -#define rmb() mb() -#define wmb() __asm__ __volatile__ ("synco": : :"memory") -#define ctrl_barrier() __icbi() -#define read_barrier_depends() do { } while(0) -#else -#define mb() __asm__ __volatile__ ("": : :"memory") -#define rmb() mb() -#define wmb() __asm__ __volatile__ ("": : :"memory") -#define ctrl_barrier() __asm__ __volatile__ ("nop;nop;nop;nop;nop;nop;nop;nop") -#define read_barrier_depends() do { } while(0) -#endif - -#ifdef CONFIG_SMP -#define smp_mb() mb() -#define smp_rmb() rmb() -#define smp_wmb() wmb() -#define smp_read_barrier_depends() read_barrier_depends() -#else -#define smp_mb() barrier() -#define smp_rmb() barrier() -#define smp_wmb() barrier() -#define smp_read_barrier_depends() do { } while(0) -#endif - -#define set_mb(var, value) do { xchg(&var, value); } while (0) - -/* - * Jump to P2 area. - * When handling TLB or caches, we need to do it from P2 area. - */ -#define jump_to_P2() \ -do { \ - unsigned long __dummy; \ - __asm__ __volatile__( \ - "mov.l 1f, %0\n\t" \ - "or %1, %0\n\t" \ - "jmp @%0\n\t" \ - " nop\n\t" \ - ".balign 4\n" \ - "1: .long 2f\n" \ - "2:" \ - : "=&r" (__dummy) \ - : "r" (0x20000000)); \ -} while (0) - -/* - * Back to P1 area. - */ -#define back_to_P1() \ -do { \ - unsigned long __dummy; \ - ctrl_barrier(); \ - __asm__ __volatile__( \ - "mov.l 1f, %0\n\t" \ - "jmp @%0\n\t" \ - " nop\n\t" \ - ".balign 4\n" \ - "1: .long 2f\n" \ - "2:" \ - : "=&r" (__dummy)); \ -} while (0) - -static inline unsigned long xchg_u32(volatile u32 *m, unsigned long val) -{ - unsigned long flags, retval; - - local_irq_save(flags); - retval = *m; - *m = val; - local_irq_restore(flags); - return retval; -} - -static inline unsigned long xchg_u8(volatile u8 *m, unsigned long val) -{ - unsigned long flags, retval; - - local_irq_save(flags); - retval = *m; - *m = val & 0xff; - local_irq_restore(flags); - return retval; -} - -extern void __xchg_called_with_bad_pointer(void); - -#define __xchg(ptr, x, size) \ -({ \ - unsigned long __xchg__res; \ - volatile void *__xchg_ptr = (ptr); \ - switch (size) { \ - case 4: \ - __xchg__res = xchg_u32(__xchg_ptr, x); \ - break; \ - case 1: \ - __xchg__res = xchg_u8(__xchg_ptr, x); \ - break; \ - default: \ - __xchg_called_with_bad_pointer(); \ - __xchg__res = x; \ - break; \ - } \ - \ - __xchg__res; \ -}) - -#define xchg(ptr,x) \ - ((__typeof__(*(ptr)))__xchg((ptr),(unsigned long)(x), sizeof(*(ptr)))) - -static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old, - unsigned long new) -{ - __u32 retval; - unsigned long flags; - - local_irq_save(flags); - retval = *m; - if (retval == old) - *m = new; - local_irq_restore(flags); /* implies memory barrier */ - return retval; -} - -/* This function doesn't exist, so you'll get a linker error - * if something tries to do an invalid cmpxchg(). */ -extern void __cmpxchg_called_with_bad_pointer(void); - -#define __HAVE_ARCH_CMPXCHG 1 - -static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old, - unsigned long new, int size) -{ - switch (size) { - case 4: - return __cmpxchg_u32(ptr, old, new); - } - __cmpxchg_called_with_bad_pointer(); - return old; -} - -#define cmpxchg(ptr,o,n) \ - ({ \ - __typeof__(*(ptr)) _o_ = (o); \ - __typeof__(*(ptr)) _n_ = (n); \ - (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \ - (unsigned long)_n_, sizeof(*(ptr))); \ - }) - -extern void *set_exception_table_vec(unsigned int vec, void *handler); - -static inline void *set_exception_table_evt(unsigned int evt, void *handler) -{ - return set_exception_table_vec(evt >> 5, handler); -} - -/* XXX - * disable hlt during certain critical i/o operations - */ -#define HAVE_DISABLE_HLT -void disable_hlt(void); -void enable_hlt(void); - -#define arch_align_stack(x) (x) - -#endif diff --git a/include/asm-sh/types.h b/include/asm-sh/types.h deleted file mode 100644 index aed4a6eb57..0000000000 --- a/include/asm-sh/types.h +++ /dev/null @@ -1,62 +0,0 @@ -#ifndef __ASM_SH_TYPES_H -#define __ASM_SH_TYPES_H - -#ifndef __ASSEMBLY__ - -typedef unsigned short umode_t; - -/* - * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the - * header files exported to user space - */ - -typedef __signed__ char __s8; -typedef unsigned char __u8; - -typedef __signed__ short __s16; -typedef unsigned short __u16; - -typedef __signed__ int __s32; -typedef unsigned int __u32; - -#if defined(__GNUC__) -__extension__ typedef __signed__ long long __s64; -__extension__ typedef unsigned long long __u64; -#endif - -#endif /* __ASSEMBLY__ */ - -/* - * These aren't exported outside the kernel to avoid name space clashes - */ -#ifdef __KERNEL__ - -#define BITS_PER_LONG 32 - -#ifndef __ASSEMBLY__ - - -typedef __signed__ char s8; -typedef unsigned char u8; - -typedef __signed__ short s16; -typedef unsigned short u16; - -typedef __signed__ int s32; -typedef unsigned int u32; - -typedef __signed__ long long s64; -typedef unsigned long long u64; - -/* Dma addresses are 32-bits wide. */ - -typedef u32 dma_addr_t; - -typedef unsigned long phys_addr_t; -typedef unsigned long phys_size_t; - -#endif /* __ASSEMBLY__ */ - -#endif /* __KERNEL__ */ - -#endif /* __ASM_SH_TYPES_H */ diff --git a/include/asm-sh/u-boot.h b/include/asm-sh/u-boot.h deleted file mode 100644 index 27d43b9347..0000000000 --- a/include/asm-sh/u-boot.h +++ /dev/null @@ -1,41 +0,0 @@ -/* - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - * - ******************************************************************** - * NOTE: This header file defines an interface to U-Boot. Including - * this (unmodified) header file in another file is considered normal - * use of U-Boot, and does *not* fall under the heading of "derived - * work". - ******************************************************************** - */ - -#ifndef __ASM_SH_U_BOOT_H_ -#define __ASM_SH_U_BOOT_H_ - -typedef struct bd_info { - unsigned long bi_memstart; /* start of DRAM memory */ - phys_size_t bi_memsize; /* size of DRAM memory in bytes */ - unsigned long bi_flashstart; /* start of FLASH memory */ - unsigned long bi_flashsize; /* size of FLASH memory */ - unsigned long bi_flashoffset; /* reserved area for startup monitor */ - unsigned long bi_sramstart; /* start of SRAM memory */ - unsigned long bi_sramsize; /* size of SRAM memory */ - unsigned long bi_ip_addr; /* IP Address */ - unsigned long bi_baudrate; /* Console Baudrate */ - unsigned long bi_boot_params; /* where this board expects params */ -} bd_t; - -#endif diff --git a/include/asm-sh/unaligned-sh4a.h b/include/asm-sh/unaligned-sh4a.h deleted file mode 100644 index 9f4dd252c9..0000000000 --- a/include/asm-sh/unaligned-sh4a.h +++ /dev/null @@ -1,258 +0,0 @@ -#ifndef __ASM_SH_UNALIGNED_SH4A_H -#define __ASM_SH_UNALIGNED_SH4A_H - -/* - * SH-4A has support for unaligned 32-bit loads, and 32-bit loads only. - * Support for 64-bit accesses are done through shifting and masking - * relative to the endianness. Unaligned stores are not supported by the - * instruction encoding, so these continue to use the packed - * struct. - * - * The same note as with the movli.l/movco.l pair applies here, as long - * as the load is gauranteed to be inlined, nothing else will hook in to - * r0 and we get the return value for free. - * - * NOTE: Due to the fact we require r0 encoding, care should be taken to - * avoid mixing these heavily with other r0 consumers, such as the atomic - * ops. Failure to adhere to this can result in the compiler running out - * of spill registers and blowing up when building at low optimization - * levels. See http://gcc.gnu.org/bugzilla/show_bug.cgi?id=34777. - */ -#include <linux/types.h> -#include <asm/byteorder.h> - -static __always_inline u32 __get_unaligned_cpu32(const u8 *p) -{ - unsigned long unaligned; - - __asm__ __volatile__ ( - "movua.l @%1, %0\n\t" - : "=z" (unaligned) - : "r" (p) - ); - - return unaligned; -} - -struct __una_u16 { u16 x __attribute__((packed)); }; -struct __una_u32 { u32 x __attribute__((packed)); }; -struct __una_u64 { u64 x __attribute__((packed)); }; - -static inline u16 __get_unaligned_cpu16(const u8 *p) -{ -#ifdef __LITTLE_ENDIAN - return p[0] | p[1] << 8; -#else - return p[0] << 8 | p[1]; -#endif -} - -/* - * Even though movua.l supports auto-increment on the read side, it can - * only store to r0 due to instruction encoding constraints, so just let - * the compiler sort it out on its own. - */ -static inline u64 __get_unaligned_cpu64(const u8 *p) -{ -#ifdef __LITTLE_ENDIAN - return (u64)__get_unaligned_cpu32(p + 4) << 32 | - __get_unaligned_cpu32(p); -#else - return (u64)__get_unaligned_cpu32(p) << 32 | - __get_unaligned_cpu32(p + 4); -#endif -} - -static inline u16 get_unaligned_le16(const void *p) -{ - return le16_to_cpu(__get_unaligned_cpu16(p)); -} - -static inline u32 get_unaligned_le32(const void *p) -{ - return le32_to_cpu(__get_unaligned_cpu32(p)); -} - -static inline u64 get_unaligned_le64(const void *p) -{ - return le64_to_cpu(__get_unaligned_cpu64(p)); -} - -static inline u16 get_unaligned_be16(const void *p) -{ - return be16_to_cpu(__get_unaligned_cpu16(p)); -} - -static inline u32 get_unaligned_be32(const void *p) -{ - return be32_to_cpu(__get_unaligned_cpu32(p)); -} - -static inline u64 get_unaligned_be64(const void *p) -{ - return be64_to_cpu(__get_unaligned_cpu64(p)); -} - -static inline void __put_le16_noalign(u8 *p, u16 val) -{ - *p++ = val; - *p++ = val >> 8; -} - -static inline void __put_le32_noalign(u8 *p, u32 val) -{ - __put_le16_noalign(p, val); - __put_le16_noalign(p + 2, val >> 16); -} - -static inline void __put_le64_noalign(u8 *p, u64 val) -{ - __put_le32_noalign(p, val); - __put_le32_noalign(p + 4, val >> 32); -} - -static inline void __put_be16_noalign(u8 *p, u16 val) -{ - *p++ = val >> 8; - *p++ = val; -} - -static inline void __put_be32_noalign(u8 *p, u32 val) -{ - __put_be16_noalign(p, val >> 16); - __put_be16_noalign(p + 2, val); -} - -static inline void __put_be64_noalign(u8 *p, u64 val) -{ - __put_be32_noalign(p, val >> 32); - __put_be32_noalign(p + 4, val); -} - -static inline void put_unaligned_le16(u16 val, void *p) -{ -#ifdef __LITTLE_ENDIAN - ((struct __una_u16 *)p)->x = val; -#else - __put_le16_noalign(p, val); -#endif -} - -static inline void put_unaligned_le32(u32 val, void *p) -{ -#ifdef __LITTLE_ENDIAN - ((struct __una_u32 *)p)->x = val; -#else - __put_le32_noalign(p, val); -#endif -} - -static inline void put_unaligned_le64(u64 val, void *p) -{ -#ifdef __LITTLE_ENDIAN - ((struct __una_u64 *)p)->x = val; -#else - __put_le64_noalign(p, val); -#endif -} - -static inline void put_unaligned_be16(u16 val, void *p) -{ -#ifdef __BIG_ENDIAN - ((struct __una_u16 *)p)->x = val; -#else - __put_be16_noalign(p, val); -#endif -} - -static inline void put_unaligned_be32(u32 val, void *p) -{ -#ifdef __BIG_ENDIAN - ((struct __una_u32 *)p)->x = val; -#else - __put_be32_noalign(p, val); -#endif -} - -static inline void put_unaligned_be64(u64 val, void *p) -{ -#ifdef __BIG_ENDIAN - ((struct __una_u64 *)p)->x = val; -#else - __put_be64_noalign(p, val); -#endif -} - -/* - * Cause a link-time error if we try an unaligned access other than - * 1,2,4 or 8 bytes long - */ -extern void __bad_unaligned_access_size(void); - -#define __get_unaligned_le(ptr) ((__force typeof(*(ptr)))({ \ - __builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr), \ - __builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_le16((ptr)), \ - __builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_le32((ptr)), \ - __builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_le64((ptr)), \ - __bad_unaligned_access_size())))); \ - })) - -#define __get_unaligned_be(ptr) ((__force typeof(*(ptr)))({ \ - __builtin_choose_expr(sizeof(*(ptr)) == 1, *(ptr), \ - __builtin_choose_expr(sizeof(*(ptr)) == 2, get_unaligned_be16((ptr)), \ - __builtin_choose_expr(sizeof(*(ptr)) == 4, get_unaligned_be32((ptr)), \ - __builtin_choose_expr(sizeof(*(ptr)) == 8, get_unaligned_be64((ptr)), \ - __bad_unaligned_access_size())))); \ - })) - -#define __put_unaligned_le(val, ptr) ({ \ - void *__gu_p = (ptr); \ - switch (sizeof(*(ptr))) { \ - case 1: \ - *(u8 *)__gu_p = (__force u8)(val); \ - break; \ - case 2: \ - put_unaligned_le16((__force u16)(val), __gu_p); \ - break; \ - case 4: \ - put_unaligned_le32((__force u32)(val), __gu_p); \ - break; \ - case 8: \ - put_unaligned_le64((__force u64)(val), __gu_p); \ - break; \ - default: \ - __bad_unaligned_access_size(); \ - break; \ - } \ - (void)0; }) - -#define __put_unaligned_be(val, ptr) ({ \ - void *__gu_p = (ptr); \ - switch (sizeof(*(ptr))) { \ - case 1: \ - *(u8 *)__gu_p = (__force u8)(val); \ - break; \ - case 2: \ - put_unaligned_be16((__force u16)(val), __gu_p); \ - break; \ - case 4: \ - put_unaligned_be32((__force u32)(val), __gu_p); \ - break; \ - case 8: \ - put_unaligned_be64((__force u64)(val), __gu_p); \ - break; \ - default: \ - __bad_unaligned_access_size(); \ - break; \ - } \ - (void)0; }) - -#ifdef __LITTLE_ENDIAN -# define get_unaligned __get_unaligned_le -# define put_unaligned __put_unaligned_le -#else -# define get_unaligned __get_unaligned_be -# define put_unaligned __put_unaligned_be -#endif - -#endif /* __ASM_SH_UNALIGNED_SH4A_H */ diff --git a/include/asm-sh/unaligned.h b/include/asm-sh/unaligned.h deleted file mode 100644 index 2e0d164050..0000000000 --- a/include/asm-sh/unaligned.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef _ASM_SH_UNALIGNED_H -#define _ASM_SH_UNALIGNED_H - -/* Copy from linux-kernel. */ - -#ifdef CONFIG_CPU_SH4A -/* SH-4A can handle unaligned loads in a relatively neutered fashion. */ -#include <asm/unaligned-sh4a.h> -#else -/* Otherwise, SH can't handle unaligned accesses. */ -#include <compiler.h> -#if defined(__BIG_ENDIAN__) -#define get_unaligned __get_unaligned_be -#define put_unaligned __put_unaligned_be -#elif defined(__LITTLE_ENDIAN__) -#define get_unaligned __get_unaligned_le -#define put_unaligned __put_unaligned_le -#endif - -#include <linux/unaligned/le_byteshift.h> -#include <linux/unaligned/be_byteshift.h> -#include <linux/unaligned/generic.h> -#endif - -#endif /* _ASM_SH_UNALIGNED_H */ |
