diff options
Diffstat (limited to 'cpu/mcf5227x')
| -rw-r--r-- | cpu/mcf5227x/cpu_init.c | 16 | ||||
| -rw-r--r-- | cpu/mcf5227x/start.S | 100 |
2 files changed, 16 insertions, 100 deletions
diff --git a/cpu/mcf5227x/cpu_init.c b/cpu/mcf5227x/cpu_init.c index e160ee1aff..beb78f5839 100644 --- a/cpu/mcf5227x/cpu_init.c +++ b/cpu/mcf5227x/cpu_init.c @@ -125,27 +125,27 @@ int cpu_init_r(void) return (0); } -void uart_port_conf(void) +void uart_port_conf(int port) { volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO; /* Setup Ports: */ - switch (CONFIG_SYS_UART_PORT) { + switch (port) { case 0: gpio->par_uart &= - (GPIO_PAR_UART_U0TXD_MASK & GPIO_PAR_UART_U0RXD_MASK); + (GPIO_PAR_UART_U0TXD_UNMASK & GPIO_PAR_UART_U0RXD_UNMASK); gpio->par_uart |= (GPIO_PAR_UART_U0TXD_U0TXD | GPIO_PAR_UART_U0RXD_U0RXD); break; case 1: gpio->par_uart &= - (GPIO_PAR_UART_U1TXD_MASK & GPIO_PAR_UART_U1RXD_MASK); + (GPIO_PAR_UART_U1TXD_UNMASK & GPIO_PAR_UART_U1RXD_UNMASK); gpio->par_uart |= (GPIO_PAR_UART_U1TXD_U1TXD | GPIO_PAR_UART_U1RXD_U1RXD); break; case 2: gpio->par_dspi &= - (GPIO_PAR_DSPI_SIN_MASK & GPIO_PAR_DSPI_SOUT_MASK); + (GPIO_PAR_DSPI_SIN_UNMASK & GPIO_PAR_DSPI_SOUT_UNMASK); gpio->par_dspi = (GPIO_PAR_DSPI_SIN_U2RXD | GPIO_PAR_DSPI_SOUT_U2TXD); break; @@ -175,11 +175,11 @@ int cfspi_claim_bus(uint bus, uint cs) switch (cs) { case 0: - gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_MASK; + gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_UNMASK; gpio->par_dspi |= GPIO_PAR_DSPI_PCS0_PCS0; break; case 2: - gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK; + gpio->par_timer &= GPIO_PAR_TIMER_T2IN_UNMASK; gpio->par_timer |= GPIO_PAR_TIMER_T2IN_DSPIPCS2; break; } @@ -199,7 +199,7 @@ void cfspi_release_bus(uint bus, uint cs) gpio->par_dspi &= ~GPIO_PAR_DSPI_PCS0_PCS0; break; case 2: - gpio->par_timer &= GPIO_PAR_TIMER_T2IN_MASK; + gpio->par_timer &= GPIO_PAR_TIMER_T2IN_UNMASK; break; } } diff --git a/cpu/mcf5227x/start.S b/cpu/mcf5227x/start.S index 0c9c89c402..30428f15d8 100644 --- a/cpu/mcf5227x/start.S +++ b/cpu/mcf5227x/start.S @@ -24,16 +24,12 @@ #include <config.h> #include <timestamp.h> #include "version.h" +#include <asm/cache.h> #ifndef CONFIG_IDENT_STRING #define CONFIG_IDENT_STRING "" #endif -/* last three long word reserved for cache status */ -#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 4) -#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END- 8) -#define CACR_STATUS (CONFIG_SYS_INIT_RAM_ADDR+CONFIG_SYS_INIT_RAM_END-12) - #define _START _start #define _FAULT _fault @@ -378,21 +374,19 @@ _start: movec %d0, %RAMBAR1 #endif + /* invalidate and disable cache */ + move.l #CF_CACR_CINV, %d0 /* Invalidate cache cmd */ + movec %d0, %CACR /* Invalidate cache */ + move.l #0, %d0 + movec %d0, %ACR0 + movec %d0, %ACR1 + /* initialize general use internal ram */ move.l #0, %d0 move.l #(ICACHE_STATUS), %a1 /* icache */ move.l #(DCACHE_STATUS), %a2 /* icache */ - move.l #(CACR_STATUS), %a3 /* CACR */ move.l %d0, (%a1) move.l %d0, (%a2) - move.l %d0, (%a3) - - /* invalidate and disable cache */ - move.l #0x01000000, %d0 /* Invalidate cache cmd */ - movec %d0, %CACR /* Invalidate cache */ - move.l #0, %d0 - movec %d0, %ACR0 - movec %d0, %ACR1 /* set stackpointer to end of internal ram to get some stackspace for the first c-code */ @@ -510,84 +504,6 @@ _int_handler: RESTORE_ALL /*------------------------------------------------------------------------------*/ -/* cache functions */ - .globl icache_enable -icache_enable: - move.l #0x01200000, %d0 /* Invalid cache */ - movec %d0, %CACR - - move.l #(CONFIG_SYS_SDRAM_BASE + 0x1c000), %d0 - movec %d0, %ACR0 - - move.l #0x81600610, %d0 /* Enable cache */ - movec %d0, %CACR - - move.l #(ICACHE_STATUS), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - .globl icache_disable -icache_disable: - move.l #0x01F00000, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Invalidate icache */ - clr.l %d0 - movec %d0, %ACR0 - movec %d0, %ACR1 - - move.l #(ICACHE_STATUS), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl icache_status -icache_status: - move.l #(ICACHE_STATUS), %a1 - move.l (%a1), %d0 - rts - - .globl icache_invalid -icache_invalid: - move.l #0x80600610, %d0 /* Invalidate icache */ - movec %d0, %CACR /* Enable and invalidate cache */ - rts - - .globl dcache_enable -dcache_enable: - move.l #0x01200000, %d0 /* Invalid cache */ - movec %d0, %CACR - - move.l #0x81300610, %d0 - movec %d0, %CACR - - move.l #(DCACHE_STATUS), %a1 - moveq #1, %d0 - move.l %d0, (%a1) - rts - - .globl dcache_disable -dcache_disable: - move.l #0x81600610, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Invalidate icache */ - - move.l #(DCACHE_STATUS), %a1 - moveq #0, %d0 - move.l %d0, (%a1) - rts - - .globl dcache_invalid -dcache_invalid: - move.l #0x81100610, %d0 /* Setup cache mask */ - movec %d0, %CACR /* Enable and invalidate cache */ - rts - - .globl dcache_status -dcache_status: - move.l #(DCACHE_STATUS), %a1 - move.l (%a1), %d0 - rts - -/*------------------------------------------------------------------------------*/ .globl version_string version_string: |
