diff options
Diffstat (limited to 'board')
150 files changed, 4376 insertions, 926 deletions
diff --git a/board/BuS/eb_cpux9k2/Kconfig b/board/BuS/eb_cpux9k2/Kconfig index 230e64d8fc..e2a787a1a8 100644 --- a/board/BuS/eb_cpux9k2/Kconfig +++ b/board/BuS/eb_cpux9k2/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "BuS" -config SYS_SOC - default "at91" - config SYS_CONFIG_NAME default "eb_cpux9k2" diff --git a/board/BuS/eb_cpux9k2/cpux9k2.c b/board/BuS/eb_cpux9k2/cpux9k2.c index 5e4778e978..76ad7c443b 100644 --- a/board/BuS/eb_cpux9k2/cpux9k2.c +++ b/board/BuS/eb_cpux9k2/cpux9k2.c @@ -98,7 +98,7 @@ int misc_init_r(void) puts("Error: invalid MAC at EEPROM\n"); } } - gd->jt[XF_do_reset] = (void *) do_reset; + gd->jt->do_reset = do_reset; #ifdef CONFIG_STATUS_LED status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING); diff --git a/board/BuS/vl_ma2sc/Kconfig b/board/BuS/vl_ma2sc/Kconfig index 2f43519089..848177f4c4 100644 --- a/board/BuS/vl_ma2sc/Kconfig +++ b/board/BuS/vl_ma2sc/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "BuS" -config SYS_SOC - default "at91" - config SYS_CONFIG_NAME default "vl_ma2sc" diff --git a/board/Marvell/db-mv784mp-gp/binary.0 b/board/Marvell/db-mv784mp-gp/binary.0 deleted file mode 100644 index 17bfad99dc..0000000000 --- a/board/Marvell/db-mv784mp-gp/binary.0 +++ /dev/null @@ -1,17 +0,0 @@ --------- -WARNING: --------- -This file should contain the bin_hdr generated by the original Marvell -U-Boot implementation. As this is currently not included in this -U-Boot version, we have added this placeholder, so that the U-Boot -image can be generated without errors. - -If you have a known to be working bin_hdr for your board, then you -just need to replace this text file here with the binary header -and recompile U-Boot. - -In a few weeks, mainline U-Boot will get support to generate the -bin_hdr with the DDR training code itself. By implementing this code -as SPL U-Boot. Then this file will not be needed any more and will -get removed. - diff --git a/board/Marvell/db-mv784mp-gp/kwbimage.cfg b/board/Marvell/db-mv784mp-gp/kwbimage.cfg index d7ef4071dd..cc05792556 100644 --- a/board/Marvell/db-mv784mp-gp/kwbimage.cfg +++ b/board/Marvell/db-mv784mp-gp/kwbimage.cfg @@ -9,4 +9,4 @@ VERSION 1 BOOT_FROM spi # Binary Header (bin_hdr) with DDR3 training code -BINARY board/Marvell/db-mv784mp-gp/binary.0 0000005b 00000068 +BINARY spl/u-boot-spl.bin 0000005b 00000068 diff --git a/board/afeb9260/Kconfig b/board/afeb9260/Kconfig index 6a5a93139d..fb64c9cec7 100644 --- a/board/afeb9260/Kconfig +++ b/board/afeb9260/Kconfig @@ -3,9 +3,6 @@ if TARGET_AFEB9260 config SYS_BOARD default "afeb9260" -config SYS_SOC - default "at91" - config SYS_CONFIG_NAME default "afeb9260" diff --git a/board/amcc/canyonlands/Kconfig b/board/amcc/canyonlands/Kconfig index 530a6efd60..848e08fbba 100644 --- a/board/amcc/canyonlands/Kconfig +++ b/board/amcc/canyonlands/Kconfig @@ -9,4 +9,42 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "canyonlands" +choice BOARD_TYPE + prompt "Select which board to build for" + +config CANYONLANDS + bool "Glacier" + help + Select this to build for the Canyonlands 460EX board. + +config GLACIER + bool "Glacier" + help + Select this to build for the Glacier 460GT board. + +config ARCHES + bool "Arches" + help + Select this to build for the Arches dual 460GT board. + +endchoice + +config DISPLAY_BOARDINFO + bool + default y + +config DM + default y + +config DM_SERIAL + default y + +config SYS_MALLOC_F + bool + default y + +config SYS_MALLOC_F_LEN + hex + default 0x400 + endif diff --git a/board/amcc/canyonlands/MAINTAINERS b/board/amcc/canyonlands/MAINTAINERS index 52bf004f6c..8be8a52a3a 100644 --- a/board/amcc/canyonlands/MAINTAINERS +++ b/board/amcc/canyonlands/MAINTAINERS @@ -6,3 +6,4 @@ F: include/configs/canyonlands.h F: configs/arches_defconfig F: configs/canyonlands_defconfig F: configs/glacier_defconfig +F: configs/glacier_ramboot_defconfig diff --git a/board/amcc/canyonlands/config.mk b/board/amcc/canyonlands/config.mk index 63b8973700..5cc90d2050 100644 --- a/board/amcc/canyonlands/config.mk +++ b/board/amcc/canyonlands/config.mk @@ -8,8 +8,6 @@ # AMCC 460EX/460GT Evaluation Board (Canyonlands) board # -PLATFORM_CPPFLAGS += -DCONFIG_440=1 - ifeq ($(debug),1) PLATFORM_CPPFLAGS += -DDEBUG endif diff --git a/board/amcc/canyonlands/u-boot-ram.lds b/board/amcc/canyonlands/u-boot-ram.lds new file mode 100644 index 0000000000..1750c74a19 --- /dev/null +++ b/board/amcc/canyonlands/u-boot-ram.lds @@ -0,0 +1,85 @@ +/* + * (C) Copyright 2009 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +OUTPUT_ARCH(powerpc) +SECTIONS +{ + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .text : + { + _image_copy_start = .; + arch/powerpc/cpu/ppc4xx/start.o (.text*) + board/amcc/canyonlands/init.o (.text*) + + *(.text*) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) + } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + KEEP(*(.got)) + _GOT2_TABLE_ = .; + KEEP(*(.got2)) + _FIXUP_TABLE_ = .; + KEEP(*(.fixup)) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data*) + *(.sdata*) + } + _edata = .; + PROVIDE (edata = .); + + . = .; + + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { + *(.data.init) + . = ALIGN(256); + LONG(0) LONG(0) /* Extend u-boot.bin to here */ + } + __init_end = .; + _end = .; + _image_binary_end = .; + + __bss_start = .; + .bss (NOLOAD) : + { + *(.bss*) + *(.sbss*) + *(COMMON) + . = ALIGN(4); + } + + __bss_end = . ; + PROVIDE (end = .); +} diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 67ac260055..8330bb64bd 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -321,8 +321,8 @@ static void enable_lvds(struct display_info_t const *dev) /* enable backlight PWM 3 */ if (pwm_init(2, 0, 0)) goto error; - /* duty cycle 200ns, period: 3000ns */ - if (pwm_config(2, 200, 3000)) + /* duty cycle 500ns, period: 3000ns */ + if (pwm_config(2, 500, 3000)) goto error; if (pwm_enable(2)) goto error; @@ -350,8 +350,8 @@ struct display_info_t const displays[] = { .right_margin = 88, .upper_margin = 10, .lower_margin = 10, - .hsync_len = 25, - .vsync_len = 1, + .hsync_len = 80, + .vsync_len = 25, .sync = 0, .vmode = FB_VMODE_NONINTERLACED } diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig index 7ebea6317f..7d5e7bee8b 100644 --- a/board/armltd/vexpress64/Kconfig +++ b/board/armltd/vexpress64/Kconfig @@ -1,4 +1,30 @@ -if TARGET_VEXPRESS_AEMV8A +if TARGET_VEXPRESS64_AEMV8A + +config SYS_BOARD + default "vexpress64" + +config SYS_VENDOR + default "armltd" + +config SYS_CONFIG_NAME + default "vexpress_aemv8a" + +endif + +if TARGET_VEXPRESS64_BASE_FVP + +config SYS_BOARD + default "vexpress64" + +config SYS_VENDOR + default "armltd" + +config SYS_CONFIG_NAME + default "vexpress_aemv8a" + +endif + +if TARGET_VEXPRESS64_JUNO config SYS_BOARD default "vexpress64" diff --git a/board/armltd/vexpress64/MAINTAINERS b/board/armltd/vexpress64/MAINTAINERS index 66c8dffa16..0ba044d7ff 100644 --- a/board/armltd/vexpress64/MAINTAINERS +++ b/board/armltd/vexpress64/MAINTAINERS @@ -9,3 +9,8 @@ VEXPRESS_AEMV8A_SEMI BOARD M: Linus Walleij <linus.walleij@linaro.org> S: Maintained F: configs/vexpress_aemv8a_semi_defconfig + +JUNO DEVELOPMENT PLATFORM BOARD +M: Linus Walleij <linus.walleij@linaro.org> +S: Maintained +F: configs/vexpress_aemv8a_juno_defconfig diff --git a/board/atmel/at91rm9200ek/Kconfig b/board/atmel/at91rm9200ek/Kconfig index bad4a37da0..952351dcdb 100644 --- a/board/atmel/at91rm9200ek/Kconfig +++ b/board/atmel/at91rm9200ek/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "atmel" -config SYS_SOC - default "at91" - config SYS_CONFIG_NAME default "at91rm9200ek" diff --git a/board/atmel/at91sam9260ek/Kconfig b/board/atmel/at91sam9260ek/Kconfig index fe00ed5e60..3844f086b4 100644 --- a/board/atmel/at91sam9260ek/Kconfig +++ b/board/atmel/at91sam9260ek/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "atmel" -config SYS_SOC - default "at91" - config SYS_CONFIG_NAME default "at91sam9260ek" diff --git a/board/atmel/at91sam9261ek/Kconfig b/board/atmel/at91sam9261ek/Kconfig index d839c1a632..2971b3cf9f 100644 --- a/board/atmel/at91sam9261ek/Kconfig +++ b/board/atmel/at91sam9261ek/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "atmel" -config SYS_SOC - default "at91" - config SYS_CONFIG_NAME default "at91sam9261ek" diff --git a/board/atmel/at91sam9263ek/Kconfig b/board/atmel/at91sam9263ek/Kconfig index 311c504da2..3f0873fe51 100644 --- a/board/atmel/at91sam9263ek/Kconfig +++ b/board/atmel/at91sam9263ek/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "atmel" -config SYS_SOC - default "at91" - config SYS_CONFIG_NAME default "at91sam9263ek" diff --git a/board/atmel/at91sam9m10g45ek/Kconfig b/board/atmel/at91sam9m10g45ek/Kconfig index 1bc086a483..211c411ef6 100644 --- a/board/atmel/at91sam9m10g45ek/Kconfig +++ b/board/atmel/at91sam9m10g45ek/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "atmel" -config SYS_SOC - default "at91" - config SYS_CONFIG_NAME default "at91sam9m10g45ek" diff --git a/board/atmel/at91sam9n12ek/Kconfig b/board/atmel/at91sam9n12ek/Kconfig index cf1d1a3670..816003a5de 100644 --- a/board/atmel/at91sam9n12ek/Kconfig +++ b/board/atmel/at91sam9n12ek/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "atmel" -config SYS_SOC - default "at91" - config SYS_CONFIG_NAME default "at91sam9n12ek" diff --git a/board/atmel/at91sam9rlek/Kconfig b/board/atmel/at91sam9rlek/Kconfig index 438d300421..81a839ac03 100644 --- a/board/atmel/at91sam9rlek/Kconfig +++ b/board/atmel/at91sam9rlek/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "atmel" -config SYS_SOC - default "at91" - config SYS_CONFIG_NAME default "at91sam9rlek" diff --git a/board/atmel/at91sam9x5ek/Kconfig b/board/atmel/at91sam9x5ek/Kconfig index 5c5ec61577..3f92754fb9 100644 --- a/board/atmel/at91sam9x5ek/Kconfig +++ b/board/atmel/at91sam9x5ek/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "atmel" -config SYS_SOC - default "at91" - config SYS_CONFIG_NAME default "at91sam9x5ek" diff --git a/board/atmel/atngw100/atngw100.c b/board/atmel/atngw100/atngw100.c index 03d767a4a8..dacd427831 100644 --- a/board/atmel/atngw100/atngw100.c +++ b/board/atmel/atngw100/atngw100.c @@ -18,14 +18,14 @@ DECLARE_GLOBAL_DATA_PTR; struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { { - .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT, - .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT, - .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT) + .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT, + .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT, + .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT) | MMU_VMR_CACHE_NONE, }, { - .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT, - .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT, - .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT) + .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT, + .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT, + .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT) | MMU_VMR_CACHE_WRBACK, }, }; @@ -52,6 +52,8 @@ int board_early_init_f(void) hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); portmux_enable_ebi(16, 23, 0, PORTMUX_DRIVE_HIGH); + sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config); + portmux_enable_usart1(PORTMUX_DRIVE_MIN); #if defined(CONFIG_MACB) @@ -68,24 +70,6 @@ int board_early_init_f(void) return 0; } -phys_size_t initdram(int board_type) -{ - unsigned long expected_size; - unsigned long actual_size; - void *sdram_base; - - sdram_base = uncached(EBI_SDRAM_BASE); - - expected_size = sdram_init(sdram_base, &sdram_config); - actual_size = get_ram_size(sdram_base, expected_size); - - if (expected_size != actual_size) - printf("Warning: Only %lu of %lu MiB SDRAM is working\n", - actual_size >> 20, expected_size >> 20); - - return actual_size; -} - int board_early_init_r(void) { gd->bd->bi_phy_id[0] = 0x01; diff --git a/board/atmel/atngw100mkii/atngw100mkii.c b/board/atmel/atngw100mkii/atngw100mkii.c index 72d19e430e..8e215d5fcf 100644 --- a/board/atmel/atngw100mkii/atngw100mkii.c +++ b/board/atmel/atngw100mkii/atngw100mkii.c @@ -23,21 +23,21 @@ DECLARE_GLOBAL_DATA_PTR; struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { { /* Atmel AT49BV640D 8 MiB x16 NOR flash on NCS0 */ - .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT, - .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT, - .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT) + .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT, + .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT, + .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT) | MMU_VMR_CACHE_NONE, }, { /* Micron MT29F2G16AAD 256 MiB x16 NAND flash on NCS3 */ - .virt_pgno = EBI_SRAM_CS3_BASE >> PAGE_SHIFT, - .nr_pages = EBI_SRAM_CS3_SIZE >> PAGE_SHIFT, - .phys = (EBI_SRAM_CS3_BASE >> PAGE_SHIFT) + .virt_pgno = EBI_SRAM_CS3_BASE >> MMU_PAGE_SHIFT, + .nr_pages = EBI_SRAM_CS3_SIZE >> MMU_PAGE_SHIFT, + .phys = (EBI_SRAM_CS3_BASE >> MMU_PAGE_SHIFT) | MMU_VMR_CACHE_NONE, }, { /* 2x16-bit ISSI IS42S16320B 64 MiB SDRAM (128 MiB total) */ - .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT, - .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT, - .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT) + .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT, + .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT, + .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT) | MMU_VMR_CACHE_WRBACK, }, }; @@ -69,6 +69,9 @@ int board_early_init_f(void) portmux_select_gpio(PORTMUX_PORT_E, 1 << 23, PORTMUX_DIR_OUTPUT | PORTMUX_INIT_HIGH | PORTMUX_DRIVE_MIN); + + sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config); + portmux_enable_usart1(PORTMUX_DRIVE_MIN); #if defined(CONFIG_MACB) @@ -85,24 +88,6 @@ int board_early_init_f(void) return 0; } -phys_size_t initdram(int board_type) -{ - unsigned long expected_size; - unsigned long actual_size; - void *sdram_base; - - sdram_base = uncached(EBI_SDRAM_BASE); - - expected_size = sdram_init(sdram_base, &sdram_config); - actual_size = get_ram_size(sdram_base, expected_size); - - if (expected_size != actual_size) - printf("Warning: Only %lu of %lu MiB SDRAM is working\n", - actual_size >> 20, expected_size >> 20); - - return actual_size; -} - int board_early_init_r(void) { gd->bd->bi_phy_id[0] = 0x01; diff --git a/board/atmel/atstk1000/atstk1000.c b/board/atmel/atstk1000/atstk1000.c index 4b6b90f683..fd4363bece 100644 --- a/board/atmel/atstk1000/atstk1000.c +++ b/board/atmel/atstk1000/atstk1000.c @@ -17,14 +17,14 @@ DECLARE_GLOBAL_DATA_PTR; struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { { - .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT, - .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT, - .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT) + .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT, + .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT, + .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT) | MMU_VMR_CACHE_NONE, }, { - .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT, - .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT, - .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT) + .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT, + .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT, + .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT) | MMU_VMR_CACHE_WRBACK, }, }; @@ -78,7 +78,10 @@ int board_early_init_f(void) hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); portmux_enable_ebi(sdram_config.data_bits, 23, 0, PORTMUX_DRIVE_HIGH); + sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config); + portmux_enable_usart1(PORTMUX_DRIVE_MIN); + #if defined(CONFIG_MACB) portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW); portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW); @@ -90,24 +93,6 @@ int board_early_init_f(void) return 0; } -phys_size_t initdram(int board_type) -{ - unsigned long expected_size; - unsigned long actual_size; - void *sdram_base; - - sdram_base = uncached(EBI_SDRAM_BASE); - - expected_size = sdram_init(sdram_base, &sdram_config); - actual_size = get_ram_size(sdram_base, expected_size); - - if (expected_size != actual_size) - printf("Warning: Only %lu of %lu MiB SDRAM is working\n", - actual_size >> 20, expected_size >> 20); - - return actual_size; -} - int board_early_init_r(void) { gd->bd->bi_phy_id[0] = 0x10; diff --git a/board/atmel/sama5d3_xplained/Kconfig b/board/atmel/sama5d3_xplained/Kconfig index 0ba8a7bf93..2df751a264 100644 --- a/board/atmel/sama5d3_xplained/Kconfig +++ b/board/atmel/sama5d3_xplained/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "atmel" -config SYS_SOC - default "at91" - config SYS_CONFIG_NAME default "sama5d3_xplained" diff --git a/board/atmel/sama5d3xek/Kconfig b/board/atmel/sama5d3xek/Kconfig index 2a9ed23ecf..abd1ad81fc 100644 --- a/board/atmel/sama5d3xek/Kconfig +++ b/board/atmel/sama5d3xek/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "atmel" -config SYS_SOC - default "at91" - config SYS_CONFIG_NAME default "sama5d3xek" diff --git a/board/atmel/sama5d4_xplained/Kconfig b/board/atmel/sama5d4_xplained/Kconfig index f320a68d30..2cb03cb178 100644 --- a/board/atmel/sama5d4_xplained/Kconfig +++ b/board/atmel/sama5d4_xplained/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "atmel" -config SYS_SOC - default "at91" - config SYS_CONFIG_NAME default "sama5d4_xplained" diff --git a/board/atmel/sama5d4_xplained/sama5d4_xplained.c b/board/atmel/sama5d4_xplained/sama5d4_xplained.c index 1c5b92c8b5..bc2aa38b92 100644 --- a/board/atmel/sama5d4_xplained/sama5d4_xplained.c +++ b/board/atmel/sama5d4_xplained/sama5d4_xplained.c @@ -10,6 +10,7 @@ #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> +#include <asm/arch/atmel_mpddrc.h> #include <asm/arch/atmel_usba_udc.h> #include <asm/arch/gpio.h> #include <asm/arch/clk.h> @@ -326,3 +327,87 @@ int board_eth_init(bd_t *bis) return rc; } + +/* SPL */ +#ifdef CONFIG_SPL_BUILD +void spl_board_init(void) +{ +#ifdef CONFIG_SYS_USE_MMC + sama5d4_xplained_mci1_hw_init(); +#elif CONFIG_SYS_USE_NANDFLASH + sama5d4_xplained_nand_hw_init(); +#elif CONFIG_SYS_USE_SERIALFLASH + sama5d4_xplained_spi0_hw_init(); +#endif +} + +static void ddr2_conf(struct atmel_mpddr *ddr2) +{ + ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); + + ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_14 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | + ATMEL_MPDDRC_CR_NB_8BANKS | + ATMEL_MPDDRC_CR_NDQS_DISABLED | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | + ATMEL_MPDDRC_CR_UNAL_SUPPORTED); + + ddr2->rtr = 0x2b0; + + ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | + 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | + 3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | + 10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | + 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); + + ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | + 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | + 25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | + 23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); + + ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | + 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | + 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); +} + +void mem_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct atmel_mpddr ddr2; + + ddr2_conf(&ddr2); + + /* enable MPDDR clock */ + at91_periph_clk_enable(ATMEL_ID_MPDDRC); + writel(0x4, &pmc->scer); + + /* DDRAM2 Controller initialize */ + ddr2_init(ATMEL_BASE_DDRCS, &ddr2); +} + +void at91_pmc_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + u32 tmp; + + tmp = AT91_PMC_PLLAR_29 | + AT91_PMC_PLLXR_PLLCOUNT(0x3f) | + AT91_PMC_PLLXR_MUL(87) | + AT91_PMC_PLLXR_DIV(1); + at91_plla_init(tmp); + + writel(0x0 << 8, &pmc->pllicpr); + + tmp = AT91_PMC_MCKR_H32MXDIV | + AT91_PMC_MCKR_PLLADIV_2 | + AT91_PMC_MCKR_MDIV_3 | + AT91_PMC_MCKR_CSS_PLLA; + at91_mck_init(tmp); +} +#endif diff --git a/board/atmel/sama5d4ek/Kconfig b/board/atmel/sama5d4ek/Kconfig index 7dc569c411..1a634032ac 100644 --- a/board/atmel/sama5d4ek/Kconfig +++ b/board/atmel/sama5d4ek/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "atmel" -config SYS_SOC - default "at91" - config SYS_CONFIG_NAME default "sama5d4ek" diff --git a/board/atmel/sama5d4ek/sama5d4ek.c b/board/atmel/sama5d4ek/sama5d4ek.c index d8ff648957..46e504131c 100644 --- a/board/atmel/sama5d4ek/sama5d4ek.c +++ b/board/atmel/sama5d4ek/sama5d4ek.c @@ -10,6 +10,7 @@ #include <asm/arch/at91_common.h> #include <asm/arch/at91_pmc.h> #include <asm/arch/at91_rstc.h> +#include <asm/arch/atmel_mpddrc.h> #include <asm/arch/atmel_usba_udc.h> #include <asm/arch/gpio.h> #include <asm/arch/clk.h> @@ -325,3 +326,87 @@ int board_eth_init(bd_t *bis) return rc; } + +/* SPL */ +#ifdef CONFIG_SPL_BUILD +void spl_board_init(void) +{ +#ifdef CONFIG_SYS_USE_MMC + sama5d4ek_mci1_hw_init(); +#elif CONFIG_SYS_USE_NANDFLASH + sama5d4ek_nand_hw_init(); +#elif CONFIG_SYS_USE_SERIALFLASH + sama5d4ek_spi0_hw_init(); +#endif +} + +static void ddr2_conf(struct atmel_mpddr *ddr2) +{ + ddr2->md = (ATMEL_MPDDRC_MD_DBW_32_BITS | ATMEL_MPDDRC_MD_DDR2_SDRAM); + + ddr2->cr = (ATMEL_MPDDRC_CR_NC_COL_10 | + ATMEL_MPDDRC_CR_NR_ROW_14 | + ATMEL_MPDDRC_CR_CAS_DDR_CAS3 | + ATMEL_MPDDRC_CR_NB_8BANKS | + ATMEL_MPDDRC_CR_NDQS_DISABLED | + ATMEL_MPDDRC_CR_DECOD_INTERLEAVED | + ATMEL_MPDDRC_CR_UNAL_SUPPORTED); + + ddr2->rtr = 0x2b0; + + ddr2->tpr0 = (8 << ATMEL_MPDDRC_TPR0_TRAS_OFFSET | + 3 << ATMEL_MPDDRC_TPR0_TRCD_OFFSET | + 3 << ATMEL_MPDDRC_TPR0_TWR_OFFSET | + 10 << ATMEL_MPDDRC_TPR0_TRC_OFFSET | + 3 << ATMEL_MPDDRC_TPR0_TRP_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TRRD_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TWTR_OFFSET | + 2 << ATMEL_MPDDRC_TPR0_TMRD_OFFSET); + + ddr2->tpr1 = (2 << ATMEL_MPDDRC_TPR1_TXP_OFFSET | + 200 << ATMEL_MPDDRC_TPR1_TXSRD_OFFSET | + 25 << ATMEL_MPDDRC_TPR1_TXSNR_OFFSET | + 23 << ATMEL_MPDDRC_TPR1_TRFC_OFFSET); + + ddr2->tpr2 = (7 << ATMEL_MPDDRC_TPR2_TFAW_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TRTP_OFFSET | + 3 << ATMEL_MPDDRC_TPR2_TRPA_OFFSET | + 2 << ATMEL_MPDDRC_TPR2_TXARDS_OFFSET | + 8 << ATMEL_MPDDRC_TPR2_TXARD_OFFSET); +} + +void mem_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + struct atmel_mpddr ddr2; + + ddr2_conf(&ddr2); + + /* enable MPDDR clock */ + at91_periph_clk_enable(ATMEL_ID_MPDDRC); + writel(0x4, &pmc->scer); + + /* DDRAM2 Controller initialize */ + ddr2_init(ATMEL_BASE_DDRCS, &ddr2); +} + +void at91_pmc_init(void) +{ + struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; + u32 tmp; + + tmp = AT91_PMC_PLLAR_29 | + AT91_PMC_PLLXR_PLLCOUNT(0x3f) | + AT91_PMC_PLLXR_MUL(87) | + AT91_PMC_PLLXR_DIV(1); + at91_plla_init(tmp); + + writel(0x0 << 8, &pmc->pllicpr); + + tmp = AT91_PMC_MCKR_H32MXDIV | + AT91_PMC_MCKR_PLLADIV_2 | + AT91_PMC_MCKR_MDIV_3 | + AT91_PMC_MCKR_CSS_PLLA; + at91_mck_init(tmp); +} +#endif diff --git a/board/avionic-design/common/tamonten-ng.c b/board/avionic-design/common/tamonten-ng.c index 86a0844273..1704627112 100644 --- a/board/avionic-design/common/tamonten-ng.c +++ b/board/avionic-design/common/tamonten-ng.c @@ -55,12 +55,12 @@ void pmu_write(uchar reg, uchar data) struct udevice *dev; int ret; - ret = i2c_get_chip_for_busnum(4, PMU_I2C_ADDRESS, &dev); + ret = i2c_get_chip_for_busnum(4, PMU_I2C_ADDRESS, 1, &dev); if (ret) { debug("%s: Cannot find PMIC I2C chip\n", __func__); return; } - i2c_write(dev, reg, &data, 1); + dm_i2c_write(dev, reg, &data, 1); } /* diff --git a/board/bachmann/ot1200/Makefile b/board/bachmann/ot1200/Makefile index 1bd42e8321..9e50bfeb86 100644 --- a/board/bachmann/ot1200/Makefile +++ b/board/bachmann/ot1200/Makefile @@ -6,4 +6,8 @@ # SPDX-License-Identifier: GPL-2.0+ # +ifdef CONFIG_SPL_BUILD +obj-y := ot1200.o ot1200_spl.o +else obj-y := ot1200.o +endif diff --git a/board/bachmann/ot1200/mx6q_4x_mt41j128.cfg b/board/bachmann/ot1200/mx6q_4x_mt41j128.cfg index bb6c60b4c3..c25f99dcfd 100644 --- a/board/bachmann/ot1200/mx6q_4x_mt41j128.cfg +++ b/board/bachmann/ot1200/mx6q_4x_mt41j128.cfg @@ -142,20 +142,6 @@ DATA 4 0x021b48b8 0x00000800 DATA 4 0x021b001c 0x00000000 DATA 4 0x021b0404 0x00011006 -/* set the default clock gate to save power */ -DATA 4 0x020c4068 0x00C03F3F -DATA 4 0x020c406c 0x0030FC03 -DATA 4 0x020c4070 0x0FFFC000 -DATA 4 0x020c4074 0x3FF00000 -DATA 4 0x020c4078 0x00FFF300 -DATA 4 0x020c407c 0x0F0000C3 -DATA 4 0x020c4080 0x000003FF - -/* enable AXI cache for VDOA/VPU/IPU */ -DATA 4 0x020e0010 0xF00000CF -/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ -DATA 4 0x020e0018 0x007F007F -DATA 4 0x020e001c 0x007F007F /* * Setup CCM_CCOSR register as follows: diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c index 93f3d65176..e434ed9b87 100644 --- a/board/bachmann/ot1200/ot1200.c +++ b/board/bachmann/ot1200/ot1200.c @@ -6,6 +6,7 @@ */ #include <common.h> +#include <asm/io.h> #include <asm/arch/clock.h> #include <asm/arch/imx-regs.h> #include <asm/arch/iomux.h> @@ -16,6 +17,7 @@ #include <asm/imx-common/mxc_i2c.h> #include <asm/imx-common/boot_mode.h> #include <asm/arch/crm_regs.h> +#include <asm/arch/sys_proto.h> #include <mmc.h> #include <fsl_esdhc.h> #include <netdev.h> @@ -46,7 +48,7 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init(void) { - gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + gd->ram_size = imx_ddr_size(); return 0; } @@ -118,8 +120,35 @@ static void setup_iomux_features(void) ARRAY_SIZE(feature_pads)); } +static void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC33, &ccm->CCGR1); + writel(0x0FFFC000, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0x00FFF300, &ccm->CCGR4); + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); +} + +static void gpr_init(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* enable AXI cache for VDOA/VPU/IPU */ + writel(0xF00000CF, &iomux->gpr[4]); + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ + writel(0x007F007F, &iomux->gpr[6]); + writel(0x007F007F, &iomux->gpr[7]); +} + int board_early_init_f(void) { + ccgr_init(); + gpr_init(); + setup_iomux_uart(); setup_iomux_spi(); setup_iomux_features(); @@ -290,9 +319,6 @@ int board_init(void) leds_on(); - /* enable ecspi3 clocks */ - enable_cspi_clock(1, 2); - #ifdef CONFIG_CMD_SATA setup_sata(); #endif diff --git a/board/bachmann/ot1200/ot1200_spl.c b/board/bachmann/ot1200/ot1200_spl.c new file mode 100644 index 0000000000..9c77fd3330 --- /dev/null +++ b/board/bachmann/ot1200/ot1200_spl.c @@ -0,0 +1,162 @@ +/* + * Copyright (C) 2015, Bachmann electronic GmbH + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <spl.h> +#include <asm/arch/mx6-ddr.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Configure MX6Q/DUAL mmdc DDR io registers */ +static struct mx6dq_iomux_ddr_regs ot1200_ddr_ioregs = { + /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 48ohm */ + .dram_sdclk_0 = 0x00000028, + .dram_sdclk_1 = 0x00000028, + .dram_cas = 0x00000028, + .dram_ras = 0x00000028, + .dram_reset = 0x00000028, + /* SDCKE[0:1]: 100k pull-up */ + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + /* SDBA2: pull-up disabled */ + .dram_sdba2 = 0x00000000, + /* SDODT[0:1]: 100k pull-up, 48 ohm */ + .dram_sdodt0 = 0x00000028, + .dram_sdodt1 = 0x00000028, + /* SDQS[0:7]: Differential input, 48 ohm */ + .dram_sdqs0 = 0x00000028, + .dram_sdqs1 = 0x00000028, + .dram_sdqs2 = 0x00000028, + .dram_sdqs3 = 0x00000028, + .dram_sdqs4 = 0x00000028, + .dram_sdqs5 = 0x00000028, + .dram_sdqs6 = 0x00000028, + .dram_sdqs7 = 0x00000028, + /* DQM[0:7]: Differential input, 48 ohm */ + .dram_dqm0 = 0x00000028, + .dram_dqm1 = 0x00000028, + .dram_dqm2 = 0x00000028, + .dram_dqm3 = 0x00000028, + .dram_dqm4 = 0x00000028, + .dram_dqm5 = 0x00000028, + .dram_dqm6 = 0x00000028, + .dram_dqm7 = 0x00000028, +}; + +/* Configure MX6Q/DUAL mmdc GRP io registers */ +static struct mx6dq_iomux_grp_regs ot1200_grp_ioregs = { + /* DDR3 */ + .grp_ddr_type = 0x000c0000, + .grp_ddrmode_ctl = 0x00020000, + /* Disable DDR pullups */ + .grp_ddrpke = 0x00000000, + /* ADDR[00:16], SDBA[0:1]: 48 ohm */ + .grp_addds = 0x00000028, + /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 48 ohm */ + .grp_ctlds = 0x00000028, + /* DATA[00:63]: Differential input, 48 ohm */ + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000028, + .grp_b1ds = 0x00000028, + .grp_b2ds = 0x00000028, + .grp_b3ds = 0x00000028, + .grp_b4ds = 0x00000028, + .grp_b5ds = 0x00000028, + .grp_b6ds = 0x00000028, + .grp_b7ds = 0x00000028, +}; + +static struct mx6_ddr_sysinfo ot1200_ddr_sysinfo = { + /* Width of data bus: 0=16, 1=32, 2=64 */ + .dsize = 2, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 32Gb per CS */ + /* Single chip select */ + .ncs = 1, + .cs1_mirror = 0, /* war 0 */ + .rtt_wr = 1, /* DDR3_RTT_60_OHM - RTT_Wr = RZQ/4 */ + .rtt_nom = 1, /* DDR3_RTT_60_OHM - RTT_Nom = RZQ/4 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ /* war 1 */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ +}; + +/* MT41K128M16JT-125 */ +static struct mx6_ddr3_cfg micron_2gib_1600 = { + .mem_speed = 1600, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, + .SRT = 1, +}; + +static struct mx6_mmdc_calibration micron_2gib_1600_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x00260025, + .p0_mpwldectrl1 = 0x00270021, + .p1_mpwldectrl0 = 0x00180034, + .p1_mpwldectrl1 = 0x00180024, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x04380344, + .p0_mpdgctrl1 = 0x0330032C, + .p1_mpdgctrl0 = 0x0338033C, + .p1_mpdgctrl1 = 0x032C0300, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x3C2E3238, + .p1_mprddlctl = 0x3A2E303C, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x36384036, + .p1_mpwrdlctl = 0x442E4438, +}; + +static void ot1200_spl_dram_init(void) +{ + mx6dq_dram_iocfg(64, &ot1200_ddr_ioregs, &ot1200_grp_ioregs); + mx6_dram_cfg(&ot1200_ddr_sysinfo, µn_2gib_1600_mmdc_calib, + µn_2gib_1600); +} + +/* + * called from C runtime startup code (arch/arm/lib/crt0.S:_main) + * - we have a stack and a place to store GD, both in SRAM + * - no variable global data is available + */ +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + /* iomux and setup of i2c */ + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* configure MMDC for SDRAM width/size and per-model calibration */ + ot1200_spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} + +void reset_cpu(ulong addr) +{ +} diff --git a/board/barco/platinum/Kconfig b/board/barco/platinum/Kconfig new file mode 100644 index 0000000000..8bbad24c0d --- /dev/null +++ b/board/barco/platinum/Kconfig @@ -0,0 +1,37 @@ +if TARGET_PLATINUM_PICON + +config SYS_CPU + default "armv7" + +config SYS_VENDOR + default "barco" + +config SYS_SOC + default "mx6" + +config SYS_BOARD + default "platinum" + +config SYS_CONFIG_NAME + default "platinum_picon" + +endif + +if TARGET_PLATINUM_TITANIUM + +config SYS_CPU + default "armv7" + +config SYS_VENDOR + default "barco" + +config SYS_SOC + default "mx6" + +config SYS_BOARD + default "platinum" + +config SYS_CONFIG_NAME + default "platinum_titanium" + +endif diff --git a/board/barco/platinum/MAINTAINERS b/board/barco/platinum/MAINTAINERS new file mode 100644 index 0000000000..a22584b5e5 --- /dev/null +++ b/board/barco/platinum/MAINTAINERS @@ -0,0 +1,7 @@ +PLATINUM BOARD +M: Stefan Roese <sr@denx.de> +S: Maintained +F: board/barco/platinum/ +F: include/configs/platinum.h +F: configs/platinum_picon_defconfig +F: configs/platinum_titanium_defconfig diff --git a/board/barco/platinum/Makefile b/board/barco/platinum/Makefile new file mode 100644 index 0000000000..abc941914a --- /dev/null +++ b/board/barco/platinum/Makefile @@ -0,0 +1,14 @@ +# +# Copyright (C) 2014, Barco (www.barco.com) +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := platinum.o +obj-$(CONFIG_TARGET_PLATINUM_PICON) += platinum_picon.o +obj-$(CONFIG_TARGET_PLATINUM_TITANIUM) += platinum_titanium.o + +ifneq ($(CONFIG_SPL_BUILD),) +obj-$(CONFIG_TARGET_PLATINUM_PICON) += spl_picon.o +obj-$(CONFIG_TARGET_PLATINUM_TITANIUM) += spl_titanium.o +endif diff --git a/board/barco/platinum/platinum.c b/board/barco/platinum/platinum.c new file mode 100644 index 0000000000..1485a4856f --- /dev/null +++ b/board/barco/platinum/platinum.c @@ -0,0 +1,217 @@ +/* + * Copyright (C) 2014, Barco (www.barco.com) + * Copyright (C) 2014 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/crm_regs.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/boot_mode.h> + +#include "platinum.h" + +DECLARE_GLOBAL_DATA_PTR; + +iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__GPIO7_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ +}; + +iomux_v3_cfg_t nfc_pads[] = { + MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS1__NAND_CE1_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS2__NAND_CE2_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_CS3__NAND_CE3_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +struct fsl_esdhc_cfg usdhc_cfg[] = { + { USDHC3_BASE_ADDR }, +}; + +void setup_gpmi_nand(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + /* config gpmi nand iomux */ + imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); + + /* config gpmi and bch clock to 100 MHz */ + clrsetbits_le32(&mxc_ccm->cs2cdr, + MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | + MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, + MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); + + /* enable gpmi and bch clock gating */ + setbits_le32(&mxc_ccm->CCGR4, + MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | + MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | + MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); + + /* enable apbh clock gating */ + setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); + + return 0; +} + +int board_ehci_hcd_init(int port) +{ + return 0; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + + if (cfg->esdhc_base == usdhc_cfg[0].esdhc_base) { + unsigned sd3_cd = IMX_GPIO_NR(7, 0); + gpio_direction_input(sd3_cd); + return !gpio_get_value(sd3_cd); + } + + return 0; +} + +int board_mmc_init(bd_t *bis) +{ + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +} + +void board_init_gpio(void) +{ + platinum_init_gpio(); +} + +void board_init_gpmi_nand(void) +{ + setup_gpmi_nand(); +} + +void board_init_i2c(void) +{ + platinum_setup_i2c(); +} + +void board_init_spi(void) +{ + platinum_setup_spi(); +} + +void board_init_uart(void) +{ + platinum_setup_uart(); +} + +void board_init_usb(void) +{ + platinum_init_usb(); +} + +void board_init_finished(void) +{ + platinum_init_finished(); +} + +int board_phy_config(struct phy_device *phydev) +{ + return platinum_phy_config(phydev); +} + +int board_eth_init(bd_t *bis) +{ + return cpu_eth_init(bis); +} + +int board_early_init_f(void) +{ + board_init_uart(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + board_init_spi(); + + board_init_i2c(); + + board_init_gpmi_nand(); + + board_init_gpio(); + + board_init_usb(); + + board_init_finished(); + + return 0; +} + +int checkboard(void) +{ + puts("Board: " CONFIG_PLATINUM_BOARD "\n"); + return 0; +} + +static const struct boot_mode board_boot_modes[] = { + /* NAND */ + { "nand", MAKE_CFGVAL(0x80, 0x02, 0x00, 0x00) }, + /* 4 bit bus width */ + { "mmc0", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00) }, + { "mmc1", MAKE_CFGVAL(0x40, 0x38, 0x00, 0x00) }, + { NULL, 0 }, +}; + +int misc_init_r(void) +{ + add_board_boot_modes(board_boot_modes); + + return 0; +} diff --git a/board/barco/platinum/platinum.h b/board/barco/platinum/platinum.h new file mode 100644 index 0000000000..d3ea8bda73 --- /dev/null +++ b/board/barco/platinum/platinum.h @@ -0,0 +1,89 @@ +/* + * Copyright (C) 2014 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _PLATINUM_H_ +#define _PLATINUM_H_ + +#include <miiphy.h> +#include <asm/arch/crm_regs.h> +#include <asm/io.h> + +/* Defines */ + +#define ECSPI1_PAD_CLK (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \ + PAD_CTL_HYS) +#define ECSPI2_PAD_CLK (PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_HYS) +#define ECSPI_PAD_MOSI (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm | \ + PAD_CTL_HYS) +#define ECSPI_PAD_MISO (PAD_CTL_SRE_FAST | PAD_CTL_PUS_100K_DOWN | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_40ohm | \ + PAD_CTL_HYS) +#define ECSPI_PAD_SS (PAD_CTL_SRE_SLOW | PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_120ohm | \ + PAD_CTL_HYS) + +#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + +#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) +#define I2C_PAD_CTRL_SCL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_SLOW) + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | \ + PAD_CTL_HYS) + + +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +#define PC_SCL MUX_PAD_CTRL(I2C_PAD_CTRL_SCL) + +/* Prototypes */ + +int platinum_setup_enet(void); +int platinum_setup_i2c(void); +int platinum_setup_spi(void); +int platinum_setup_uart(void); +int platinum_phy_config(struct phy_device *phydev); +int platinum_init_gpio(void); +int platinum_init_usb(void); +int platinum_init_finished(void); + +static inline void ccgr_init(void) +{ + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0x00C03F3F, &ccm->CCGR0); + writel(0x0030FC03, &ccm->CCGR1); + writel(0x0FFFC000, &ccm->CCGR2); + writel(0x3FF00000, &ccm->CCGR3); + writel(0xFFFFF300, &ccm->CCGR4); /* enable NAND/GPMI/BCH clks */ + writel(0x0F0000C3, &ccm->CCGR5); + writel(0x000003FF, &ccm->CCGR6); +} + +static inline void gpr_init(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + /* enable AXI cache for VDOA/VPU/IPU */ + writel(0xF00000CF, &iomux->gpr[4]); + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ + writel(0x007F007F, &iomux->gpr[6]); + writel(0x007F007F, &iomux->gpr[7]); +} + +#endif /* _PLATINUM_H_ */ diff --git a/board/barco/platinum/platinum_picon.c b/board/barco/platinum/platinum_picon.c new file mode 100644 index 0000000000..b2eab766c5 --- /dev/null +++ b/board/barco/platinum/platinum_picon.c @@ -0,0 +1,244 @@ +/* + * Copyright (C) 2014, Barco (www.barco.com) + * Copyright (C) 2014 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/mxc_i2c.h> +#include <i2c.h> +#include <miiphy.h> + +#include "platinum.h" + +#define GPIO_IP_NCONFIG IMX_GPIO_NR(5, 18) +#define GPIO_HK_NCONFIG IMX_GPIO_NR(7, 13) +#define GPIO_LS_NCONFIG IMX_GPIO_NR(5, 19) + +#define GPIO_I2C0_SEL0 IMX_GPIO_NR(5, 2) +#define GPIO_I2C0_SEL1 IMX_GPIO_NR(1, 11) +#define GPIO_I2C0_ENBN IMX_GPIO_NR(1, 13) + +#define GPIO_I2C2_SEL0 IMX_GPIO_NR(1, 17) +#define GPIO_I2C2_SEL1 IMX_GPIO_NR(1, 20) +#define GPIO_I2C2_ENBN IMX_GPIO_NR(1, 14) + +#define GPIO_USB_RESET IMX_GPIO_NR(1, 5) + +iomux_v3_cfg_t const ecspi1_pads[] = { + MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI1_PAD_CLK), + MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO), + MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI), + MX6_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS), + MX6_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(ECSPI_PAD_SS), + MX6_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(ECSPI_PAD_SS), +}; + +iomux_v3_cfg_t const ecspi2_pads[] = { + MX6_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(ECSPI2_PAD_CLK), + MX6_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO), + MX6_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI), + MX6_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS), + MX6_PAD_EIM_LBA__ECSPI2_SS1 | MUX_PAD_CTRL(ECSPI_PAD_SS), +}; + +iomux_v3_cfg_t const enet_pads[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +/* PHY nRESET */ +iomux_v3_cfg_t const phy_reset_pad = { + MX6_PAD_SD1_DAT2__GPIO1_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart4_pads[] = { + MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT16__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT17__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart5_pads[] = { + MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT18__UART5_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT19__UART5_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const i2c0_mux_pads[] = { + MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD2_CMD__GPIO1_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD2_DAT2__GPIO1_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const i2c2_mux_pads[] = { + MX6_PAD_SD1_DAT1__GPIO1_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_SD2_DAT1__GPIO1_IO14 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +struct i2c_pads_info i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC_SCL, + .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC_SCL, + .gp = IMX_GPIO_NR(5, 27) + }, + .sda = { + .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC, + .gp = IMX_GPIO_NR(5, 26) + } +}; + +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC_SCL, + .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC_SCL, + .gp = IMX_GPIO_NR(1, 3) + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC, + .gp = IMX_GPIO_NR(1, 6) + } +}; + +/* + * This enet related pin-muxing and GPIO handling is done + * in SPL U-Boot. For early initialization. And to give the + * PHY some time to come out of reset before the U-Boot + * ethernet driver tries to access its registers via MDIO. + */ +int platinum_setup_enet(void) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + unsigned phy_reset = IMX_GPIO_NR(1, 19); + + /* First configure PHY reset GPIO pin */ + imx_iomux_v3_setup_pad(phy_reset_pad); + + /* Reconfigure enet muxing while PHY is in reset */ + gpio_direction_output(phy_reset, 0); + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); + mdelay(10); + gpio_set_value(phy_reset, 1); + udelay(100); + + /* set GPIO_16 as ENET_REF_CLK_OUT */ + setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); + + return enable_fec_anatop_clock(ENET_50MHZ); +} + +int platinum_setup_i2c(void) +{ + imx_iomux_v3_setup_multiple_pads(i2c0_mux_pads, + ARRAY_SIZE(i2c0_mux_pads)); + imx_iomux_v3_setup_multiple_pads(i2c2_mux_pads, + ARRAY_SIZE(i2c2_mux_pads)); + + mdelay(10); + + /* Disable i2c mux 0 */ + gpio_direction_output(GPIO_I2C0_SEL0, 0); + gpio_direction_output(GPIO_I2C0_SEL1, 0); + gpio_direction_output(GPIO_I2C0_ENBN, 1); + + /* Disable i2c mux 1 */ + gpio_direction_output(GPIO_I2C2_SEL0, 0); + gpio_direction_output(GPIO_I2C2_SEL1, 0); + gpio_direction_output(GPIO_I2C2_ENBN, 1); + + udelay(10); + + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + + /* Disable all leds */ + i2c_set_bus_num(0); + i2c_reg_write(0x60, 0x05, 0x55); + + return 0; +} + +int platinum_setup_spi(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); + imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads)); + + return 0; +} + +int platinum_setup_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); + imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); + + return 0; +} + +int platinum_phy_config(struct phy_device *phydev) +{ + /* Use generic infrastructure, no specific setup */ + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int platinum_init_gpio(void) +{ + /* Reset FPGA's */ + gpio_direction_output(GPIO_IP_NCONFIG, 0); + gpio_direction_output(GPIO_HK_NCONFIG, 0); + gpio_direction_output(GPIO_LS_NCONFIG, 0); + udelay(3); + gpio_set_value(GPIO_IP_NCONFIG, 1); + gpio_set_value(GPIO_HK_NCONFIG, 1); + gpio_set_value(GPIO_LS_NCONFIG, 1); + + /* no dmd configuration yet */ + + return 0; +} + +int platinum_init_usb(void) +{ + /* Reset usb hub */ + gpio_direction_output(GPIO_USB_RESET, 0); + udelay(100); + gpio_set_value(GPIO_USB_RESET, 1); + + return 0; +} + +int platinum_init_finished(void) +{ + /* Enable led 0 */ + i2c_set_bus_num(0); + i2c_reg_write(0x60, 0x05, 0x54); + + return 0; +} diff --git a/board/barco/platinum/platinum_titanium.c b/board/barco/platinum/platinum_titanium.c new file mode 100644 index 0000000000..73a955f019 --- /dev/null +++ b/board/barco/platinum/platinum_titanium.c @@ -0,0 +1,209 @@ +/* + * Copyright (C) 2014, Barco (www.barco.com) + * Copyright (C) 2014 Stefan Roese <sr@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/mxc_i2c.h> +#include <miiphy.h> +#include <micrel.h> + +#include "platinum.h" + +iomux_v3_cfg_t const ecspi1_pads[] = { + MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(ECSPI1_PAD_CLK), + MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO), + MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI), + MX6_PAD_CSI0_DAT7__ECSPI1_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS), + /* non mounted spi nor flash for booting */ + MX6_PAD_EIM_D19__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_D24__ECSPI1_SS2 | MUX_PAD_CTRL(ECSPI_PAD_SS), + MX6_PAD_EIM_D25__ECSPI1_SS3 | MUX_PAD_CTRL(ECSPI_PAD_SS), +}; + +iomux_v3_cfg_t const ecspi2_pads[] = { + MX6_PAD_EIM_CS0__ECSPI2_SCLK | MUX_PAD_CTRL(ECSPI2_PAD_CLK), + MX6_PAD_EIM_OE__ECSPI2_MISO | MUX_PAD_CTRL(ECSPI_PAD_MISO), + MX6_PAD_EIM_CS1__ECSPI2_MOSI | MUX_PAD_CTRL(ECSPI_PAD_MOSI), + MX6_PAD_EIM_RW__ECSPI2_SS0 | MUX_PAD_CTRL(ECSPI_PAD_SS), +}; + +iomux_v3_cfg_t const enet_pads1[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + /* pin 35 - 1 (PHY_AD2) on reset */ + MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 32 - 1 - (MODE0) all */ + MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 31 - 1 - (MODE1) all */ + MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 28 - 1 - (MODE2) all */ + MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 27 - 1 - (MODE3) all */ + MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 33 - 1 - (CLK125_EN) 125Mhz clockout enabled */ + MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* pin 42 PHY nRST */ + MX6_PAD_EIM_D23__GPIO3_IO23 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const enet_pads2[] = { + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D28__UART2_DTE_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D29__UART2_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart4_pads[] = { + MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT16__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT17__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +struct i2c_pads_info i2c_pad_info0 = { + .scl = { + .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC_SCL, + .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC_SCL, + .gp = IMX_GPIO_NR(5, 27) + }, + .sda = { + .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, + .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC, + .gp = IMX_GPIO_NR(5, 26) + } +}; + +struct i2c_pads_info i2c_pad_info2 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_3__I2C3_SCL | PC_SCL, + .gpio_mode = MX6_PAD_GPIO_3__GPIO1_IO03 | PC_SCL, + .gp = IMX_GPIO_NR(1, 3) + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_GPIO_16__GPIO7_IO11 | PC, + .gp = IMX_GPIO_NR(7, 11) + } +}; + +/* + * This enet related pin-muxing and GPIO handling is done + * in SPL U-Boot. For early initialization. And to give the + * PHY some time to come out of reset before the U-Boot + * ethernet driver tries to access its registers via MDIO. + */ +int platinum_setup_enet(void) +{ + gpio_direction_output(IMX_GPIO_NR(3, 23), 0); + gpio_direction_output(IMX_GPIO_NR(6, 30), 1); + gpio_direction_output(IMX_GPIO_NR(6, 25), 1); + gpio_direction_output(IMX_GPIO_NR(6, 27), 1); + gpio_direction_output(IMX_GPIO_NR(6, 28), 1); + gpio_direction_output(IMX_GPIO_NR(6, 29), 1); + imx_iomux_v3_setup_multiple_pads(enet_pads1, ARRAY_SIZE(enet_pads1)); + gpio_direction_output(IMX_GPIO_NR(6, 24), 1); + + /* Need delay 10ms according to KSZ9021 spec */ + mdelay(10); + gpio_set_value(IMX_GPIO_NR(3, 23), 1); + udelay(100); + + imx_iomux_v3_setup_multiple_pads(enet_pads2, ARRAY_SIZE(enet_pads2)); + + return 0; +} + +int platinum_setup_i2c(void) +{ + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info0); + setup_i2c(2, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info2); + + return 0; +} + +int platinum_setup_spi(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); + imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads)); + + return 0; +} + +int platinum_setup_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); + imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); + + return 0; +} + +int platinum_phy_config(struct phy_device *phydev) +{ + /* min rx data delay */ + ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_RX_DATA_SKEW, + 0x0); + /* min tx data delay */ + ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_TX_DATA_SKEW, + 0x0); + /* max rx/tx clock delay, min rx/tx control */ + ksz9021_phy_extended_write(phydev, MII_KSZ9021_EXT_RGMII_CLOCK_SKEW, + 0xf0f0); + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int platinum_init_gpio(void) +{ + /* Default GPIO's */ + /* Toggle CONFIG_n to reset fpga on every boot */ + gpio_direction_output(IMX_GPIO_NR(5, 18), 0); + /* Need delay >=2uS */ + udelay(3); + gpio_set_value(IMX_GPIO_NR(5, 18), 1); + + /* Default pin 1,15 high - DLP_FLASH_WPZ */ + gpio_direction_output(IMX_GPIO_NR(1, 15), 1); + + return 0; +} + +int platinum_init_usb(void) +{ + return 0; +} + +int platinum_init_finished(void) +{ + return 0; +} diff --git a/board/barco/platinum/spl_picon.c b/board/barco/platinum/spl_picon.c new file mode 100644 index 0000000000..f421c2108c --- /dev/null +++ b/board/barco/platinum/spl_picon.c @@ -0,0 +1,182 @@ +/* + * Copyright (C) 2014 Stefan Roese <sr@denx.de> + * + * Based on: gw_ventana_spl.c which is: + * Copyright (C) 2014 Gateworks Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <asm/io.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-ddr.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/mxc_i2c.h> +#include <spl.h> + +#include "platinum.h" + +DECLARE_GLOBAL_DATA_PTR; + +#undef RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */ + +/* Configure MX6Q/DUAL mmdc DDR io registers */ +struct mx6sdl_iomux_ddr_regs mx6sdl_ddr_ioregs = { + /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ + .dram_sdclk_0 = 0x00020030, + .dram_sdclk_1 = 0x00020030, + .dram_cas = 0x00020030, + .dram_ras = 0x00020030, + .dram_reset = 0x00020030, + /* SDCKE[0:1]: 100k pull-up */ + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + /* SDBA2: pull-up disabled */ + .dram_sdba2 = 0x00000000, + /* SDODT[0:1]: 100k pull-up, 40 ohm */ + .dram_sdodt0 = 0x00003030, + .dram_sdodt1 = 0x00003030, + /* SDQS[0:7]: Differential input, 40 ohm */ + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_sdqs2 = 0x00000030, + .dram_sdqs3 = 0x00000030, + .dram_sdqs4 = 0x00000030, + .dram_sdqs5 = 0x00000030, + .dram_sdqs6 = 0x00000030, + .dram_sdqs7 = 0x00000030, + /* DQM[0:7]: Differential input, 40 ohm */ + .dram_dqm0 = 0x00020030, + .dram_dqm1 = 0x00020030, + .dram_dqm2 = 0x00020030, + .dram_dqm3 = 0x00020030, + .dram_dqm4 = 0x00020030, + .dram_dqm5 = 0x00020030, + .dram_dqm6 = 0x00020030, + .dram_dqm7 = 0x00020030, +}; + +/* Configure MX6Q/DUAL mmdc GRP io registers */ +struct mx6sdl_iomux_grp_regs mx6sdl_grp_ioregs = { + /* DDR3 */ + .grp_ddr_type = 0x000c0000, + .grp_ddrmode_ctl = 0x00020000, + /* disable DDR pullups */ + .grp_ddrpke = 0x00000000, + /* ADDR[00:16], SDBA[0:1]: 40 ohm */ + .grp_addds = 0x00000030, + /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ + .grp_ctlds = 0x00000030, + /* DATA[00:63]: Differential input, 40 ohm */ + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_b2ds = 0x00000030, + .grp_b3ds = 0x00000030, + .grp_b4ds = 0x00000030, + .grp_b5ds = 0x00000030, + .grp_b6ds = 0x00000030, + .grp_b7ds = 0x00000030, +}; + +/* MT41K256M16HA-125 */ +static struct mx6_ddr3_cfg mt41k256m16ha_125 = { + .mem_speed = 1600, + .density = 4, /* 4Gbit */ + .width = 16, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +/* + * Values from running the Freescale DDR stress tool via USB + */ +static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { + /* write leveling calibration determine */ + .p0_mpwldectrl0 = 0x0044004E, + .p0_mpwldectrl1 = 0x001F0023, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x02480248, + .p0_mpdgctrl1 = 0x0210021C, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x42444444, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x36322C32, +}; + +static void spl_dram_init(int width) +{ + struct mx6_ddr3_cfg *mem = &mt41k256m16ha_125; + struct mx6_ddr_sysinfo sysinfo = { + /* width of data bus:0=16,1=32,2=64 */ + .dsize = width / 32, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 32Gb per CS */ + /* single chip select */ + .ncs = 1, + .cs1_mirror = 1, + .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ +#ifdef RTT_NOM_120OHM + .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ +#else + .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ +#endif + .walat = 0, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + }; + + mx6sdl_dram_iocfg(width, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); + mx6_dram_cfg(&sysinfo, &mx6dq_mmdc_calib, mem); +} + +/* + * Called from C runtime startup code (arch/arm/lib/crt0.S:_main) + * - we have a stack and a place to store GD, both in SRAM + * - no variable global data is available + */ +void board_init_f(ulong dummy) +{ + /* Setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + gpr_init(); + + /* UART iomux */ + board_early_init_f(); + + /* Setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* Init DDR with 32bit width */ + spl_dram_init(32); + + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* + * Setup enet related MUXing early to give the PHY + * some time to wake-up from reset + */ + platinum_setup_enet(); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} diff --git a/board/barco/platinum/spl_titanium.c b/board/barco/platinum/spl_titanium.c new file mode 100644 index 0000000000..26fe26ba2b --- /dev/null +++ b/board/barco/platinum/spl_titanium.c @@ -0,0 +1,185 @@ +/* + * Copyright (C) 2014 Stefan Roese <sr@denx.de> + * + * Based on: gw_ventana_spl.c which is: + * Copyright (C) 2014 Gateworks Corporation + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <i2c.h> +#include <asm/io.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-ddr.h> +#include <asm/arch/mx6-pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/iomux-v3.h> +#include <asm/imx-common/mxc_i2c.h> +#include <spl.h> + +#include "platinum.h" + +DECLARE_GLOBAL_DATA_PTR; + +#undef RTT_NOM_120OHM /* use 120ohm Rtt_nom vs 60ohm (lower power) */ + +/* Configure MX6Q/DUAL mmdc DDR io registers */ +struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { + /* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */ + .dram_sdclk_0 = 0x00020030, + .dram_sdclk_1 = 0x00020030, + .dram_cas = 0x00020030, + .dram_ras = 0x00020030, + .dram_reset = 0x00020030, + /* SDCKE[0:1]: 100k pull-up */ + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + /* SDBA2: pull-up disabled */ + .dram_sdba2 = 0x00000000, + /* SDODT[0:1]: 100k pull-up, 40 ohm */ + .dram_sdodt0 = 0x00003030, + .dram_sdodt1 = 0x00003030, + /* SDQS[0:7]: Differential input, 40 ohm */ + .dram_sdqs0 = 0x00000030, + .dram_sdqs1 = 0x00000030, + .dram_sdqs2 = 0x00000030, + .dram_sdqs3 = 0x00000030, + .dram_sdqs4 = 0x00000030, + .dram_sdqs5 = 0x00000030, + .dram_sdqs6 = 0x00000030, + .dram_sdqs7 = 0x00000030, + /* DQM[0:7]: Differential input, 40 ohm */ + .dram_dqm0 = 0x00020030, + .dram_dqm1 = 0x00020030, + .dram_dqm2 = 0x00020030, + .dram_dqm3 = 0x00020030, + .dram_dqm4 = 0x00020030, + .dram_dqm5 = 0x00020030, + .dram_dqm6 = 0x00020030, + .dram_dqm7 = 0x00020030, +}; + +/* Configure MX6Q/DUAL mmdc GRP io registers */ +struct mx6dq_iomux_grp_regs mx6dq_grp_ioregs = { + /* DDR3 */ + .grp_ddr_type = 0x000c0000, + .grp_ddrmode_ctl = 0x00020000, + /* disable DDR pullups */ + .grp_ddrpke = 0x00000000, + /* ADDR[00:16], SDBA[0:1]: 40 ohm */ + .grp_addds = 0x00000030, + /* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */ + .grp_ctlds = 0x00000030, + /* DATA[00:63]: Differential input, 40 ohm */ + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000030, + .grp_b1ds = 0x00000030, + .grp_b2ds = 0x00000030, + .grp_b3ds = 0x00000030, + .grp_b4ds = 0x00000030, + .grp_b5ds = 0x00000030, + .grp_b6ds = 0x00000030, + .grp_b7ds = 0x00000030, +}; + +/* MT41J128M16JT-125 */ +static struct mx6_ddr3_cfg mt41j128m16jt_125 = { + .mem_speed = 1600, + .density = 2, + .width = 16, + .banks = 8, + .rowaddr = 14, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +static struct mx6_mmdc_calibration mx6dq_mmdc_calib = { + /* Write leveling calibration determine */ + .p0_mpwldectrl0 = 0x001f001f, + .p0_mpwldectrl1 = 0x001f001f, + .p1_mpwldectrl0 = 0x00440044, + .p1_mpwldectrl1 = 0x00440044, + /* Read DQS Gating calibration */ + .p0_mpdgctrl0 = 0x434b0350, + .p0_mpdgctrl1 = 0x034c0359, + .p1_mpdgctrl0 = 0x434b0350, + .p1_mpdgctrl1 = 0x03650348, + /* Read Calibration: DQS delay relative to DQ read access */ + .p0_mprddlctl = 0x4436383b, + .p1_mprddlctl = 0x39393341, + /* Write Calibration: DQ/DM delay relative to DQS write access */ + .p0_mpwrdlctl = 0x35373933, + .p1_mpwrdlctl = 0x48254a36, +}; + +static void spl_dram_init(int width) +{ + struct mx6_ddr3_cfg *mem = &mt41j128m16jt_125; + struct mx6_ddr_sysinfo sysinfo = { + /* width of data bus:0=16,1=32,2=64 */ + .dsize = width / 32, + /* config for full 4GB range so that get_mem_size() works */ + .cs_density = 32, /* 32Gb per CS */ + /* single chip select */ + .ncs = 1, + .cs1_mirror = 1, + .rtt_wr = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Wr = RZQ/4 */ +#ifdef RTT_NOM_120OHM + .rtt_nom = 2 /*DDR3_RTT_120_OHM*/, /* RTT_Nom = RZQ/2 */ +#else + .rtt_nom = 1 /*DDR3_RTT_60_OHM*/, /* RTT_Nom = RZQ/4 */ +#endif + .walat = 0, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + }; + + mx6dq_dram_iocfg(width, &mx6dq_ddr_ioregs, &mx6dq_grp_ioregs); + mx6_dram_cfg(&sysinfo, &mx6dq_mmdc_calib, mem); +} + +/* + * Called from C runtime startup code (arch/arm/lib/crt0.S:_main) + * - we have a stack and a place to store GD, both in SRAM + * - no variable global data is available + */ +void board_init_f(ulong dummy) +{ + /* Setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + gpr_init(); + + /* UART iomux */ + board_early_init_f(); + + /* Setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* Init DDR with 32bit width */ + spl_dram_init(32); + + /* Clear the BSS */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* + * Setup enet related MUXing early to give the PHY + * some time to wake-up from reset + */ + platinum_setup_enet(); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); +} diff --git a/board/bluewater/snapper9260/Kconfig b/board/bluewater/snapper9260/Kconfig index c896c46895..b8e9cbc585 100644 --- a/board/bluewater/snapper9260/Kconfig +++ b/board/bluewater/snapper9260/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "bluewater" -config SYS_SOC - default "at91" - config SYS_CONFIG_NAME default "snapper9260" diff --git a/board/buffalo/lsxl/README b/board/buffalo/lsxl/README new file mode 100644 index 0000000000..ef5ed42880 --- /dev/null +++ b/board/buffalo/lsxl/README @@ -0,0 +1,139 @@ +Intro +----- +The Buffalo Linkstation Pro/Live, codename LS-XHL and LS-CHLv2, is a single +disk NAS server. The PCBs of the LS-XHL and LS-CHLv2 are almost the same. +The LS-XHL has a faster CPU and more RAM with a wider data bus, therefore +the LS-XHL PCB has two SDRAM chips. Both have a Kirkwood CPU (Marvell +88F6281). The only on-board storage is a 4 Mbit SPI flash which stores the +bootloader and its environment. The linux kernel and the initial ramdisk +are loaded from the hard disk. + + +Rescue Mode +----------- +These linkstations don't have a populated serial port. There is no way to +access an (unmodified) board other than using the netconsole. If you want +to recover from a bad environment setting or an empty environment, you can +do this only with a working network connection. + +Therefore, on entering the resuce mode, a random ethernet address is +generated if no valid address could be loaded from the environment variable +'ethaddr' and a DHCP request is sent. After a successful DHCP response is +received, the network settings are configured and the ncip is unset. Thus +all netconsole packets are broadcasted and you can use the netconsole to +access board from any host within the network segment. To determine the IP +address assigned to the board, you either have to sniff the traffic or +check the logs/leases of your DHCP server. + +The resuce mode is selected by holding the push button for at least one +second, while powering-on the device. The status LED turns solid amber if +the resuce mode is enabled, thus providing a visual feedback. + +Pressing the same button for at least 10 seconds on power-up will erase the +environment and reset the board. In this case the visual indication will +be: +- blinking blue, for about one second +- solid amber, for about nine seconds +- blinking amber, until you release the button + +This ensures, that you still can recover a device with a broken +environment by first erasing the environment and then entering the rescue +mode. + +Once the rescue mode is started, use the ncb binary from the tools/ +directory to access your board. There is a helper script named +'restore_env' to save your changes. It unsets all the network variables +which were set by the rescue mode, saves your changes and then resets the +board. + +The common use case for this is setting a MAC address. Let us assume you +have an empty environment, the board comes up with the amber LED blinking. +Then you enter the rescue mode, connect to the board with the ncb tool and +use the following commands to set your MAC address: + + setenv ethaddr 00:00:00:00:00:00 + run restore_env + +Of course you need to replace the 00:00:00:00:00:00 with your valid MAC +address, which can be found on a sticker on the bottom of your box. + + +Status LED +---------- +blinking blue + Bootloader is running normally. + +blinking amber + No ethaddr set. Use the `Rescue Mode` to set one. + +blinking red + Something bad happend during loading the operating system. + +The default behavior of the linux kernel is to turn on the blue LED. So if +the blinking blue LED changes to solid blue the kernel was loaded +successfully. + + +Power-on Switch +--------------- +The power-on switch is a software switch. If it is not in ON position when +the bootloader starts, the bootloader will disable the HDD and USB power +and stop the fan. Then it loops until the switch is in ON position again, +enables the power and fan again and continue booting. + + +Boot sources +------------ +The environment defines several different boot sources: + +legacy + This is the default boot source. It loads the kernel and ramdisk from the + attached HDD using the original filenames. The load addresses were + modified to support loading larger kernels. But it should behave the same + as the original bootloader. + +hdd + Use this for new-style booting. Loads three files /vmlinuz, /initrd.img + and /dtb from the boot partition. This should work out of the box if you + have debian and the flash-kernel package installed. + +usb + Same as hdd expect, that the files are loaded from an attached USB mass + storage device and the filename for the device tree is kirkwood-lsxhl.dtb + (or kirkwood-lschlv2.dtb). + +net + Same as usb expect, that the file are loaded from the network. + +rescue + Automatically activated if the push button is pressed for at least one + second on power-up. Does a DHCP request and enables the network console. + See `Rescue Mode` for more information. + +You can change the boot source by setting the 'bootsource' variable to the +corresponding value. Please note, that the restore_env script will the the +bootsource back to 'legacy'. + + +Flash map +--------- +00000 - 5ffff u-boot +60000 - 6ffff reserved, may be used to store dtb +70000 - 7ffff u-boot environment + + +Compiling +--------- +make lsxhl_config (or lschlv2_config) +make u-boot.kwb + + +Update your board +----------------- +Just flash the resulting u-boot.kwb to the beginning of the SPI flash. If +you already have a bootloader CLI, you can use the following commands: + + sf probe 0 + bootp ${loadaddr} u-boot.kwb + sf erase 0 +${filelen} + sf write 0 ${fileaddr} ${filesize} diff --git a/board/calao/sbc35_a9g20/Kconfig b/board/calao/sbc35_a9g20/Kconfig index fb5a1a3f42..37ecfb5f7d 100644 --- a/board/calao/sbc35_a9g20/Kconfig +++ b/board/calao/sbc35_a9g20/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "calao" -config SYS_SOC - default "at91" - config SYS_CONFIG_NAME default "sbc35_a9g20" diff --git a/board/calao/tny_a9260/Kconfig b/board/calao/tny_a9260/Kconfig index b1de8f8ba8..2b663298f3 100644 --- a/board/calao/tny_a9260/Kconfig +++ b/board/calao/tny_a9260/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "calao" -config SYS_SOC - default "at91" - config SYS_CONFIG_NAME default "tny_a9260" diff --git a/board/calao/usb_a9263/Kconfig b/board/calao/usb_a9263/Kconfig index 7a159dc3ba..19e446ded5 100644 --- a/board/calao/usb_a9263/Kconfig +++ b/board/calao/usb_a9263/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "calao" -config SYS_SOC - default "at91" - config SYS_CONFIG_NAME default "usb_a9263" diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index 84e36439fa..ae6945ba9c 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -15,19 +15,86 @@ #include <netdev.h> #include <fdt_support.h> #include <sata.h> +#include <splash.h> #include <asm/arch/crm_regs.h> #include <asm/arch/sys_proto.h> #include <asm/arch/iomux.h> +#include <asm/arch/mxc_hdmi.h> #include <asm/imx-common/mxc_i2c.h> #include <asm/imx-common/sata.h> +#include <asm/imx-common/video.h> #include <asm/io.h> #include <asm/gpio.h> #include <dm/platform_data/serial_mxc.h> #include "common.h" #include "../common/eeprom.h" +#include "../common/common.h" DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_SPLASH_SCREEN +static struct splash_location cm_fx6_splash_locations[] = { + { + .name = "sf", + .storage = SPLASH_STORAGE_SF, + .offset = 0x100000, + }, +}; + +int splash_screen_prepare(void) +{ + return splash_source_load(cm_fx6_splash_locations, + ARRAY_SIZE(cm_fx6_splash_locations)); +} +#endif + +#ifdef CONFIG_IMX_HDMI +static void cm_fx6_enable_hdmi(struct display_info_t const *dev) +{ + imx_enable_hdmi_phy(); +} + +struct display_info_t const displays[] = { + { + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = detect_hdmi, + .enable = cm_fx6_enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 40385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED, + } + }, +}; +size_t display_count = ARRAY_SIZE(displays); + +static void cm_fx6_setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + int reg; + + enable_ipu_clock(); + imx_setup_hdmi(); + reg = __raw_readl(&mxc_ccm->CCGR3); + reg |= MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK; + writel(reg, &mxc_ccm->CCGR3); +} +#else +static inline void cm_fx6_setup_display(void) {} +#endif /* CONFIG_VIDEO_IPUV3 */ + #ifdef CONFIG_DWC_AHSATA static int cm_fx6_issd_gpios[] = { /* The order of the GPIOs in the array is important! */ @@ -345,32 +412,36 @@ static iomux_v3_cfg_t const enet_pads[] = { MUX_PAD_CTRL(ENET_PAD_CTRL)), }; -static int handle_mac_address(void) +static int handle_mac_address(char *env_var, uint eeprom_bus) { unsigned char enetaddr[6]; int rc; - rc = eth_getenv_enetaddr("ethaddr", enetaddr); + rc = eth_getenv_enetaddr(env_var, enetaddr); if (rc) return 0; - rc = cl_eeprom_read_mac_addr(enetaddr); + rc = cl_eeprom_read_mac_addr(enetaddr, eeprom_bus); if (rc) return rc; if (!is_valid_ether_addr(enetaddr)) return -1; - return eth_setenv_enetaddr("ethaddr", enetaddr); + return eth_setenv_enetaddr(env_var, enetaddr); } +#define SB_FX6_I2C_EEPROM_BUS 0 +#define NO_MAC_ADDR "No MAC address found for %s\n" int board_eth_init(bd_t *bis) { int err; - err = handle_mac_address(); - if (err) - puts("No MAC address found\n"); + if (handle_mac_address("ethaddr", CONFIG_SYS_I2C_EEPROM_BUS)) + printf(NO_MAC_ADDR, "primary NIC"); + + if (handle_mac_address("eth1addr", SB_FX6_I2C_EEPROM_BUS)) + printf(NO_MAC_ADDR, "secondary NIC"); SETUP_IOMUX_PADS(enet_pads); /* phy reset */ @@ -464,7 +535,13 @@ int ft_board_setup(void *blob, bd_t *bd) /* MAC addr */ if (eth_getenv_enetaddr("ethaddr", enetaddr)) { - fdt_find_and_setprop(blob, "/fec", "local-mac-address", + fdt_find_and_setprop(blob, + "/soc/aips-bus@02100000/ethernet@02188000", + "local-mac-address", enetaddr, 6, 1); + } + + if (eth_getenv_enetaddr("eth1addr", enetaddr)) { + fdt_find_and_setprop(blob, "/eth@pcie", "local-mac-address", enetaddr, 6, 1); } @@ -506,6 +583,8 @@ int board_init(void) if (ret) printf("Warning: I2C setup failed: %d\n", ret); + cm_fx6_setup_display(); + return 0; } diff --git a/board/compulab/cm_t335/Kconfig b/board/compulab/cm_t335/Kconfig index 683efde764..aadbfbc84d 100644 --- a/board/compulab/cm_t335/Kconfig +++ b/board/compulab/cm_t335/Kconfig @@ -12,4 +12,13 @@ config SYS_SOC config SYS_CONFIG_NAME default "cm_t335" +config DM + default y if !SPL_BUILD + +config DM_GPIO + default y if !SPL_BUILD + +config DM_SERIAL + default y if !SPL_BUILD + endif diff --git a/board/compulab/cm_t335/cm_t335.c b/board/compulab/cm_t335/cm_t335.c index 9583149bed..592ef3d30f 100644 --- a/board/compulab/cm_t335/cm_t335.c +++ b/board/compulab/cm_t335/cm_t335.c @@ -110,7 +110,7 @@ static int handle_mac_address(void) if (rv) return 0; - rv = cl_eeprom_read_mac_addr(enetaddr); + rv = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS); if (rv) get_efuse_mac_addr(enetaddr); diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c index 43463d5b47..c4ea8ea875 100644 --- a/board/compulab/cm_t35/cm_t35.c +++ b/board/compulab/cm_t35/cm_t35.c @@ -19,6 +19,7 @@ #include <i2c.h> #include <usb.h> #include <mmc.h> +#include <splash.h> #include <twl4030.h> #include <linux/compiler.h> @@ -59,11 +60,18 @@ void get_board_mem_timings(struct board_sdrc_timings *timings) } #endif -#define CM_T35_SPLASH_NAND_OFFSET 0x100000 +struct splash_location splash_locations[] = { + { + .name = "nand", + .storage = SPLASH_STORAGE_NAND, + .offset = 0x100000, + }, +}; int splash_screen_prepare(void) { - return cl_splash_screen_prepare(CM_T35_SPLASH_NAND_OFFSET); + return splash_source_load(splash_locations, + ARRAY_SIZE(splash_locations)); } /* @@ -429,7 +437,7 @@ static int handle_mac_address(void) if (rc) return 0; - rc = cl_eeprom_read_mac_addr(enetaddr); + rc = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS); if (rc) return rc; diff --git a/board/compulab/cm_t3517/cm_t3517.c b/board/compulab/cm_t3517/cm_t3517.c index cac1ad9ef1..624cf4c034 100644 --- a/board/compulab/cm_t3517/cm_t3517.c +++ b/board/compulab/cm_t3517/cm_t3517.c @@ -163,7 +163,7 @@ static int cm_t3517_handle_mac_address(void) if (ret) return 0; - ret = cl_eeprom_read_mac_addr(enetaddr); + ret = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS); if (ret) { ret = am3517_get_efuse_enetaddr(enetaddr); if (ret) diff --git a/board/compulab/cm_t54/cm_t54.c b/board/compulab/cm_t54/cm_t54.c index 2c2530ab3f..fdea909ff7 100644 --- a/board/compulab/cm_t54/cm_t54.c +++ b/board/compulab/cm_t54/cm_t54.c @@ -165,7 +165,7 @@ static int handle_mac_address(void) if (ret) return 0; - ret = cl_eeprom_read_mac_addr(enetaddr); + ret = cl_eeprom_read_mac_addr(enetaddr, CONFIG_SYS_I2C_EEPROM_BUS); if (ret || !is_valid_ether_addr(enetaddr)) generate_mac_addr(enetaddr); diff --git a/board/compulab/common/Makefile b/board/compulab/common/Makefile index dbf0009652..286f32731d 100644 --- a/board/compulab/common/Makefile +++ b/board/compulab/common/Makefile @@ -9,5 +9,4 @@ obj-y += common.o obj-$(CONFIG_SYS_I2C) += eeprom.o obj-$(CONFIG_LCD) += omap3_display.o -obj-$(CONFIG_SPLASH_SCREEN) += splash.o obj-$(CONFIG_SMC911X) += omap3_smc911x.o diff --git a/board/compulab/common/common.h b/board/compulab/common/common.h index 68ffb111dc..8f38b79fb0 100644 --- a/board/compulab/common/common.h +++ b/board/compulab/common/common.h @@ -24,15 +24,6 @@ static inline int cl_usb_hub_init(int gpio, const char *label) static inline void cl_usb_hub_deinit(int gpio) {} #endif /* CONFIG_CMD_USB */ -#ifdef CONFIG_SPLASH_SCREEN -int cl_splash_screen_prepare(int nand_offset); -#else /* !CONFIG_SPLASH_SCREEN */ -static inline int cl_splash_screen_prepare(int nand_offset) -{ - return -ENOSYS; -} -#endif /* CONFIG_SPLASH_SCREEN */ - #ifdef CONFIG_SMC911X int cl_omap3_smc911x_init(int id, int cs, u32 base_addr, int (*reset)(int), int rst_gpio); diff --git a/board/compulab/common/eeprom.c b/board/compulab/common/eeprom.c index a45e7be11f..77bcea44b4 100644 --- a/board/compulab/common/eeprom.c +++ b/board/compulab/common/eeprom.c @@ -31,6 +31,7 @@ #define LAYOUT_INVALID 0 #define LAYOUT_LEGACY 0xff +static int cl_eeprom_bus; static int cl_eeprom_layout; /* Implicitly LAYOUT_INVALID */ static int cl_eeprom_read(uint offset, uchar *buf, int len) @@ -38,7 +39,7 @@ static int cl_eeprom_read(uint offset, uchar *buf, int len) int res; unsigned int current_i2c_bus = i2c_get_bus_num(); - res = i2c_set_bus_num(CONFIG_SYS_I2C_EEPROM_BUS); + res = i2c_set_bus_num(cl_eeprom_bus); if (res < 0) return res; @@ -50,13 +51,18 @@ static int cl_eeprom_read(uint offset, uchar *buf, int len) return res; } -static int cl_eeprom_setup_layout(void) +static int cl_eeprom_setup(uint eeprom_bus) { int res; - if (cl_eeprom_layout != LAYOUT_INVALID) + /* + * We know the setup was already done when the layout is set to a valid + * value and we're using the same bus as before. + */ + if (cl_eeprom_layout != LAYOUT_INVALID && eeprom_bus == cl_eeprom_bus) return 0; + cl_eeprom_bus = eeprom_bus; res = cl_eeprom_read(EEPROM_LAYOUT_VER_OFFSET, (uchar *)&cl_eeprom_layout, 1); if (res) { @@ -77,7 +83,7 @@ void get_board_serial(struct tag_serialnr *serialnr) memset(serialnr, 0, sizeof(*serialnr)); - if (cl_eeprom_setup_layout()) + if (cl_eeprom_setup(CONFIG_SYS_I2C_EEPROM_BUS)) return; offset = (cl_eeprom_layout != LAYOUT_LEGACY) ? @@ -96,11 +102,11 @@ void get_board_serial(struct tag_serialnr *serialnr) * Routine: cl_eeprom_read_mac_addr * Description: read mac address and store it in buf. */ -int cl_eeprom_read_mac_addr(uchar *buf) +int cl_eeprom_read_mac_addr(uchar *buf, uint eeprom_bus) { uint offset; - if (cl_eeprom_setup_layout()) + if (cl_eeprom_setup(eeprom_bus)) return 0; offset = (cl_eeprom_layout != LAYOUT_LEGACY) ? @@ -123,7 +129,7 @@ u32 cl_eeprom_get_board_rev(void) if (board_rev) return board_rev; - if (cl_eeprom_setup_layout()) + if (cl_eeprom_setup(CONFIG_SYS_I2C_EEPROM_BUS)) return 0; if (cl_eeprom_layout != LAYOUT_LEGACY) diff --git a/board/compulab/common/eeprom.h b/board/compulab/common/eeprom.h index 85d5bf03d6..50c6b0226f 100644 --- a/board/compulab/common/eeprom.h +++ b/board/compulab/common/eeprom.h @@ -11,10 +11,10 @@ #define _EEPROM_ #ifdef CONFIG_SYS_I2C -int cl_eeprom_read_mac_addr(uchar *buf); +int cl_eeprom_read_mac_addr(uchar *buf, uint eeprom_bus); u32 cl_eeprom_get_board_rev(void); #else -static inline int cl_eeprom_read_mac_addr(uchar *buf) +static inline int cl_eeprom_read_mac_addr(uchar *buf, uint eeprom_bus) { return 1; } diff --git a/board/compulab/common/splash.c b/board/compulab/common/splash.c deleted file mode 100644 index 49ed49b81e..0000000000 --- a/board/compulab/common/splash.c +++ /dev/null @@ -1,72 +0,0 @@ -/* - * (C) Copyright 2014 CompuLab, Ltd. <www.compulab.co.il> - * - * Authors: Igor Grinberg <grinberg@compulab.co.il> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <nand.h> -#include <bmp_layout.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifdef CONFIG_CMD_NAND -static int splash_load_from_nand(u32 bmp_load_addr, int nand_offset) -{ - struct bmp_header *bmp_hdr; - int res; - size_t bmp_size, bmp_header_size = sizeof(struct bmp_header); - - if (bmp_load_addr + bmp_header_size >= gd->start_addr_sp) - goto splash_address_too_high; - - res = nand_read_skip_bad(&nand_info[nand_curr_device], - nand_offset, &bmp_header_size, - NULL, nand_info[nand_curr_device].size, - (u_char *)bmp_load_addr); - if (res < 0) - return res; - - bmp_hdr = (struct bmp_header *)bmp_load_addr; - bmp_size = le32_to_cpu(bmp_hdr->file_size); - - if (bmp_load_addr + bmp_size >= gd->start_addr_sp) - goto splash_address_too_high; - - return nand_read_skip_bad(&nand_info[nand_curr_device], - nand_offset, &bmp_size, - NULL, nand_info[nand_curr_device].size, - (u_char *)bmp_load_addr); - -splash_address_too_high: - printf("Error: splashimage address too high. Data overwrites U-Boot " - "and/or placed beyond DRAM boundaries.\n"); - - return -1; -} -#else -static inline int splash_load_from_nand(u32 bmp_load_addr, int nand_offset) -{ - return -1; -} -#endif /* CONFIG_CMD_NAND */ - -int cl_splash_screen_prepare(int nand_offset) -{ - char *env_splashimage_value; - u32 bmp_load_addr; - - env_splashimage_value = getenv("splashimage"); - if (env_splashimage_value == NULL) - return -1; - - bmp_load_addr = simple_strtoul(env_splashimage_value, 0, 16); - if (bmp_load_addr == 0) { - printf("Error: bad splashimage address specified\n"); - return -1; - } - - return splash_load_from_nand(bmp_load_addr, nand_offset); -} diff --git a/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c b/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c index a74547bf65..f9ac330c33 100644 --- a/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c +++ b/board/earthlcd/favr-32-ezkit/favr-32-ezkit.c @@ -17,14 +17,14 @@ DECLARE_GLOBAL_DATA_PTR; struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { { - .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT, - .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT, - .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT) + .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT, + .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT, + .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT) | MMU_VMR_CACHE_NONE, }, { - .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT, - .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT, - .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT) + .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT, + .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT, + .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT) | MMU_VMR_CACHE_WRBACK, }, }; @@ -52,6 +52,9 @@ int board_early_init_f(void) hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH); + + sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config); + portmux_enable_usart3(PORTMUX_DRIVE_MIN); #if defined(CONFIG_MACB) portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_HIGH); @@ -63,24 +66,6 @@ int board_early_init_f(void) return 0; } -phys_size_t initdram(int board_type) -{ - unsigned long expected_size; - unsigned long actual_size; - void *sdram_base; - - sdram_base = uncached(EBI_SDRAM_BASE); - - expected_size = sdram_init(sdram_base, &sdram_config); - actual_size = get_ram_size(sdram_base, expected_size); - - if (expected_size != actual_size) - printf("Warning: Only %lu of %lu MiB SDRAM is working\n", - actual_size >> 20, expected_size >> 20); - - return actual_size; -} - int board_early_init_r(void) { gd->bd->bi_phy_id[0] = 0x01; diff --git a/board/egnite/ethernut5/Kconfig b/board/egnite/ethernut5/Kconfig index c42c734f1f..5a6c1c5de1 100644 --- a/board/egnite/ethernut5/Kconfig +++ b/board/egnite/ethernut5/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "egnite" -config SYS_SOC - default "at91" - config SYS_CONFIG_NAME default "ethernut5" diff --git a/board/esd/meesc/Kconfig b/board/esd/meesc/Kconfig index 5041041dd2..150348ac34 100644 --- a/board/esd/meesc/Kconfig +++ b/board/esd/meesc/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "esd" -config SYS_SOC - default "at91" - config SYS_CONFIG_NAME default "meesc" diff --git a/board/esd/otc570/Kconfig b/board/esd/otc570/Kconfig index 55a2f70f40..4966f5f755 100644 --- a/board/esd/otc570/Kconfig +++ b/board/esd/otc570/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "esd" -config SYS_SOC - default "at91" - config SYS_CONFIG_NAME default "otc570" diff --git a/board/eukrea/cpu9260/Kconfig b/board/eukrea/cpu9260/Kconfig index 9bd077b1ff..90d2124557 100644 --- a/board/eukrea/cpu9260/Kconfig +++ b/board/eukrea/cpu9260/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "eukrea" -config SYS_SOC - default "at91" - config SYS_CONFIG_NAME default "cpu9260" diff --git a/board/eukrea/cpuat91/Kconfig b/board/eukrea/cpuat91/Kconfig index b69e4c3f82..27b005cdf4 100644 --- a/board/eukrea/cpuat91/Kconfig +++ b/board/eukrea/cpuat91/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "eukrea" -config SYS_SOC - default "at91" - config SYS_CONFIG_NAME default "cpuat91" diff --git a/board/freescale/mx53loco/imximage.cfg b/board/freescale/mx53loco/imximage.cfg index d1c1931e46..a5f1d98bd1 100644 --- a/board/freescale/mx53loco/imximage.cfg +++ b/board/freescale/mx53loco/imximage.cfg @@ -59,7 +59,7 @@ DATA 4 0x63fd9090 0x4d444c44 DATA 4 0x63fd907c 0x01370138 DATA 4 0x63fd9080 0x013b013c DATA 4 0x63fd9018 0x00011740 -DATA 4 0x63fd9000 0xc3190000 +DATA 4 0x63fd9000 0x83190000 DATA 4 0x63fd900c 0x9f5152e3 DATA 4 0x63fd9010 0xb68e8a63 DATA 4 0x63fd9014 0x01ff00db @@ -72,6 +72,7 @@ DATA 4 0x63fd901c 0x00008033 DATA 4 0x63fd901c 0x00028031 DATA 4 0x63fd901c 0x052080b0 DATA 4 0x63fd901c 0x04008040 +DATA 4 0x63fd9000 0xc3190000 DATA 4 0x63fd901c 0x0000803a DATA 4 0x63fd901c 0x0000803b DATA 4 0x63fd901c 0x00028039 diff --git a/board/freescale/mx6qsabreauto/mx6qsabreauto.c b/board/freescale/mx6qsabreauto/mx6qsabreauto.c index 59387ffaaa..a90360f2df 100644 --- a/board/freescale/mx6qsabreauto/mx6qsabreauto.c +++ b/board/freescale/mx6qsabreauto/mx6qsabreauto.c @@ -311,30 +311,9 @@ static void setup_gpmi_nand(void) /* config gpmi nand iomux */ imx_iomux_v3_setup_multiple_pads(gpmi_pads, ARRAY_SIZE(gpmi_pads)); - /* gate ENFC_CLK_ROOT clock first,before clk source switch */ - clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); - clrbits_le32(&mxc_ccm->CCGR4, - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK); - - /* config gpmi and bch clock to 100 MHz */ - clrsetbits_le32(&mxc_ccm->cs2cdr, - MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | - MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | - MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, - MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | + setup_gpmi_io_clk((MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | - MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); - - /* enable ENFC_CLK_ROOT clock */ - setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); - - /* enable gpmi and bch clock gating */ - setbits_le32(&mxc_ccm->CCGR4, - MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | - MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | - MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); + MXC_CCM_CS2CDR_ENFC_CLK_SEL(3))); /* enable apbh clock gating */ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); diff --git a/board/freescale/mx6sxsabresd/MAINTAINERS b/board/freescale/mx6sxsabresd/MAINTAINERS index f52f300bed..c0f5d9c8e4 100644 --- a/board/freescale/mx6sxsabresd/MAINTAINERS +++ b/board/freescale/mx6sxsabresd/MAINTAINERS @@ -4,3 +4,4 @@ S: Maintained F: board/freescale/mx6sxsabresd/ F: include/configs/mx6sxsabresd.h F: configs/mx6sxsabresd_defconfig +F: configs/mx6sxsabresd_spl_defconfig diff --git a/board/freescale/mx6sxsabresd/mx6sxsabresd.c b/board/freescale/mx6sxsabresd/mx6sxsabresd.c index 5cc58ac868..a2c9aae32c 100644 --- a/board/freescale/mx6sxsabresd/mx6sxsabresd.c +++ b/board/freescale/mx6sxsabresd/mx6sxsabresd.c @@ -326,6 +326,7 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { +#ifndef CONFIG_SPL_BUILD int i, ret; /* @@ -369,6 +370,47 @@ int board_mmc_init(bd_t *bis) } return 0; +#else + struct src *src_regs = (struct src *)SRC_BASE_ADDR; + u32 val; + u32 port; + + val = readl(&src_regs->sbmr1); + + if ((val & 0xc0) != 0x40) { + printf("Not boot from USDHC!\n"); + return -EINVAL; + } + + port = (val >> 11) & 0x3; + printf("port %d\n", port); + switch (port) { + case 1: + imx_iomux_v3_setup_multiple_pads( + usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); + usdhc_cfg[0].esdhc_base = USDHC2_BASE_ADDR; + break; + case 2: + imx_iomux_v3_setup_multiple_pads( + usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + gpio_direction_input(USDHC3_CD_GPIO); + gpio_direction_output(USDHC3_PWR_GPIO, 1); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[0].esdhc_base = USDHC3_BASE_ADDR; + break; + case 3: + imx_iomux_v3_setup_multiple_pads( + usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + gpio_direction_input(USDHC4_CD_GPIO); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + usdhc_cfg[0].esdhc_base = USDHC4_BASE_ADDR; + break; + } + + gd->arch.sdhc_clk = usdhc_cfg[0].sdhc_clk; + return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); +#endif } #ifdef CONFIG_FSL_QSPI @@ -423,14 +465,135 @@ int board_init(void) return 0; } -int board_late_init(void) +int checkboard(void) { + puts("Board: MX6SX SABRE SDB\n"); + return 0; } -int checkboard(void) +#ifdef CONFIG_SPL_BUILD +#include <libfdt.h> +#include <spl.h> +#include <asm/arch/mx6-ddr.h> + +const struct mx6sx_iomux_ddr_regs mx6_ddr_ioregs = { + .dram_dqm0 = 0x00000028, + .dram_dqm1 = 0x00000028, + .dram_dqm2 = 0x00000028, + .dram_dqm3 = 0x00000028, + .dram_ras = 0x00000020, + .dram_cas = 0x00000020, + .dram_odt0 = 0x00000020, + .dram_odt1 = 0x00000020, + .dram_sdba2 = 0x00000000, + .dram_sdcke0 = 0x00003000, + .dram_sdcke1 = 0x00003000, + .dram_sdclk_0 = 0x00000030, + .dram_sdqs0 = 0x00000028, + .dram_sdqs1 = 0x00000028, + .dram_sdqs2 = 0x00000028, + .dram_sdqs3 = 0x00000028, + .dram_reset = 0x00000020, +}; + +const struct mx6sx_iomux_grp_regs mx6_grp_ioregs = { + .grp_addds = 0x00000020, + .grp_ddrmode_ctl = 0x00020000, + .grp_ddrpke = 0x00000000, + .grp_ddrmode = 0x00020000, + .grp_b0ds = 0x00000028, + .grp_b1ds = 0x00000028, + .grp_ctlds = 0x00000020, + .grp_ddr_type = 0x000c0000, + .grp_b2ds = 0x00000028, + .grp_b3ds = 0x00000028, +}; + +const struct mx6_mmdc_calibration mx6_mmcd_calib = { + .p0_mpwldectrl0 = 0x00290025, + .p0_mpwldectrl1 = 0x00220022, + .p0_mpdgctrl0 = 0x41480144, + .p0_mpdgctrl1 = 0x01340130, + .p0_mprddlctl = 0x3C3E4244, + .p0_mpwrdlctl = 0x34363638, +}; + +static struct mx6_ddr3_cfg mem_ddr = { + .mem_speed = 1600, + .density = 4, + .width = 32, + .banks = 8, + .rowaddr = 15, + .coladdr = 10, + .pagesz = 2, + .trcd = 1375, + .trcmin = 4875, + .trasmin = 3500, +}; + +static void ccgr_init(void) { - puts("Board: MX6SX SABRE SDB\n"); + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + + writel(0xFFFFFFFF, &ccm->CCGR0); + writel(0xFFFFFFFF, &ccm->CCGR1); + writel(0xFFFFFFFF, &ccm->CCGR2); + writel(0xFFFFFFFF, &ccm->CCGR3); + writel(0xFFFFFFFF, &ccm->CCGR4); + writel(0xFFFFFFFF, &ccm->CCGR5); + writel(0xFFFFFFFF, &ccm->CCGR6); + writel(0xFFFFFFFF, &ccm->CCGR7); +} - return 0; +static void spl_dram_init(void) +{ + struct mx6_ddr_sysinfo sysinfo = { + .dsize = mem_ddr.width/32, + .cs_density = 24, + .ncs = 1, + .cs1_mirror = 0, + .rtt_wr = 2, + .rtt_nom = 2, /* RTT_Nom = RZQ/2 */ + .walat = 1, /* Write additional latency */ + .ralat = 5, /* Read additional latency */ + .mif3_mode = 3, /* Command prediction working mode */ + .bi_on = 1, /* Bank interleaving enabled */ + .sde_to_rst = 0x10, /* 14 cycles, 200us (JEDEC default) */ + .rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */ + }; + + mx6sx_dram_iocfg(mem_ddr.width, &mx6_ddr_ioregs, &mx6_grp_ioregs); + mx6_dram_cfg(&sysinfo, &mx6_mmcd_calib, &mem_ddr); +} + +void board_init_f(ulong dummy) +{ + /* setup AIPS and disable watchdog */ + arch_cpu_init(); + + ccgr_init(); + + /* iomux and setup of i2c */ + board_early_init_f(); + + /* setup GP timer */ + timer_init(); + + /* UART clocks enabled and gd valid - init serial console */ + preloader_console_init(); + + /* DDR initialization */ + spl_dram_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + /* load/boot image from boot device */ + board_init_r(NULL, 0); } + +void reset_cpu(ulong addr) +{ +} +#endif diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig index 33a31f311f..ea454721c5 100644 --- a/board/google/chromebook_link/Kconfig +++ b/board/google/chromebook_link/Kconfig @@ -22,8 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MARK_GRAPHICS_MEM_WRCOMB select BOARD_ROMSIZE_KB_8192 -config MMCONF_BASE_ADDRESS - hex +config PCIE_ECAM_BASE default 0xf0000000 config EARLY_POST_CROS_EC diff --git a/board/gumstix/pepper/Kconfig b/board/gumstix/pepper/Kconfig index 6f94612fe2..3099a9eae1 100644 --- a/board/gumstix/pepper/Kconfig +++ b/board/gumstix/pepper/Kconfig @@ -12,4 +12,13 @@ config SYS_SOC config SYS_CONFIG_NAME default "pepper" +config DM + default y if !SPL_BUILD + +config DM_GPIO + default y if !SPL_BUILD + +config DM_SERIAL + default y if !SPL_BUILD + endif diff --git a/board/imgtec/malta/malta.c b/board/imgtec/malta/malta.c index 78c4bd4efe..79562f79a8 100644 --- a/board/imgtec/malta/malta.c +++ b/board/imgtec/malta/malta.c @@ -6,6 +6,7 @@ */ #include <common.h> +#include <ide.h> #include <netdev.h> #include <pci.h> #include <pci_gt64120.h> @@ -123,6 +124,7 @@ void _machine_restart(void) reset_base = (void __iomem *)CKSEG1ADDR(MALTA_RESET_BASE); __raw_writel(GORESET, reset_base); + mdelay(1000); } int board_early_init_f(void) @@ -217,4 +219,22 @@ void pci_init_board(void) pci_read_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, &val8); val8 |= PCI_CFG_PIIX4_SERIRQC_EN | PCI_CFG_PIIX4_SERIRQC_CONT; pci_write_config_byte(bdf, PCI_CFG_PIIX4_SERIRQC, val8); + + bdf = pci_find_device(PCI_VENDOR_ID_INTEL, + PCI_DEVICE_ID_INTEL_82371AB, 0); + if (bdf == -1) + panic("Failed to find PIIX4 IDE controller\n"); + + /* enable bus master & IO access */ + val32 |= PCI_COMMAND_MASTER | PCI_COMMAND_IO; + pci_write_config_dword(bdf, PCI_COMMAND, val32); + + /* set latency */ + pci_write_config_byte(bdf, PCI_LATENCY_TIMER, 0x40); + + /* enable IDE/ATA */ + pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_PRI, + PCI_CFG_PIIX4_IDETIM_IDE); + pci_write_config_dword(bdf, PCI_CFG_PIIX4_IDETIM_SEC, + PCI_CFG_PIIX4_IDETIM_IDE); } diff --git a/board/in-circuit/grasshopper/grasshopper.c b/board/in-circuit/grasshopper/grasshopper.c index 340b713188..91b41162de 100644 --- a/board/in-circuit/grasshopper/grasshopper.c +++ b/board/in-circuit/grasshopper/grasshopper.c @@ -18,14 +18,14 @@ DECLARE_GLOBAL_DATA_PTR; struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { { - .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT, - .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT, - .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT) + .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT, + .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT, + .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT) | MMU_VMR_CACHE_NONE, }, { - .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT, - .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT, - .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT) + .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT, + .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT, + .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT) | MMU_VMR_CACHE_WRBACK, }, }; @@ -53,6 +53,8 @@ int board_early_init_f(void) hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); portmux_enable_ebi(SDRAM_DATA_32BIT, 23, 0, PORTMUX_DRIVE_HIGH); + sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config); + portmux_enable_usart0(PORTMUX_DRIVE_MIN); portmux_enable_usart1(PORTMUX_DRIVE_MIN); #if defined(CONFIG_MACB) @@ -69,24 +71,6 @@ int board_early_init_f(void) return 0; } -phys_size_t initdram(int board_type) -{ - unsigned long expected_size; - unsigned long actual_size; - void *sdram_base; - - sdram_base = uncached(EBI_SDRAM_BASE); - - expected_size = sdram_init(sdram_base, &sdram_config); - actual_size = get_ram_size(sdram_base, expected_size); - - if (expected_size != actual_size) - printf("Warning: Only %lu of %lu MiB SDRAM is working\n", - actual_size >> 20, expected_size >> 20); - - return actual_size; -} - int board_early_init_r(void) { gd->bd->bi_phy_id[0] = 0x00; diff --git a/board/intel/galileo/Kconfig b/board/intel/galileo/Kconfig new file mode 100644 index 0000000000..85afbbc8c5 --- /dev/null +++ b/board/intel/galileo/Kconfig @@ -0,0 +1,21 @@ +if TARGET_GALILEO + +config SYS_BOARD + default "galileo" + +config SYS_VENDOR + default "intel" + +config SYS_SOC + default "quark" + +config SYS_CONFIG_NAME + default "galileo" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR + select INTEL_QUARK + select BOARD_ROMSIZE_KB_1024 + +endif diff --git a/board/intel/galileo/MAINTAINERS b/board/intel/galileo/MAINTAINERS new file mode 100644 index 0000000000..dbbc82e8a1 --- /dev/null +++ b/board/intel/galileo/MAINTAINERS @@ -0,0 +1,6 @@ +INTEL GALILEO BOARD +M: Bin Meng <bmeng.cn@gmail.com> +S: Maintained +F: board/intel/galileo/ +F: include/configs/galileo.h +F: configs/galileo_defconfig diff --git a/board/intel/galileo/Makefile b/board/intel/galileo/Makefile new file mode 100644 index 0000000000..8356df198c --- /dev/null +++ b/board/intel/galileo/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += galileo.o start.o diff --git a/board/intel/galileo/galileo.c b/board/intel/galileo/galileo.c new file mode 100644 index 0000000000..f2e74687ed --- /dev/null +++ b/board/intel/galileo/galileo.c @@ -0,0 +1,19 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + return 0; +} + +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) +{ + return; +} diff --git a/board/intel/galileo/start.S b/board/intel/galileo/start.S new file mode 100644 index 0000000000..a71db69be9 --- /dev/null +++ b/board/intel/galileo/start.S @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.globl early_board_init +early_board_init: + jmp early_board_init_ret diff --git a/board/intel/minnowmax/Kconfig b/board/intel/minnowmax/Kconfig new file mode 100644 index 0000000000..43c50a519b --- /dev/null +++ b/board/intel/minnowmax/Kconfig @@ -0,0 +1,24 @@ +if TARGET_MINNOWMAX + +config SYS_BOARD + default "minnowmax" + +config SYS_VENDOR + default "intel" + +config SYS_SOC + default "baytrail" + +config SYS_CONFIG_NAME + default "minnowmax" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select X86_RESET_VECTOR + select INTEL_BAYTRAIL + select BOARD_ROMSIZE_KB_8192 + +config PCIE_ECAM_BASE + default 0xe0000000 + +endif diff --git a/board/intel/minnowmax/MAINTAINERS b/board/intel/minnowmax/MAINTAINERS new file mode 100644 index 0000000000..d655761d57 --- /dev/null +++ b/board/intel/minnowmax/MAINTAINERS @@ -0,0 +1,6 @@ +CircuitCo Minnowboard Max +M: Simon Glass <sjg@chromium.org> +S: Maintained +F: board/intel/minnowmax +F: include/configs/minnowmax.h +F: configs/minnowmax_defconfig diff --git a/board/intel/minnowmax/Makefile b/board/intel/minnowmax/Makefile new file mode 100644 index 0000000000..1a614324a2 --- /dev/null +++ b/board/intel/minnowmax/Makefile @@ -0,0 +1,7 @@ +# +# Copyright (C) 2015, Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += minnowmax.o start.o diff --git a/board/intel/minnowmax/minnowmax.c b/board/intel/minnowmax/minnowmax.c new file mode 100644 index 0000000000..6e82b16335 --- /dev/null +++ b/board/intel/minnowmax/minnowmax.c @@ -0,0 +1,32 @@ +/* + * Copyright (C) 2015, Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/ibmpc.h> +#include <asm/pnp_def.h> +#include <netdev.h> +#include <smsc_lpc47m.h> + +#define SERIAL_DEV PNP_DEV(0x2e, 4) + +DECLARE_GLOBAL_DATA_PTR; + +int board_early_init_f(void) +{ + lpc47m_enable_serial(SERIAL_DEV, UART0_BASE); + + return 0; +} + +void setup_pch_gpios(u16 gpiobase, const struct pch_gpio_map *gpio) +{ + return; +} + +int board_eth_init(bd_t *bis) +{ + return pci_eth_init(bis); +} diff --git a/board/intel/minnowmax/start.S b/board/intel/minnowmax/start.S new file mode 100644 index 0000000000..2c941a4a51 --- /dev/null +++ b/board/intel/minnowmax/start.S @@ -0,0 +1,9 @@ +/* + * Copyright (C) 2015, Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +.globl early_board_init +early_board_init: + jmp early_board_init_ret diff --git a/board/isee/igep0033/Kconfig b/board/isee/igep0033/Kconfig index e989e4b15c..2fe2ef1706 100644 --- a/board/isee/igep0033/Kconfig +++ b/board/isee/igep0033/Kconfig @@ -12,4 +12,13 @@ config SYS_SOC config SYS_CONFIG_NAME default "am335x_igep0033" +config DM + default y if !SPL_BUILD + +config DM_GPIO + default y if !SPL_BUILD + +config DM_SERIAL + default y if !SPL_BUILD + endif diff --git a/board/isee/igep00x0/igep00x0.c b/board/isee/igep00x0/igep00x0.c index 47522f8013..693fce741a 100644 --- a/board/isee/igep00x0/igep00x0.c +++ b/board/isee/igep00x0/igep00x0.c @@ -5,6 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ #include <common.h> +#include <status_led.h> #include <dm.h> #include <ns16550.h> #include <twl4030.h> @@ -53,21 +54,12 @@ int board_init(void) /* boot param addr */ gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); - return 0; -} - -#if defined(CONFIG_SHOW_BOOT_PROGRESS) && !defined(CONFIG_SPL_BUILD) -void show_boot_progress(int val) -{ - if (val < 0) { - /* something went wrong */ - return; - } +#if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) + status_led_set(STATUS_LED_BOOT, STATUS_LED_ON); +#endif - if (!gpio_request(IGEP00X0_GPIO_LED, "")) - gpio_direction_output(IGEP00X0_GPIO_LED, 1); + return 0; } -#endif #ifdef CONFIG_SPL_BUILD /* diff --git a/board/isee/igep00x0/igep00x0.h b/board/isee/igep00x0/igep00x0.h index 181f81f2a1..3c7ff9b148 100644 --- a/board/isee/igep00x0/igep00x0.h +++ b/board/isee/igep00x0/igep00x0.h @@ -7,14 +7,6 @@ #ifndef _IGEP00X0_H_ #define _IGEP00X0_H_ -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) -#define IGEP00X0_GPIO_LED 27 -#endif - -#if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0030) -#define IGEP00X0_GPIO_LED 16 -#endif - const omap3_sysinfo sysinfo = { DDR_STACKED, #if (CONFIG_MACH_TYPE == MACH_TYPE_IGEP0020) diff --git a/board/keymile/common/common.h b/board/keymile/common/common.h index e075f4687b..dcfefc46b3 100644 --- a/board/keymile/common/common.h +++ b/board/keymile/common/common.h @@ -126,7 +126,8 @@ struct bfticu_iomap { #endif int ethernet_present(void); -int ivm_read_eeprom(void); +int ivm_read_eeprom(unsigned char *buf, int len); +int ivm_analyze_eeprom(unsigned char *buf, int len); int trigger_fpga_config(void); int wait_for_fpga_config(void); diff --git a/board/keymile/common/ivm.c b/board/keymile/common/ivm.c index b6b19ccb8e..42db54221b 100644 --- a/board/keymile/common/ivm.c +++ b/board/keymile/common/ivm.c @@ -10,6 +10,8 @@ #include <i2c.h> #include "common.h" +#define MAC_STR_SZ 20 + static int ivm_calc_crc(unsigned char *buf, int len) { const unsigned short crc_tab[16] = { @@ -185,45 +187,37 @@ static int ivm_check_crc(unsigned char *buf, int block) return 0; } -static int calculate_mac_offset(unsigned char *valbuf, unsigned char *buf, +/* take care of the possible MAC address offset and the IVM content offset */ +static int process_mac(unsigned char *valbuf, unsigned char *buf, int offset) { + unsigned char mac[6]; unsigned long val = (buf[4] << 16) + (buf[5] << 8) + buf[6]; - if (offset == 0) - return 0; + /* use an intermediate buffer, to not change IVM content + * MAC address is at offset 1 + */ + memcpy(mac, buf+1, 6); - val += offset; - buf[4] = (val >> 16) & 0xff; - buf[5] = (val >> 8) & 0xff; - buf[6] = val & 0xff; - sprintf((char *)valbuf, "%pM", buf + 1); + if (offset) { + val += offset; + mac[3] = (val >> 16) & 0xff; + mac[4] = (val >> 8) & 0xff; + mac[5] = val & 0xff; + } + + sprintf((char *)valbuf, "%pM", mac); return 0; } static int ivm_analyze_block2(unsigned char *buf, int len) { - unsigned char valbuf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN]; + unsigned char valbuf[MAC_STR_SZ]; unsigned long count; /* IVM_MAC Adress begins at offset 1 */ sprintf((char *)valbuf, "%pM", buf + 1); ivm_set_value("IVM_MacAddress", (char *)valbuf); - /* if an offset is defined, add it */ - calculate_mac_offset(buf, valbuf, CONFIG_PIGGY_MAC_ADRESS_OFFSET); -#ifdef MACH_TYPE_KM_KIRKWOOD - setenv((char *)"ethaddr", (char *)valbuf); -#else - if (getenv("ethaddr") == NULL) - setenv((char *)"ethaddr", (char *)valbuf); -#endif -#ifdef CONFIG_KMVECT1 -/* KMVECT1 has two ethernet interfaces */ - if (getenv("eth1addr") == NULL) { - calculate_mac_offset(buf, valbuf, 1); - setenv((char *)"eth1addr", (char *)valbuf); - } -#endif /* IVM_MacCount */ count = (buf[10] << 24) + (buf[11] << 16) + @@ -236,7 +230,7 @@ static int ivm_analyze_block2(unsigned char *buf, int len) return 0; } -static int ivm_analyze_eeprom(unsigned char *buf, int len) +int ivm_analyze_eeprom(unsigned char *buf, int len) { unsigned short val; unsigned char valbuf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN]; @@ -296,21 +290,44 @@ static int ivm_analyze_eeprom(unsigned char *buf, int len) return 0; } -int ivm_read_eeprom(void) +static int ivm_populate_env(unsigned char *buf, int len) +{ + unsigned char *page2; + unsigned char valbuf[MAC_STR_SZ]; + + /* do we have the page 2 filled ? if not return */ + if (ivm_check_crc(buf, 2)) + return 0; + page2 = &buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN*2]; + + /* if an offset is defined, add it */ + process_mac(valbuf, page2, CONFIG_PIGGY_MAC_ADRESS_OFFSET); + if (getenv("ethaddr") == NULL) + setenv((char *)"ethaddr", (char *)valbuf); +#ifdef CONFIG_KMVECT1 +/* KMVECT1 has two ethernet interfaces */ + if (getenv("eth1addr") == NULL) { + process_mac(valbuf, page2, 1); + setenv((char *)"eth1addr", (char *)valbuf); + } +#endif + + return 0; +} + +int ivm_read_eeprom(unsigned char *buf, int len) { - uchar i2c_buffer[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; int ret; i2c_set_bus_num(CONFIG_KM_IVM_BUS); /* add deblocking here */ i2c_make_abort(); - ret = i2c_read(CONFIG_SYS_IVM_EEPROM_ADR, 0, 1, i2c_buffer, - CONFIG_SYS_IVM_EEPROM_MAX_LEN); + ret = i2c_read(CONFIG_SYS_IVM_EEPROM_ADR, 0, 1, buf, len); if (ret != 0) { printf("Error reading EEprom\n"); return -2; } - return ivm_analyze_eeprom(i2c_buffer, CONFIG_SYS_IVM_EEPROM_MAX_LEN); + return ivm_populate_env(buf, len); } diff --git a/board/keymile/km82xx/km82xx.c b/board/keymile/km82xx/km82xx.c index bf84676b9b..c599b40936 100644 --- a/board/keymile/km82xx/km82xx.c +++ b/board/keymile/km82xx/km82xx.c @@ -18,6 +18,8 @@ #include <i2c.h> #include "../common/common.h" +static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; + /* * I/O Port configuration table * @@ -393,9 +395,15 @@ int board_early_init_r(void) return 0; } +int misc_init_r(void) +{ + ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); + return 0; +} + int hush_init_var(void) { - ivm_read_eeprom(); + ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); return 0; } diff --git a/board/keymile/km83xx/km83xx.c b/board/keymile/km83xx/km83xx.c index 1da0dcb9d8..89e9e1e57c 100644 --- a/board/keymile/km83xx/km83xx.c +++ b/board/keymile/km83xx/km83xx.c @@ -28,6 +28,8 @@ #include "../common/common.h" +static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; + const qe_iop_conf_t qe_iop_conf_tab[] = { /* port pin dir open_drain assign */ #if defined(CONFIG_MPC8360) @@ -190,6 +192,7 @@ int board_early_init_r(void) int misc_init_r(void) { + ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); return 0; } @@ -370,7 +373,7 @@ int ft_board_setup(void *blob, bd_t *bd) #if defined(CONFIG_HUSH_INIT_VAR) int hush_init_var(void) { - ivm_read_eeprom(); + ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); return 0; } #endif diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index 1c7c108cb5..2938861f36 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -102,6 +102,8 @@ static const u32 kwmpp_config[] = { 0 }; +static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; + #if defined(CONFIG_KM_MGCOGE3UN) /* * Wait for startup OK from mgcoge3ne @@ -210,6 +212,8 @@ int misc_init_r(void) } #endif + ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); + initialize_unit_leds(); set_km_env(); set_bootcount_addr(); @@ -419,7 +423,7 @@ void reset_phy(void) #if defined(CONFIG_HUSH_INIT_VAR) int hush_init_var(void) { - ivm_read_eeprom(); + ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); return 0; } #endif diff --git a/board/keymile/kmp204x/kmp204x.c b/board/keymile/kmp204x/kmp204x.c index a74f75bad4..eebb47fc21 100644 --- a/board/keymile/kmp204x/kmp204x.c +++ b/board/keymile/kmp204x/kmp204x.c @@ -26,6 +26,8 @@ DECLARE_GLOBAL_DATA_PTR; +static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN]; + int checkboard(void) { printf("Board: Keymile %s\n", CONFIG_KM_BOARD_NAME); @@ -195,13 +197,14 @@ int misc_init_r(void) } } + ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); return 0; } #if defined(CONFIG_HUSH_INIT_VAR) int hush_init_var(void) { - ivm_read_eeprom(); + ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN); return 0; } #endif diff --git a/board/maxbcm/binary.0 b/board/maxbcm/binary.0 deleted file mode 100644 index 17bfad99dc..0000000000 --- a/board/maxbcm/binary.0 +++ /dev/null @@ -1,17 +0,0 @@ --------- -WARNING: --------- -This file should contain the bin_hdr generated by the original Marvell -U-Boot implementation. As this is currently not included in this -U-Boot version, we have added this placeholder, so that the U-Boot -image can be generated without errors. - -If you have a known to be working bin_hdr for your board, then you -just need to replace this text file here with the binary header -and recompile U-Boot. - -In a few weeks, mainline U-Boot will get support to generate the -bin_hdr with the DDR training code itself. By implementing this code -as SPL U-Boot. Then this file will not be needed any more and will -get removed. - diff --git a/board/maxbcm/kwbimage.cfg b/board/maxbcm/kwbimage.cfg index 5a3bc67c1c..cc05792556 100644 --- a/board/maxbcm/kwbimage.cfg +++ b/board/maxbcm/kwbimage.cfg @@ -9,4 +9,4 @@ VERSION 1 BOOT_FROM spi # Binary Header (bin_hdr) with DDR3 training code -BINARY board/maxbcm/binary.0 0000005b 00000068 +BINARY spl/u-boot-spl.bin 0000005b 00000068 diff --git a/board/maxbcm/maxbcm.c b/board/maxbcm/maxbcm.c index 7fc83ee820..46b16ac29c 100644 --- a/board/maxbcm/maxbcm.c +++ b/board/maxbcm/maxbcm.c @@ -11,6 +11,9 @@ #include <asm/arch/soc.h> #include <linux/mbus.h> +#include "../drivers/ddr/mvebu/ddr3_hw_training.h" +#include "../arch/arm/mvebu-common/serdes/high_speed_env_spec.h" + DECLARE_GLOBAL_DATA_PTR; /* Base addresses for the external device chip selects */ @@ -19,8 +22,84 @@ DECLARE_GLOBAL_DATA_PTR; #define DEV_CS2_BASE 0xe2000000 #define DEV_CS3_BASE 0xe3000000 -/* Needed for dynamic (board-specific) mbus configuration */ -extern struct mvebu_mbus_state mbus_state; +/* DDR3 static configuration */ +MV_DRAM_MC_INIT ddr3_b0_maxbcm[MV_MAX_DDR3_STATIC_SIZE] = { + {0x00001400, 0x7301CC30}, /* DDR SDRAM Configuration Register */ + {0x00001404, 0x30000820}, /* Dunit Control Low Register */ + {0x00001408, 0x5515BAAB}, /* DDR SDRAM Timing (Low) Register */ + {0x0000140C, 0x38DA3F97}, /* DDR SDRAM Timing (High) Register */ + {0x00001410, 0x20100005}, /* DDR SDRAM Address Control Register */ + {0x00001414, 0x0000F3FF}, /* DDR SDRAM Open Pages Control Reg */ + {0x00001418, 0x00000e00}, /* DDR SDRAM Operation Register */ + {0x0000141C, 0x00000672}, /* DDR SDRAM Mode Register */ + {0x00001420, 0x00000004}, /* DDR SDRAM Extended Mode Register */ + {0x00001424, 0x0000F3FF}, /* Dunit Control High Register */ + {0x00001428, 0x0011A940}, /* Dunit Control High Register */ + {0x0000142C, 0x014C5134}, /* Dunit Control High Register */ + {0x0000147C, 0x0000D771}, + + {0x00001494, 0x00010000}, /* DDR SDRAM ODT Control (Low) Reg */ + {0x0000149C, 0x00000001}, /* DDR Dunit ODT Control Register */ + {0x000014A0, 0x00000001}, + {0x000014A8, 0x00000101}, + + /* Recommended Settings from Marvell for 4 x 16 bit devices: */ + {0x000014C0, 0x192424C9}, /* DRAM addr and Ctrl Driving Strenght*/ + {0x000014C4, 0xAAA24C9}, /* DRAM Data and DQS Driving Strenght */ + + /* + * DO NOT Modify - Open Mbus Window - 2G - Mbus is required for the + * training sequence + */ + {0x000200e8, 0x3FFF0E01}, + {0x00020184, 0x3FFFFFE0}, /* Close fast path Window to - 2G */ + + {0x0001504, 0x3FFFFFE1}, /* CS0 Size */ + {0x000150C, 0x00000000}, /* CS1 Size */ + {0x0001514, 0x00000000}, /* CS2 Size */ + {0x000151C, 0x00000000}, /* CS3 Size */ + + {0x0020220, 0x00000007}, /* Reserved */ + + {0x00001538, 0x0000000B}, /* Read Data Sample Delays Register */ + {0x0000153C, 0x0000000B}, /* Read Data Ready Delay Register */ + + {0x000015D0, 0x00000670}, /* MR0 */ + {0x000015D4, 0x00000044}, /* MR1 */ + {0x000015D8, 0x00000018}, /* MR2 */ + {0x000015DC, 0x00000000}, /* MR3 */ + {0x000015E0, 0x00000001}, + {0x000015E4, 0x00203c18}, /* ZQDS Configuration Register */ + {0x000015EC, 0xF800A225}, /* DDR PHY */ + + {0x0, 0x0} +}; + +MV_DRAM_MODES maxbcm_ddr_modes[MV_DDR3_MODES_NUMBER] = { + {"maxbcm_1600-800", 0xB, 0x5, 0x0, A0, ddr3_b0_maxbcm, NULL}, +}; + +extern MV_SERDES_CHANGE_M_PHY serdes_change_m_phy[]; + +/* MAXBCM: SERDES 0-4 PCIE, Serdes 7 = SGMII 0, all others = unconnected */ +MV_BIN_SERDES_CFG maxbcm_serdes_cfg[] = { + { MV_PEX_ROOT_COMPLEX, 0x20011111, 0x00000000, + { PEX_BUS_MODE_X1, PEX_BUS_MODE_X1, PEX_BUS_DISABLED, + PEX_BUS_DISABLED }, + 0x1f, serdes_change_m_phy + } +}; + +MV_DRAM_MODES *ddr3_get_static_ddr_mode(void) +{ + /* Only one mode supported for this board */ + return &maxbcm_ddr_modes[0]; +} + +MV_BIN_SERDES_CFG *board_serdes_cfg_get(u8 pex_mode) +{ + return &maxbcm_serdes_cfg[0]; +} int board_early_init_f(void) { @@ -63,9 +142,7 @@ int checkboard(void) /* Configure and enable MV88E6185 switch */ void reset_phy(void) { - u16 devadr = CONFIG_PHY_BASE_ADDR; char *name = "neta0"; - u16 reg; if (miiphy_set_current_dev(name)) return; diff --git a/board/mimc/mimc200/mimc200.c b/board/mimc/mimc200/mimc200.c index 2ad53ec2ab..f078295508 100644 --- a/board/mimc/mimc200/mimc200.c +++ b/board/mimc/mimc200/mimc200.c @@ -20,19 +20,19 @@ struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { { - .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT, - .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT, - .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT) + .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT, + .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT, + .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT) | MMU_VMR_CACHE_NONE, }, { - .virt_pgno = EBI_SRAM_CS2_BASE >> PAGE_SHIFT, - .nr_pages = EBI_SRAM_CS2_SIZE >> PAGE_SHIFT, - .phys = (EBI_SRAM_CS2_BASE >> PAGE_SHIFT) + .virt_pgno = EBI_SRAM_CS2_BASE >> MMU_PAGE_SHIFT, + .nr_pages = EBI_SRAM_CS2_SIZE >> MMU_PAGE_SHIFT, + .phys = (EBI_SRAM_CS2_BASE >> MMU_PAGE_SHIFT) | MMU_VMR_CACHE_NONE, }, { - .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT, - .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT, - .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT) + .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT, + .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT, + .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT) | MMU_VMR_CACHE_WRBACK, }, }; @@ -91,6 +91,8 @@ int board_early_init_f(void) /* Enable 26 address bits and NCS2 */ portmux_enable_ebi(16, 26, PORTMUX_EBI_CS(2), PORTMUX_DRIVE_HIGH); + sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config); + portmux_enable_usart1(PORTMUX_DRIVE_MIN); /* de-assert "force sys reset" pin */ @@ -151,24 +153,6 @@ int board_early_init_f(void) return 0; } -phys_size_t initdram(int board_type) -{ - unsigned long expected_size; - unsigned long actual_size; - void *sdram_base; - - sdram_base = uncached(EBI_SDRAM_BASE); - - expected_size = sdram_init(sdram_base, &sdram_config); - actual_size = get_ram_size(sdram_base, expected_size); - - if (expected_size != actual_size) - printf("Warning: Only %lu of %lu MiB SDRAM is working\n", - actual_size >> 20, expected_size >> 20); - - return actual_size; -} - int board_early_init_r(void) { gd->bd->bi_phy_id[0] = 0x01; diff --git a/board/miromico/hammerhead/hammerhead.c b/board/miromico/hammerhead/hammerhead.c index d82fee7b90..a0c7d3b323 100644 --- a/board/miromico/hammerhead/hammerhead.c +++ b/board/miromico/hammerhead/hammerhead.c @@ -21,14 +21,14 @@ DECLARE_GLOBAL_DATA_PTR; struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = { { - .virt_pgno = CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT, - .nr_pages = CONFIG_SYS_FLASH_SIZE >> PAGE_SHIFT, - .phys = (CONFIG_SYS_FLASH_BASE >> PAGE_SHIFT) + .virt_pgno = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT, + .nr_pages = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT, + .phys = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT) | MMU_VMR_CACHE_NONE, }, { - .virt_pgno = CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT, - .nr_pages = EBI_SDRAM_SIZE >> PAGE_SHIFT, - .phys = (CONFIG_SYS_SDRAM_BASE >> PAGE_SHIFT) + .virt_pgno = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT, + .nr_pages = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT, + .phys = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT) | MMU_VMR_CACHE_WRBACK, }, }; @@ -63,6 +63,8 @@ int board_early_init_f(void) hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); portmux_enable_ebi(32, 23, 0, PORTMUX_DRIVE_HIGH); + sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config); + portmux_enable_usart1(PORTMUX_DRIVE_MIN); #if defined(CONFIG_MACB) @@ -74,24 +76,6 @@ int board_early_init_f(void) return 0; } -phys_size_t initdram(int board_type) -{ - unsigned long expected_size; - unsigned long actual_size; - void *sdram_base; - - sdram_base = uncached(EBI_SDRAM_BASE); - - expected_size = sdram_init(sdram_base, &sdram_config); - actual_size = get_ram_size(sdram_base, expected_size); - - if (expected_size != actual_size) - printf("Warning: Only %lu of %lu MiB SDRAM is working\n", - actual_size >> 20, expected_size >> 20); - - return actual_size; -} - int board_early_init_r(void) { gd->bd->bi_phy_id[0] = 0x01; diff --git a/board/nokia/rx51/lowlevel_init.S b/board/nokia/rx51/lowlevel_init.S index e25290966c..9d4ea1b3f9 100644 --- a/board/nokia/rx51/lowlevel_init.S +++ b/board/nokia/rx51/lowlevel_init.S @@ -37,7 +37,8 @@ ih_magic: /* IH_MAGIC in big endian from include/image.h */ .global save_boot_params save_boot_params: - + /* Get return address */ + ldr lr, =save_boot_params_ret /* Copy valid attached kernel to address KERNEL_ADDRESS */ diff --git a/board/nvidia/cardhu/cardhu.c b/board/nvidia/cardhu/cardhu.c index 95c4ff2509..1540526a61 100644 --- a/board/nvidia/cardhu/cardhu.c +++ b/board/nvidia/cardhu/cardhu.c @@ -46,7 +46,7 @@ void board_sdmmc_voltage_init(void) int ret; int i; - ret = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, &dev); + ret = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev); if (ret) { debug("%s: Cannot find PMIC I2C chip\n", __func__); return; @@ -57,7 +57,7 @@ void board_sdmmc_voltage_init(void) reg = 0x32; for (i = 0; i < MAX_I2C_RETRY; ++i) { - if (i2c_write(dev, reg, data_buffer, 1)) + if (dm_i2c_write(dev, reg, data_buffer, 1)) udelay(100); } @@ -66,7 +66,7 @@ void board_sdmmc_voltage_init(void) reg = 0x67; for (i = 0; i < MAX_I2C_RETRY; ++i) { - if (i2c_write(dev, reg, data_buffer, 1)) + if (dm_i2c_write(dev, reg, data_buffer, 1)) udelay(100); } } @@ -94,7 +94,7 @@ int tegra_pcie_board_init(void) u8 addr, data[1]; int err; - err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, &dev); + err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev); if (err) { debug("failed to find PMU bus\n"); return err; @@ -104,7 +104,7 @@ int tegra_pcie_board_init(void) data[0] = 0x15; addr = 0x30; - err = i2c_write(dev, addr, data, 1); + err = dm_i2c_write(dev, addr, data, 1); if (err) { debug("failed to set VDD supply\n"); return err; @@ -121,7 +121,7 @@ int tegra_pcie_board_init(void) data[0] = 0x15; addr = 0x31; - err = i2c_write(dev, addr, data, 1); + err = dm_i2c_write(dev, addr, data, 1); if (err) { debug("failed to set AVDD supply\n"); return err; diff --git a/board/nvidia/dalmore/dalmore.c b/board/nvidia/dalmore/dalmore.c index 2a737468dd..d7c1a695ff 100644 --- a/board/nvidia/dalmore/dalmore.c +++ b/board/nvidia/dalmore/dalmore.c @@ -55,7 +55,7 @@ void board_sdmmc_voltage_init(void) uchar reg, data_buffer[1]; int ret; - ret = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, &dev); + ret = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev); if (ret) { debug("%s: Cannot find PMIC I2C chip\n", __func__); return; @@ -65,7 +65,7 @@ void board_sdmmc_voltage_init(void) data_buffer[0] = 0x31; reg = 0x61; - ret = i2c_write(dev, reg, data_buffer, 1); + ret = dm_i2c_write(dev, reg, data_buffer, 1); if (ret) printf("%s: PMU i2c_write %02X<-%02X returned %d\n", __func__, reg, data_buffer[0], ret); @@ -74,7 +74,7 @@ void board_sdmmc_voltage_init(void) data_buffer[0] = 0x01; reg = 0x60; - ret = i2c_write(dev, reg, data_buffer, 1); + ret = dm_i2c_write(dev, reg, data_buffer, 1); if (ret) printf("%s: PMU i2c_write %02X<-%02X returned %d\n", __func__, reg, data_buffer[0], ret); @@ -83,12 +83,12 @@ void board_sdmmc_voltage_init(void) data_buffer[0] = 0x03; reg = 0x14; - ret = i2c_get_chip_for_busnum(0, BAT_I2C_ADDRESS, &dev); + ret = i2c_get_chip_for_busnum(0, BAT_I2C_ADDRESS, 1, &dev); if (ret) { debug("%s: Cannot find charger I2C chip\n", __func__); return; } - ret = i2c_write(dev, reg, data_buffer, 1); + ret = dm_i2c_write(dev, reg, data_buffer, 1); if (ret) printf("%s: BAT i2c_write %02X<-%02X returned %d\n", __func__, reg, data_buffer[0], ret); diff --git a/board/nvidia/whistler/whistler.c b/board/nvidia/whistler/whistler.c index 3114b20be0..3476f1159f 100644 --- a/board/nvidia/whistler/whistler.c +++ b/board/nvidia/whistler/whistler.c @@ -27,21 +27,21 @@ void pin_mux_mmc(void) int ret; /* Turn on MAX8907B LDO12 to 2.8V for J40 power */ - ret = i2c_get_chip_for_busnum(0, 0x3c, &dev); + ret = i2c_get_chip_for_busnum(0, 0x3c, 1, &dev); if (ret) { printf("%s: Cannot find MAX8907B I2C chip\n", __func__); return; } val = 0x29; - ret = i2c_write(dev, 0x46, &val, 1); + ret = dm_i2c_write(dev, 0x46, &val, 1); if (ret) printf("i2c_write 0 0x3c 0x46 failed: %d\n", ret); val = 0x00; - ret = i2c_write(dev, 0x45, &val, 1); + ret = dm_i2c_write(dev, 0x45, &val, 1); if (ret) printf("i2c_write 0 0x3c 0x45 failed: %d\n", ret); val = 0x1f; - ret = i2c_write(dev, 0x44, &val, 1); + ret = dm_i2c_write(dev, 0x44, &val, 1); if (ret) printf("i2c_write 0 0x3c 0x44 failed: %d\n", ret); @@ -64,17 +64,17 @@ void pin_mux_usb(void) */ /* Turn on TAC6416's GPIO 0+1 for USB1/3's VBUS */ - ret = i2c_get_chip_for_busnum(0, 0x20, &dev); + ret = i2c_get_chip_for_busnum(0, 0x20, 1, &dev); if (ret) { printf("%s: Cannot find TAC6416 I2C chip\n", __func__); return; } val = 0x03; - ret = i2c_write(dev, 2, &val, 1); + ret = dm_i2c_write(dev, 2, &val, 1); if (ret) printf("i2c_write 0 0x20 2 failed: %d\n", ret); val = 0xfc; - ret = i2c_write(dev, 6, &val, 1); + ret = dm_i2c_write(dev, 6, &val, 1); if (ret) printf("i2c_write 0 0x20 6 failed: %d\n", ret); } diff --git a/board/phytec/pcm051/Kconfig b/board/phytec/pcm051/Kconfig index 2cc0d8872d..65094cf9fd 100644 --- a/board/phytec/pcm051/Kconfig +++ b/board/phytec/pcm051/Kconfig @@ -12,4 +12,13 @@ config SYS_SOC config SYS_CONFIG_NAME default "pcm051" +config DM + default y if !SPL_BUILD + +config DM_GPIO + default y if !SPL_BUILD + +config DM_SERIAL + default y if !SPL_BUILD + endif diff --git a/board/raspberrypi/rpi/Makefile b/board/raspberrypi/rpi/Makefile index c53c92b1dd..4ce2c983b3 100644 --- a/board/raspberrypi/rpi/Makefile +++ b/board/raspberrypi/rpi/Makefile @@ -1,15 +1,7 @@ # -# See file CREDITS for list of people who contributed to this -# project. +# (C) Copyright 2012 Stephen Warren # -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License -# version 2 as published by the Free Software Foundation. -# -# This program is distributed in the hope that it will be useful, but -# WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. +# SPDX-License-Identifier: GPL-2.0 # obj-y := rpi.o diff --git a/board/raspberrypi/rpi/rpi.c b/board/raspberrypi/rpi/rpi.c index c18271fce8..50a699bb9e 100644 --- a/board/raspberrypi/rpi/rpi.c +++ b/board/raspberrypi/rpi/rpi.c @@ -1,23 +1,14 @@ /* - * (C) Copyright 2012-2013 Stephen Warren + * (C) Copyright 2012-2013,2015 Stephen Warren * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License - * version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, but - * WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. + * SPDX-License-Identifier: GPL-2.0 */ #include <common.h> #include <config.h> #include <dm.h> #include <fdt_support.h> +#include <fdt_simplefb.h> #include <lcd.h> #include <mmc.h> #include <asm/gpio.h> @@ -38,7 +29,11 @@ U_BOOT_DEVICE(bcm2835_gpios) = { }; static const struct pl01x_serial_platdata serial_platdata = { +#ifdef CONFIG_BCM2836 + .base = 0x3f201000, +#else .base = 0x20201000, +#endif .type = TYPE_PL011, .clock = 3000000, }; @@ -86,9 +81,20 @@ static const struct { } models[] = { [0] = { "Unknown model", +#ifdef CONFIG_BCM2836 + "bcm2836-rpi-other.dtb", +#else "bcm2835-rpi-other.dtb", +#endif false, }, +#ifdef CONFIG_BCM2836 + [BCM2836_BOARD_REV_2_B] = { + "2 Model B", + "bcm2836-rpi-2-b.dtb", + true, + }, +#else [BCM2835_BOARD_REV_B_I2C0_2] = { "Model B (no P5)", "bcm2835-rpi-b-i2c0.dtb", @@ -159,6 +165,7 @@ static const struct { "bcm2835-rpi-a-plus.dtb", false, }, +#endif }; u32 rpi_board_rev = 0; @@ -266,7 +273,15 @@ static void get_board_rev(void) return; } + /* + * For details of old-vs-new scheme, see: + * https://github.com/pimoroni/RPi.version/blob/master/RPi/version.py + * http://www.raspberrypi.org/forums/viewtopic.php?f=63&t=99293&p=690282 + * (a few posts down) + */ rpi_board_rev = msg->get_board_rev.body.resp.rev; + if (rpi_board_rev & 0x800000) + rpi_board_rev = (rpi_board_rev >> 4) & 0xff; if (rpi_board_rev >= ARRAY_SIZE(models)) { printf("RPI: Board rev %u outside known range\n", rpi_board_rev); @@ -278,7 +293,7 @@ static void get_board_rev(void) } name = models[rpi_board_rev].name; - printf("RPI model: %s\n", name); + printf("RPI %s\n", name); } int board_init(void) diff --git a/board/raspberrypi/rpi_2/Kconfig b/board/raspberrypi/rpi_2/Kconfig new file mode 100644 index 0000000000..032184d5ad --- /dev/null +++ b/board/raspberrypi/rpi_2/Kconfig @@ -0,0 +1,15 @@ +if TARGET_RPI_2 + +config SYS_BOARD + default "rpi_2" + +config SYS_VENDOR + default "raspberrypi" + +config SYS_SOC + default "bcm2835" + +config SYS_CONFIG_NAME + default "rpi_2" + +endif diff --git a/board/raspberrypi/rpi_2/MAINTAINERS b/board/raspberrypi/rpi_2/MAINTAINERS new file mode 100644 index 0000000000..85a480c9d1 --- /dev/null +++ b/board/raspberrypi/rpi_2/MAINTAINERS @@ -0,0 +1,6 @@ +RPI_2 BOARD +M: Stephen Warren <swarren@wwwdotorg.org> +S: Maintained +F: board/raspberrypi/rpi_2/ +F: include/configs/rpi_2.h +F: configs/rpi_2_defconfig diff --git a/board/raspberrypi/rpi_2/Makefile b/board/raspberrypi/rpi_2/Makefile new file mode 100644 index 0000000000..d82cd21f4c --- /dev/null +++ b/board/raspberrypi/rpi_2/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2012,2015 Stephen Warren +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-y := ../rpi/rpi.o diff --git a/board/renesas/silk/Kconfig b/board/renesas/silk/Kconfig new file mode 100644 index 0000000000..07aee0e50f --- /dev/null +++ b/board/renesas/silk/Kconfig @@ -0,0 +1,12 @@ +if TARGET_SILK + +config SYS_BOARD + default "silk" + +config SYS_VENDOR + default "renesas" + +config SYS_CONFIG_NAME + default "silk" + +endif diff --git a/board/renesas/silk/MAINTAINERS b/board/renesas/silk/MAINTAINERS new file mode 100644 index 0000000000..b566ccfbd9 --- /dev/null +++ b/board/renesas/silk/MAINTAINERS @@ -0,0 +1,6 @@ +SILK BOARD +M: Cogent Embedded, Inc. <source@cogentembedded.com> +S: Maintained +F: board/renesas/silk/ +F: include/configs/silk.h +F: configs/silk_defconfig diff --git a/board/renesas/silk/Makefile b/board/renesas/silk/Makefile new file mode 100644 index 0000000000..e6eea6142e --- /dev/null +++ b/board/renesas/silk/Makefile @@ -0,0 +1,10 @@ +# +# board/renesas/silk/Makefile +# +# Copyright (C) 2015 Renesas Electronics Corporation +# Copyright (C) 2015 Cogent Embedded, Inc. +# +# SPDX-License-Identifier: GPL-2.0 +# + +obj-y := silk.o qos.o ../rcar-gen2-common/common.o diff --git a/board/renesas/silk/qos.c b/board/renesas/silk/qos.c new file mode 100644 index 0000000000..4f6e46ce52 --- /dev/null +++ b/board/renesas/silk/qos.c @@ -0,0 +1,951 @@ +/* + * board/renesas/silk/qos.c + * + * Copyright (C) 2015 Renesas Electronics Corporation + * Copyright (C) 2015 Cogent Embedded, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + * + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/mach-types.h> +#include <asm/io.h> +#include <asm/arch/rmobile.h> + +#if defined(CONFIG_RMOBILE_EXTRAM_BOOT) +/* QoS version 0.11 */ + +enum { + DBSC3_00, DBSC3_01, DBSC3_02, DBSC3_03, DBSC3_04, + DBSC3_05, DBSC3_06, DBSC3_07, DBSC3_08, DBSC3_09, + DBSC3_10, DBSC3_11, DBSC3_12, DBSC3_13, DBSC3_14, + DBSC3_15, + DBSC3_NR, +}; + +static u32 dbsc3_0_r_qos_addr[DBSC3_NR] = { + [DBSC3_00] = DBSC3_0_QOS_R0_BASE, + [DBSC3_01] = DBSC3_0_QOS_R1_BASE, + [DBSC3_02] = DBSC3_0_QOS_R2_BASE, + [DBSC3_03] = DBSC3_0_QOS_R3_BASE, + [DBSC3_04] = DBSC3_0_QOS_R4_BASE, + [DBSC3_05] = DBSC3_0_QOS_R5_BASE, + [DBSC3_06] = DBSC3_0_QOS_R6_BASE, + [DBSC3_07] = DBSC3_0_QOS_R7_BASE, + [DBSC3_08] = DBSC3_0_QOS_R8_BASE, + [DBSC3_09] = DBSC3_0_QOS_R9_BASE, + [DBSC3_10] = DBSC3_0_QOS_R10_BASE, + [DBSC3_11] = DBSC3_0_QOS_R11_BASE, + [DBSC3_12] = DBSC3_0_QOS_R12_BASE, + [DBSC3_13] = DBSC3_0_QOS_R13_BASE, + [DBSC3_14] = DBSC3_0_QOS_R14_BASE, + [DBSC3_15] = DBSC3_0_QOS_R15_BASE, +}; + +static u32 dbsc3_0_w_qos_addr[DBSC3_NR] = { + [DBSC3_00] = DBSC3_0_QOS_W0_BASE, + [DBSC3_01] = DBSC3_0_QOS_W1_BASE, + [DBSC3_02] = DBSC3_0_QOS_W2_BASE, + [DBSC3_03] = DBSC3_0_QOS_W3_BASE, + [DBSC3_04] = DBSC3_0_QOS_W4_BASE, + [DBSC3_05] = DBSC3_0_QOS_W5_BASE, + [DBSC3_06] = DBSC3_0_QOS_W6_BASE, + [DBSC3_07] = DBSC3_0_QOS_W7_BASE, + [DBSC3_08] = DBSC3_0_QOS_W8_BASE, + [DBSC3_09] = DBSC3_0_QOS_W9_BASE, + [DBSC3_10] = DBSC3_0_QOS_W10_BASE, + [DBSC3_11] = DBSC3_0_QOS_W11_BASE, + [DBSC3_12] = DBSC3_0_QOS_W12_BASE, + [DBSC3_13] = DBSC3_0_QOS_W13_BASE, + [DBSC3_14] = DBSC3_0_QOS_W14_BASE, + [DBSC3_15] = DBSC3_0_QOS_W15_BASE, +}; + +void qos_init(void) +{ + int i; + struct rcar_s3c *s3c; + struct rcar_s3c_qos *s3c_qos; + struct rcar_dbsc3_qos *qos_addr; + struct rcar_mxi *mxi; + struct rcar_mxi_qos *mxi_qos; + struct rcar_axi_qos *axi_qos; + + /* DBSC DBADJ2 */ + writel(0x20042004, DBSC3_0_DBADJ2); + + /* S3C -QoS */ + s3c = (struct rcar_s3c *)S3C_BASE; + writel(0x1F0D0B0A, &s3c->s3crorr); + writel(0x1F0D0B09, &s3c->s3cworr); + + /* QoS Control Registers */ + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI0_BASE; + writel(0x00890089, &s3c_qos->s3cqos0); + writel(0x20960010, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA2200, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960010, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA2200, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_CCI1_BASE; + writel(0x00890089, &s3c_qos->s3cqos0); + writel(0x20960010, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA2200, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960010, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA2200, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_MXI_BASE; + writel(0x80928092, &s3c_qos->s3cqos0); + writel(0x20960020, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA20DC, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960020, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA20DC, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + s3c_qos = (struct rcar_s3c_qos *)S3C_QOS_AXI_BASE; + writel(0x00820082, &s3c_qos->s3cqos0); + writel(0x20960020, &s3c_qos->s3cqos1); + writel(0x20302030, &s3c_qos->s3cqos2); + writel(0x20AA20FA, &s3c_qos->s3cqos3); + writel(0x00002032, &s3c_qos->s3cqos4); + writel(0x20960020, &s3c_qos->s3cqos5); + writel(0x20302030, &s3c_qos->s3cqos6); + writel(0x20AA20FA, &s3c_qos->s3cqos7); + writel(0x00002032, &s3c_qos->s3cqos8); + + /* DBSC -QoS */ + /* DBSC0 - Read */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_r_qos_addr[i]; + writel(0x00000002, &qos_addr->dblgcnt); + writel(0x0000207D, &qos_addr->dbtmval0); + writel(0x00002053, &qos_addr->dbtmval1); + writel(0x0000202A, &qos_addr->dbtmval2); + writel(0x00001FBD, &qos_addr->dbtmval3); + writel(0x00000001, &qos_addr->dbrqctr); + writel(0x00002064, &qos_addr->dbthres0); + writel(0x0000203E, &qos_addr->dbthres1); + writel(0x00002019, &qos_addr->dbthres2); + writel(0x00000001, &qos_addr->dblgqon); + } + + /* DBSC0 - Write */ + for (i = DBSC3_00; i < DBSC3_NR; i++) { + qos_addr = (struct rcar_dbsc3_qos *)dbsc3_0_w_qos_addr[i]; + writel(0x00000002, &qos_addr->dblgcnt); + writel(0x0000207D, &qos_addr->dbtmval0); + writel(0x00002053, &qos_addr->dbtmval1); + writel(0x00002043, &qos_addr->dbtmval2); + writel(0x00002030, &qos_addr->dbtmval3); + writel(0x00000001, &qos_addr->dbrqctr); + writel(0x00002064, &qos_addr->dbthres0); + writel(0x0000203E, &qos_addr->dbthres1); + writel(0x00002031, &qos_addr->dbthres2); + writel(0x00000001, &qos_addr->dblgqon); + } + + /* CCI-400 -QoS */ + writel(0x20000800, CCI_400_MAXOT_1); + writel(0x20000800, CCI_400_MAXOT_2); + writel(0x0000000C, CCI_400_QOSCNTL_1); + writel(0x0000000C, CCI_400_QOSCNTL_2); + + /* MXI -QoS */ + /* Transaction Control (MXI) */ + mxi = (struct rcar_mxi *)MXI_BASE; + writel(0x00000013, &mxi->mxrtcr); + writel(0x00000013, &mxi->mxwtcr); + writel(0x00780080, &mxi->mxsaar0); + writel(0x02000800, &mxi->mxsaar1); + + /* QoS Control (MXI) */ + mxi_qos = (struct rcar_mxi_qos *)MXI_QOS_BASE; + writel(0x0000000C, &mxi_qos->vspdu0); + writel(0x0000000E, &mxi_qos->du0); + + /* AXI -QoS */ + /* Transaction Control (MXI) */ + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SYX64TO128_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AVB_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX0_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX1_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_IMUX2_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_LBS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUDS_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUM_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MMUS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_RTX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDS1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB20_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_USB22_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_AX2M_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CC50_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002029, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CCI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_CS_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_DDM_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_ETH_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_MPXM_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_SDM1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000214C, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_TRAB_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x000020A6, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM0_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI_UDM1_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (RT-AXI) */ + axi_qos = (struct rcar_axi_qos *)RT_AXI_SHX_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_DBG_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_RTX64TO128_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)RT_AXI_SY2RT_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (MP-AXI) */ + axi_qos = (struct rcar_axi_qos *)MP_AXI_ADSP_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002037, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002014, &axi_qos->qosctset0); + writel(0x00000040, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_ASDS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002014, &axi_qos->qosctset0); + writel(0x00000040, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_MLP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00001FF0, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00002001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_MMUMP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPU_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x00002053, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MP_AXI_SPUC_BASE; + writel(0x00000000, &axi_qos->qosconf); + writel(0x0000206E, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (SYS-AXI256) */ + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_AXI128TO256_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_SYX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MPX_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)SYS_AXI256_MXI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020EB, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (CCI-AXI) */ + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS0_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_SYX2_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUDS_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUM_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MXI_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x00002245, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUS1_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)CCI_AXI_MMUMP_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002004, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000000, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + /* QoS Register (Media-AXI) */ + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXR_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020DC, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x000020AA, &axi_qos->qosthres0); + writel(0x00002032, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_MXW_BASE; + writel(0x00000002, &axi_qos->qosconf); + writel(0x000020DC, &axi_qos->qosctset0); + writel(0x00002096, &axi_qos->qosctset1); + writel(0x00002030, &axi_qos->qosctset2); + writel(0x00002030, &axi_qos->qosctset3); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x000020AA, &axi_qos->qosthres0); + writel(0x00002032, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_TDMW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPDU0CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002190, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VIN0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00001FF0, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00002001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_FDP0W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMSW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSP1W_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_IMRW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0R_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VSPD0W_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x000020C8, &axi_qos->qosctset0); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0R_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x00002063, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_DU0W_BASE; + writel(0x00000003, &axi_qos->qosconf); + writel(0x00002063, &axi_qos->qosctset0); + writel(0x00000001, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0CW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VR_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VCP0VW_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00000001, &axi_qos->qosthres0); + writel(0x00000001, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); + + axi_qos = (struct rcar_axi_qos *)MEDIA_AXI_VPC0R_BASE; + writel(0x00000001, &axi_qos->qosconf); + writel(0x00002073, &axi_qos->qosctset0); + writel(0x00000020, &axi_qos->qosreqctr); + writel(0x00002064, &axi_qos->qosthres0); + writel(0x00002004, &axi_qos->qosthres1); + writel(0x00000001, &axi_qos->qosthres2); + writel(0x00000001, &axi_qos->qosqon); +} +#else /* CONFIG_RMOBILE_EXTRAM_BOOT */ +void qos_init(void) +{ +} +#endif /* CONFIG_RMOBILE_EXTRAM_BOOT */ diff --git a/board/renesas/silk/qos.h b/board/renesas/silk/qos.h new file mode 100644 index 0000000000..75a20bb075 --- /dev/null +++ b/board/renesas/silk/qos.h @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2015 Renesas Electronics Corporation + * Copyright (C) 2015 Cogent Embedded, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef __QOS_H__ +#define __QOS_H__ + +void qos_init(void); + +#endif diff --git a/board/renesas/silk/silk.c b/board/renesas/silk/silk.c new file mode 100644 index 0000000000..dfd9a9d3e4 --- /dev/null +++ b/board/renesas/silk/silk.c @@ -0,0 +1,163 @@ +/* + * board/renesas/silk/silk.c + * + * Copyright (C) 2015 Renesas Electronics Corporation + * Copyright (C) 2015 Cogent Embedded, Inc. + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <malloc.h> +#include <asm/processor.h> +#include <asm/mach-types.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/arch/rmobile.h> +#include <asm/arch/rcar-mstp.h> +#include <asm/arch/mmc.h> +#include <netdev.h> +#include <miiphy.h> +#include <i2c.h> +#include <div64.h> +#include "qos.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define CLK2MHZ(clk) (clk / 1000 / 1000) +void s_init(void) +{ + struct rcar_rwdt *rwdt = (struct rcar_rwdt *)RWDT_BASE; + struct rcar_swdt *swdt = (struct rcar_swdt *)SWDT_BASE; + + /* Watchdog init */ + writel(0xA5A5A500, &rwdt->rwtcsra); + writel(0xA5A5A500, &swdt->swtcsra); + + /* QoS */ + qos_init(); +} + +#define TMU0_MSTP125 (1 << 25) +#define SCIF2_MSTP719 (1 << 19) +#define ETHER_MSTP813 (1 << 13) +#define IIC1_MSTP323 (1 << 23) +#define MMC0_MSTP315 (1 << 15) + +int board_early_init_f(void) +{ + /* TMU */ + mstp_clrbits_le32(MSTPSR1, SMSTPCR1, TMU0_MSTP125); + + /* SCIF2 */ + mstp_clrbits_le32(MSTPSR7, SMSTPCR7, SCIF2_MSTP719); + + /* ETHER */ + mstp_clrbits_le32(MSTPSR8, SMSTPCR8, ETHER_MSTP813); + + /* IIC1 / sh-i2c ch1 */ + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, IIC1_MSTP323); + +#ifdef CONFIG_SH_MMCIF + /* MMC */ + mstp_clrbits_le32(MSTPSR3, SMSTPCR3, MMC0_MSTP315); +#endif + return 0; +} + +int board_init(void) +{ + /* adress of boot parameters */ + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; + + /* Init PFC controller */ + r8a7794_pinmux_init(); + + /* Ether Enable */ + gpio_request(GPIO_FN_ETH_CRS_DV, NULL); + gpio_request(GPIO_FN_ETH_RX_ER, NULL); + gpio_request(GPIO_FN_ETH_RXD0, NULL); + gpio_request(GPIO_FN_ETH_RXD1, NULL); + gpio_request(GPIO_FN_ETH_LINK, NULL); + gpio_request(GPIO_FN_ETH_REFCLK, NULL); + gpio_request(GPIO_FN_ETH_MDIO, NULL); + gpio_request(GPIO_FN_ETH_TXD1, NULL); + gpio_request(GPIO_FN_ETH_TX_EN, NULL); + gpio_request(GPIO_FN_ETH_MAGIC, NULL); + gpio_request(GPIO_FN_ETH_TXD0, NULL); + gpio_request(GPIO_FN_ETH_MDC, NULL); + gpio_request(GPIO_FN_IRQ8, NULL); + + /* PHY reset */ + gpio_request(GPIO_GP_1_24, NULL); + gpio_direction_output(GPIO_GP_1_24, 0); + mdelay(20); + gpio_set_value(GPIO_GP_1_24, 1); + udelay(1); + + return 0; +} + +#define CXR24 0xEE7003C0 /* MAC address high register */ +#define CXR25 0xEE7003C8 /* MAC address low register */ +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_SH_ETHER + int ret = -ENODEV; + u32 val; + unsigned char enetaddr[6]; + + ret = sh_eth_initialize(bis); + if (!eth_getenv_enetaddr("ethaddr", enetaddr)) + return ret; + + /* Set Mac address */ + val = enetaddr[0] << 24 | enetaddr[1] << 16 | + enetaddr[2] << 8 | enetaddr[3]; + writel(val, CXR24); + + val = enetaddr[4] << 8 | enetaddr[5]; + writel(val, CXR25); + + return ret; +#else + return 0; +#endif +} + +int board_mmc_init(bd_t *bis) +{ + int ret = 0; + +#ifdef CONFIG_SH_MMCIF + /* MMC0 */ + gpio_request(GPIO_GP_4_31, NULL); + gpio_set_value(GPIO_GP_4_31, 1); + + ret = mmcif_mmc_init(); +#endif + return ret; +} + +int dram_init(void) +{ + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} + +const struct rmobile_sysinfo sysinfo = { + CONFIG_RMOBILE_BOARD_STRING +}; + +void reset_cpu(ulong addr) +{ + u8 val; + + i2c_set_bus_num(1); /* PowerIC connected to ch1 */ + i2c_read(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); + val |= 0x02; + i2c_write(CONFIG_SYS_I2C_POWERIC_ADDR, 0x13, 1, &val, 1); +} diff --git a/board/ronetix/pm9261/Kconfig b/board/ronetix/pm9261/Kconfig index a4934c582e..8c54198102 100644 --- a/board/ronetix/pm9261/Kconfig +++ b/board/ronetix/pm9261/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "ronetix" -config SYS_SOC - default "at91" - config SYS_CONFIG_NAME default "pm9261" diff --git a/board/ronetix/pm9263/Kconfig b/board/ronetix/pm9263/Kconfig index 339a6ea169..5b47d34845 100644 --- a/board/ronetix/pm9263/Kconfig +++ b/board/ronetix/pm9263/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "ronetix" -config SYS_SOC - default "at91" - config SYS_CONFIG_NAME default "pm9263" diff --git a/board/ronetix/pm9g45/Kconfig b/board/ronetix/pm9g45/Kconfig index 65fc5c4838..ad5309f816 100644 --- a/board/ronetix/pm9g45/Kconfig +++ b/board/ronetix/pm9g45/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "ronetix" -config SYS_SOC - default "at91" - config SYS_CONFIG_NAME default "pm9g45" diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index 8b4c8e9a9d..da2245ff9d 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -355,3 +355,31 @@ int misc_init_r(void) return 0; } #endif + +void reset_misc(void) +{ + struct gpio_desc gpio = {}; + int node; + + node = fdt_node_offset_by_compatible(gd->fdt_blob, 0, + "samsung,emmc-reset"); + if (node < 0) + return; + + gpio_request_by_name_nodev(gd->fdt_blob, node, "reset-gpio", 0, &gpio, + GPIOD_IS_OUT); + + if (dm_gpio_is_valid(&gpio)) { + /* + * Reset eMMC + * + * FIXME: Need to optimize delay time. Minimum 1usec pulse is + * required by 'JEDEC Standard No.84-A441' (eMMC) + * document but real delay time is expected to greater + * than 1usec. + */ + dm_gpio_set_value(&gpio, 0); + mdelay(10); + dm_gpio_set_value(&gpio, 1); + } +} diff --git a/board/samsung/goni/Kconfig b/board/samsung/goni/Kconfig index cbbf5a9315..2c5d3fc3be 100644 --- a/board/samsung/goni/Kconfig +++ b/board/samsung/goni/Kconfig @@ -12,4 +12,13 @@ config SYS_SOC config SYS_CONFIG_NAME default "s5p_goni" +config DM + default y if !SPL_BUILD + +config DM_GPIO + default y if !SPL_BUILD + +config DM_SERIAL + default y if !SPL_BUILD + endif diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index b7d23817e1..bff6ac928c 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -248,12 +248,12 @@ static void board_clock_init(void) * MOUTc2c = 800 Mhz * MOUTpwi = 108 MHz * - * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 400 (1) + * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 200 (3) * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1) * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1) * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5) */ - set = G2D_ACP_RATIO(1) | C2C_RATIO(1) | PWI_RATIO(5) | + set = G2D_ACP_RATIO(3) | C2C_RATIO(1) | PWI_RATIO(5) | C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1); clrsetbits_le32(&clk->div_dmc1, clr, set); @@ -415,15 +415,6 @@ static int pmic_init_max77686(void) return 0; } -#ifdef CONFIG_SYS_I2C_INIT_BOARD -static void board_init_i2c(void) -{ - /* I2C_0 */ - if (exynos_pinmux_config(PERIPH_ID_I2C0, PINMUX_FLAG_NONE)) - debug("I2C%d not configured\n", (I2C_0)); -} -#endif - int exynos_early_init_f(void) { board_clock_init(); @@ -444,10 +435,7 @@ int exynos_init(void) int exynos_power_init(void) { -#ifdef CONFIG_SYS_I2C_INIT_BOARD - board_init_i2c(); -#endif - pmic_init(I2C_0); + pmic_init(0); pmic_init_max77686(); return 0; @@ -515,11 +503,3 @@ int board_usb_init(int index, enum usb_init_type init) return s3c_udc_probe(&s5pc210_otg_data); } #endif - -void reset_misc(void) -{ - /* Reset eMMC*/ - gpio_set_value(EXYNOS4X12_GPIO_K12, 0); - mdelay(10); - gpio_set_value(EXYNOS4X12_GPIO_K12, 1); -} diff --git a/board/samsung/smdk5420/Kconfig b/board/samsung/smdk5420/Kconfig index a9d62fffa5..576abaea69 100644 --- a/board/samsung/smdk5420/Kconfig +++ b/board/samsung/smdk5420/Kconfig @@ -22,6 +22,9 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "peach-pi" +config DM_CROS_EC + default y + endif if TARGET_PEACH_PIT @@ -35,6 +38,9 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "peach-pit" +config DM_CROS_EC + default y + endif if TARGET_SMDK5420 diff --git a/board/samsung/smdkc100/Kconfig b/board/samsung/smdkc100/Kconfig index d2157b4d05..996fe3cc45 100644 --- a/board/samsung/smdkc100/Kconfig +++ b/board/samsung/smdkc100/Kconfig @@ -12,4 +12,13 @@ config SYS_SOC config SYS_CONFIG_NAME default "smdkc100" +config DM + default y if !SPL_BUILD + +config DM_GPIO + default y if !SPL_BUILD + +config DM_SERIAL + default y if !SPL_BUILD + endif diff --git a/board/sandbox/README.sandbox b/board/sandbox/README.sandbox index 5f879f5506..3c0df17845 100644 --- a/board/sandbox/README.sandbox +++ b/board/sandbox/README.sandbox @@ -18,8 +18,8 @@ create unit tests which we can run to test this upper level code. CONFIG_SANDBOX is defined when building a native board. -The chosen vendor and board names are also 'sandbox', so there is a single -board in board/sandbox. +The board name is 'sandbox' but the vendor name is unset, so there is a +single board in board/sandbox. CONFIG_SANDBOX_BIG_ENDIAN should be defined when running on big-endian machines. diff --git a/board/siemens/corvus/Kconfig b/board/siemens/corvus/Kconfig index 7b505aac36..69fe0f0723 100644 --- a/board/siemens/corvus/Kconfig +++ b/board/siemens/corvus/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "siemens" -config SYS_SOC - default "at91" - config SYS_CONFIG_NAME default "corvus" diff --git a/board/siemens/taurus/Kconfig b/board/siemens/taurus/Kconfig index c07d244bc3..cf71e4ce56 100644 --- a/board/siemens/taurus/Kconfig +++ b/board/siemens/taurus/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "siemens" -config SYS_SOC - default "at91" - config SYS_CONFIG_NAME default "taurus" diff --git a/board/silica/pengwyn/Kconfig b/board/silica/pengwyn/Kconfig index f2e1098f62..6ecda8041c 100644 --- a/board/silica/pengwyn/Kconfig +++ b/board/silica/pengwyn/Kconfig @@ -12,4 +12,13 @@ config SYS_SOC config SYS_CONFIG_NAME default "pengwyn" +config DM + default y if !SPL_BUILD + +config DM_GPIO + default y if !SPL_BUILD + +config DM_SERIAL + default y if !SPL_BUILD + endif diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig index 738b55e74a..9cf54e51ac 100644 --- a/board/sunxi/Kconfig +++ b/board/sunxi/Kconfig @@ -39,16 +39,23 @@ config DRAM_CLK default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I ---help--- Set the dram clock speed, valid range 240 - 480, must be a multiple - of 24. Note on sun4i / sun5i / sun7i this is only used by boards - which use dram autoconfig. + of 24. + +if MACH_SUN5I || MACH_SUN7I +config DRAM_MBUS_CLK + int "sunxi mbus clock speed" + default 300 + ---help--- + Set the mbus clock speed. The maximum on sun5i hardware is 300MHz. + +endif config DRAM_ZQ int "sunxi dram zq value" default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I default 127 if MACH_SUN7I ---help--- - Set the dram zq value. Note on sun4i / sun5i / sun7i this is only - used by boards which use dram autoconfig. + Set the dram zq value. if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I config DRAM_EMR1 @@ -56,98 +63,81 @@ config DRAM_EMR1 default 0 if MACH_SUN4I default 4 if MACH_SUN5I || MACH_SUN7I ---help--- - Set the dram controller emr1 value. Note this is only used by boards - which use dram autoconfig. -endif - -config SYS_CONFIG_NAME - default "sun4i" if MACH_SUN4I - default "sun5i" if MACH_SUN5I - default "sun6i" if MACH_SUN6I - default "sun7i" if MACH_SUN7I - default "sun8i" if MACH_SUN8I - -choice - prompt "Board" - -config TARGET_A10S_OLINUXINO_M - bool "A10S_OLINUXINO_M" - depends on MACH_SUN5I - -config TARGET_A13_OLINUXINOM - bool "A13_OLINUXINOM" - depends on MACH_SUN5I - -config TARGET_A13_OLINUXINO - bool "A13_OLINUXINO" - depends on MACH_SUN5I + Set the dram controller emr1 value. -config TARGET_A20_OLINUXINO_L2 - bool "A20_OLINUXINO_L2" - depends on MACH_SUN7I - -config TARGET_A20_OLINUXINO_L - bool "A20_OLINUXINO_L" - depends on MACH_SUN7I - -config TARGET_A20_OLINUXINO_M - bool "A20_OLINUXINO_M" - depends on MACH_SUN7I - -config TARGET_AUXTEK_T004 - bool "AUXTEK_T004" - depends on MACH_SUN5I - -config TARGET_BANANAPI - bool "BANANAPI" - depends on MACH_SUN7I - -config TARGET_BANANAPRO - bool "BANANAPRO" - depends on MACH_SUN7I - -config TARGET_CUBIEBOARD2 - bool "CUBIEBOARD2" - depends on MACH_SUN7I - -config TARGET_CUBIETRUCK - bool "CUBIETRUCK" - depends on MACH_SUN7I +config DRAM_ODT_EN + int "sunxi dram odt_en value" + default 0 + ---help--- + Set the dram controller odt_en parameter. This can be used to + enable/disable the ODT feature. -config TARGET_PCDUINO3 - bool "PCDUINO3" - depends on MACH_SUN7I +config DRAM_TPR3 + hex "sunxi dram tpr3 value" + default 0 + ---help--- + Set the dram controller tpr3 parameter. This parameter configures + the delay on the command lane and also phase shifts, which are + applied for sampling incoming read data. The default value 0 + means that no phase/delay adjustments are necessary. Properly + configuring this parameter increases reliability at high DRAM + clock speeds. + +config DRAM_DQS_GATING_DELAY + hex "sunxi dram dqs_gating_delay value" + default 0 + ---help--- + Set the dram controller dqs_gating_delay parmeter. Each byte + encodes the DQS gating delay for each byte lane. The delay + granularity is 1/4 cycle. For example, the value 0x05060606 + means that the delay is 5 quarter-cycles for one lane (1.25 + cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes. + The default value 0 means autodetection. The results of hardware + autodetection are not very reliable and depend on the chip + temperature (sometimes producing different results on cold start + and warm reboot). But the accuracy of hardware autodetection + is usually good enough, unless running at really high DRAM + clocks speeds (up to 600MHz). If unsure, keep as 0. -config TARGET_MELE_M3 - bool "MELE_M3" - depends on MACH_SUN7I +choice + prompt "sunxi dram timings" + default DRAM_TIMINGS_VENDOR_MAGIC + ---help--- + Select the timings of the DDR3 chips. -config TARGET_MK802_A10S - bool "MK802_A10S" - depends on MACH_SUN5I +config DRAM_TIMINGS_VENDOR_MAGIC + bool "Magic vendor timings from Android" + ---help--- + The same DRAM timings as in the Allwinner boot0 bootloader. -config TARGET_MSI_PRIMO73 - bool "MSI Primo73 (7\" tablet)" - depends on MACH_SUN7I +config DRAM_TIMINGS_DDR3_1066F_1333H + bool "JEDEC DDR3-1333H with down binning to DDR3-1066F" + ---help--- + Use the timings of the standard JEDEC DDR3-1066F speed bin for + DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin + for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips + used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333 + or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm + that down binning to DDR3-1066F is supported (because DDR3-1066F + uses a bit faster timings than DDR3-1333H). + +config DRAM_TIMINGS_DDR3_800E_1066G_1333J + bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J" ---help--- - The MSI Primo73 is an A20 based tablet, with 1G RAM, 16G NAND, - 1024x600 TN LCD display, mono speaker, 0.3 MP front camera, 2.0 MP - rear camera, 3000 mAh battery, gt911 touchscreen, mma8452 accelerometer - and rtl8188etv usb wifi. Has "power", "volume+" and "volume-" buttons - (both volume buttons are also connected to the UBOOT_SEL pin). The - external connectors are represented by MicroSD slot, MiniHDMI, MicroUSB - OTG and 3.5mm headphone jack. More details are available at - http://linux-sunxi.org/MSI_Primo73 + Use the timings of the slowest possible JEDEC speed bin for the + selected DRAM_CLK. Depending on the DRAM_CLK value, it may be + DDR3-800E, DDR3-1066G or DDR3-1333J. -config TARGET_I12_TVBOX - bool "I12_TVBOX" - depends on MACH_SUN7I +endchoice -config TARGET_R7DONGLE - bool "R7DONGLE" - depends on MACH_SUN5I +endif -endchoice +config SYS_CONFIG_NAME + default "sun4i" if MACH_SUN4I + default "sun5i" if MACH_SUN5I + default "sun6i" if MACH_SUN6I + default "sun7i" if MACH_SUN7I + default "sun8i" if MACH_SUN8I config SYS_BOARD default "sunxi" @@ -159,6 +149,16 @@ config SPL_FEL bool "SPL/FEL mode support" depends on SPL default n + help + This enables support for Fast Early Loader (FEL) mode. This + allows U-Boot to be loaded to the board over USB by the on-chip + boot rom. U-Boot should be sent in two parts: SPL first, with + 'fel write 0x2000 u-boot-spl.bin; fel exe 0x2000' then U-Boot with + 'fel write 0x4a000000 u-boot.bin; fel exe 0x4a000000'. This option + shrinks the amount of SRAM available to SPL, so only enable it if + you need FEL. Note that enabling this option only allows FEL to be + used; it is still possible to boot U-Boot from boot media. U-Boot + SPL detects when it is being loaded using FEL. config UART0_PORT_F bool "UART0 on MicroSD breakout board" @@ -223,6 +223,14 @@ config USB0_VBUS_PIN Set the Vbus enable pin for usb0 (otg). This takes a string in the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. +config USB0_VBUS_DET + string "Vbus detect pin for usb0 (otg)" + depends on USB_MUSB_SUNXI + default "" + ---help--- + Set the Vbus detect pin for usb0 (otg). This takes a string in the + format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. + config USB1_VBUS_PIN string "Vbus enable pin for usb1 (ehci0)" default "PH6" if MACH_SUN4I || MACH_SUN7I @@ -270,6 +278,16 @@ config VIDEO_VGA_VIA_LCD LCD interface driving a VGA connector, such as found on the Olimex A13 boards. +config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH + boolean "Force sync active high for VGA via LCD controller support" + depends on VIDEO_VGA_VIA_LCD + default n + ---help--- + Say Y here if you've a board which uses opendrain drivers for the vga + hsync and vsync signals. Opendrain drivers cannot generate steep enough + positive edges for a stable video output, so on boards with opendrain + drivers the sync signals must always be active high. + config VIDEO_VGA_EXTERNAL_DAC_EN string "LCD panel power enable pin" depends on VIDEO_VGA_VIA_LCD @@ -302,6 +320,14 @@ config VIDEO_LCD_POWER Set the power enable pin for the LCD panel. This takes a string in the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. +config VIDEO_LCD_RESET + string "LCD panel reset pin" + depends on VIDEO + default "" + ---help--- + Set the reset pin for the LCD panel. This takes a string in the format + understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. + config VIDEO_LCD_BL_EN string "LCD panel backlight enable pin" depends on VIDEO @@ -326,6 +352,30 @@ config VIDEO_LCD_BL_PWM_ACTIVE_LOW ---help--- Set this if the backlight pwm output is active low. +config VIDEO_LCD_PANEL_I2C + bool "LCD panel needs to be configured via i2c" + depends on VIDEO + default m + ---help--- + Say y here if the LCD panel needs to be configured via i2c. This + will add a bitbang i2c controller using gpios to talk to the LCD. + +config VIDEO_LCD_PANEL_I2C_SDA + string "LCD panel i2c interface SDA pin" + depends on VIDEO_LCD_PANEL_I2C + default "PG12" + ---help--- + Set the SDA pin for the LCD i2c interface. This takes a string in the + format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. + +config VIDEO_LCD_PANEL_I2C_SCL + string "LCD panel i2c interface SCL pin" + depends on VIDEO_LCD_PANEL_I2C + default "PG10" + ---help--- + Set the SCL pin for the LCD i2c interface. This takes a string in the + format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H. + # Note only one of these may be selected at a time! But hidden choices are # not supported by Kconfig @@ -364,6 +414,14 @@ config VIDEO_LCD_PANEL_HITACHI_TX18D42VM ---help--- 7.85" 1024x768 Hitachi tx18d42vm LCD panel support +config VIDEO_LCD_TL059WV5C0 + bool "tl059wv5c0 LCD panel" + select VIDEO_LCD_PANEL_I2C + select VIDEO_LCD_IF_PARALLEL + ---help--- + 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and + Aigo M60/M608/M606 tablets. + endchoice @@ -383,4 +441,10 @@ config USB_KEYBOARD Say Y here to add support for using a USB keyboard (typically used in combination with a graphical console). +config GMAC_TX_DELAY + int "GMAC Transmit Clock Delay Chain" + default 0 + ---help--- + Set the GMAC Transmit Clock Delay Chain value. + endif diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index 743e7f5351..9a287d3c30 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -34,16 +34,6 @@ F: configs/qt840a_defconfig F: include/configs/sun8i.h F: configs/Ippo_q8h_v1_2_defconfig -CUBIEBOARD2 BOARD -M: Ian Campbell <ijc@hellion.org.uk> -M: Hans de Goede <hdegoede@redhat.com> -S: Maintained -F: include/configs/sun7i.h -F: configs/Cubieboard2_defconfig -F: configs/Cubieboard2_FEL_defconfig -F: configs/Cubietruck_defconfig -F: configs/Cubietruck_FEL_defconfig - A20-OLINUXINO-LIME BOARD M: FUKAUMI Naoki <naobsd@gmail.com> S: Maintained @@ -56,41 +46,55 @@ S: Maintained F: board/sunxi/dram_a20_olinuxino_l2.c F: configs/A20-OLinuXino-Lime2_defconfig +AMPE A76 BOARD +M: Paul Kocialkowski <contact@paulk.fr> +S: Maintained +F: configs/Ampe_A76_defconfig + COLOMBUS BOARD M: Maxime Ripard <maxime.ripard@free-electrons.com> S: Maintained F: configs/Colombus_defconfig +CUBIEBOARD2 BOARD +M: Ian Campbell <ijc@hellion.org.uk> +M: Hans de Goede <hdegoede@redhat.com> +S: Maintained +F: include/configs/sun7i.h +F: configs/Cubieboard2_defconfig +F: configs/Cubietruck_defconfig + GEMEI-G9 TABLET -M: Priit Laes <plaes@plaes.org> -S: Maintained -F: configs/sunxi_Gemei_G9_defconfig +M: Priit Laes <plaes@plaes.org> +S: Maintained +F: configs/sunxi_Gemei_G9_defconfig -HUMMINIGBIRD-A31 BOARD +HUMMINGBIRD-A31 BOARD M: Chen-Yu Tsai <wens@csie.org> S: Maintained F: configs/Hummingbird_A31_defconfig +INET-86VS BOARD +M: Michal Suchanek <hramrach@gmail.com> +S: Maintained +F: board/sunxi/dram_inet_86vs.c +F: configs/Inet_86VS_defconfig + IPPO-Q8H-V5 BOARD M: Chen-Yu Tsai <wens@csie.org> S: Maintained F: configs/Ippo_q8h_v5_defconfig -MSI-PRIMO73 BOARD -M: Siarhei Siamashka <siarhei.siamashka@gmail.com> -S: Maintained -F: configs/MSI_Primo73_defconfig - -MSI-PRIMO81 BOARD -M: Siarhei Siamashka <siarhei.siamashka@gmail.com> -S: Maintained -F: configs/MSI_Primo81_defconfig - LINKSPRITE-PCDUINO BOARD M: Zoltan Herpai <wigyori@uid0.hu> S: Maintained F: configs/Linksprite_pcDuino_defconfig +LINKSPRITE-PCDUINO3-NANO BOARD +M: Adam Sampson <ats@offog.org> +S: Maintained +F: configs/Linksprite_pcDuino3_Nano_defconfig + MARSBOARD-A10 BOARD M: Aleksei Mamlin <mamlinav@gmail.com> S: Maintained @@ -100,3 +104,18 @@ MELE M5 BOARD M: Ian Campbell <ijc@hellion.org.uk> S: Maintained F: configs/Mele_M5_defconfig + +MSI-PRIMO73 BOARD +M: Siarhei Siamashka <siarhei.siamashka@gmail.com> +S: Maintained +F: configs/MSI_Primo73_defconfig + +MSI-PRIMO81 BOARD +M: Siarhei Siamashka <siarhei.siamashka@gmail.com> +S: Maintained +F: configs/MSI_Primo81_defconfig + +TZX-Q8-713B7 BOARD +M: Paul Kocialkowski <contact@paulk.fr> +S: Maintained +F: configs/TZX-Q8-713B7_defconfig diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile index 71edb83c5d..43766e0ef4 100644 --- a/board/sunxi/Makefile +++ b/board/sunxi/Makefile @@ -12,11 +12,5 @@ obj-y += board.o obj-$(CONFIG_SUNXI_GMAC) += gmac.o obj-$(CONFIG_SUNXI_AHCI) += ahci.o obj-$(CONFIG_MACH_SUN4I) += dram_sun4i_auto.o +obj-$(CONFIG_MACH_SUN5I) += dram_sun5i_auto.o obj-$(CONFIG_MACH_SUN7I) += dram_sun5i_auto.o -obj-$(CONFIG_TARGET_A10S_OLINUXINO_M) += dram_a10s_olinuxino_m.o -obj-$(CONFIG_TARGET_A13_OLINUXINO) += dram_a13_olinuxino.o -obj-$(CONFIG_TARGET_A13_OLINUXINOM) += dram_a13_oli_micro.o -# This is not a typo, uses the same mem settings as the a10s-olinuxino-m -obj-$(CONFIG_TARGET_AUXTEK_T004) += dram_a10s_olinuxino_m.o -obj-$(CONFIG_TARGET_MK802_A10S) += dram_sun5i_auto.o -obj-$(CONFIG_TARGET_R7DONGLE) += dram_r7dongle.o diff --git a/board/sunxi/board.c b/board/sunxi/board.c index b70e00ce6b..e1891d198e 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -33,6 +33,12 @@ #include <linux/usb/musb.h> #include <net.h> +#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) +/* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */ +int soft_i2c_gpio_sda; +int soft_i2c_gpio_scl; +#endif + DECLARE_GLOBAL_DATA_PTR; /* add board specific code here */ @@ -152,6 +158,10 @@ void i2c_init_board(void) sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUNXI_GPB0_TWI0); sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUNXI_GPB0_TWI0); clock_twi_onoff(0, 1); +#if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD) + soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA); + soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL); +#endif } #ifdef CONFIG_SPL_BUILD diff --git a/board/sunxi/dram_a10s_olinuxino_m.c b/board/sunxi/dram_a10s_olinuxino_m.c deleted file mode 100644 index 8900539e7f..0000000000 --- a/board/sunxi/dram_a10s_olinuxino_m.c +++ /dev/null @@ -1,31 +0,0 @@ -/* this file is generated, don't edit it yourself */ - -#include <common.h> -#include <asm/arch/dram.h> - -static struct dram_para dram_para = { - .clock = 432, - .type = 3, - .rank_num = 1, - .density = 4096, - .io_width = 16, - .bus_width = 16, - .cas = 9, - .zq = 123, - .odt_en = 0, - .size = 512, - .tpr0 = 0x42d899b7, - .tpr1 = 0xa090, - .tpr2 = 0x22a00, - .tpr3 = 0, - .tpr4 = 0, - .tpr5 = 0, - .emr1 = 0x4, - .emr2 = 0x10, - .emr3 = 0, -}; - -unsigned long sunxi_dram_init(void) -{ - return dramc_init(&dram_para); -} diff --git a/board/sunxi/dram_a13_oli_micro.c b/board/sunxi/dram_a13_oli_micro.c deleted file mode 100644 index 8154ea2ca9..0000000000 --- a/board/sunxi/dram_a13_oli_micro.c +++ /dev/null @@ -1,32 +0,0 @@ -/* this file is generated, don't edit it yourself */ - -#include <common.h> -#include <asm/arch/dram.h> - -static struct dram_para dram_para = { - .clock = 408, - .type = 3, - .rank_num = 1, - .density = 2048, - .io_width = 16, - .bus_width = 16, - .cas = 9, - .zq = 123, - .odt_en = 0, - .size = 256, - .tpr0 = 0x42d899b7, - .tpr1 = 0xa090, - .tpr2 = 0x22a00, - .tpr3 = 0, - .tpr4 = 0, - .tpr5 = 0, - .emr1 = 0, - .emr2 = 0x10, - .emr3 = 0, - -}; - -unsigned long sunxi_dram_init(void) -{ - return dramc_init(&dram_para); -} diff --git a/board/sunxi/dram_a13_olinuxino.c b/board/sunxi/dram_a13_olinuxino.c deleted file mode 100644 index ca96260250..0000000000 --- a/board/sunxi/dram_a13_olinuxino.c +++ /dev/null @@ -1,31 +0,0 @@ -/* this file is generated, don't edit it yourself */ - -#include <common.h> -#include <asm/arch/dram.h> - -static struct dram_para dram_para = { - .clock = 408, - .type = 3, - .rank_num = 1, - .density = 2048, - .io_width = 8, - .bus_width = 16, - .cas = 9, - .zq = 123, - .odt_en = 0, - .size = 512, - .tpr0 = 0x42d899b7, - .tpr1 = 0xa090, - .tpr2 = 0x22a00, - .tpr3 = 0, - .tpr4 = 0, - .tpr5 = 0, - .emr1 = 0, - .emr2 = 0x10, - .emr3 = 0, -}; - -unsigned long sunxi_dram_init(void) -{ - return dramc_init(&dram_para); -} diff --git a/board/sunxi/dram_bananapi.c b/board/sunxi/dram_bananapi.c deleted file mode 100644 index 0ed7943043..0000000000 --- a/board/sunxi/dram_bananapi.c +++ /dev/null @@ -1,31 +0,0 @@ -/* this file is generated, don't edit it yourself */ - -#include <common.h> -#include <asm/arch/dram.h> - -static struct dram_para dram_para = { - .clock = 432, - .type = 3, - .rank_num = 1, - .density = 4096, - .io_width = 16, - .bus_width = 32, - .cas = 9, - .zq = 0x7f, - .odt_en = 0, - .size = 1024, - .tpr0 = 0x42d899b7, - .tpr1 = 0xa090, - .tpr2 = 0x22a00, - .tpr3 = 0x0, - .tpr4 = 0x1, - .tpr5 = 0x0, - .emr1 = 0x4, - .emr2 = 0x10, - .emr3 = 0x0, -}; - -unsigned long sunxi_dram_init(void) -{ - return dramc_init(&dram_para); -} diff --git a/board/sunxi/dram_r7dongle.c b/board/sunxi/dram_r7dongle.c deleted file mode 100644 index 59343cb2a5..0000000000 --- a/board/sunxi/dram_r7dongle.c +++ /dev/null @@ -1,31 +0,0 @@ -/* this file is generated, don't edit it yourself */ - -#include <common.h> -#include <asm/arch/dram.h> - -static struct dram_para dram_para = { - .clock = 384, - .type = 3, - .rank_num = 1, - .density = 2048, - .io_width = 8, - .bus_width = 32, - .cas = 9, - .zq = 123, - .odt_en = 0, - .size = 1024, - .tpr0 = 0x42d899b7, - .tpr1 = 0xa090, - .tpr2 = 0x22a00, - .tpr3 = 0, - .tpr4 = 0, - .tpr5 = 0, - .emr1 = 0x04, - .emr2 = 0x10, - .emr3 = 0, -}; - -unsigned long sunxi_dram_init(void) -{ - return dramc_init(&dram_para); -} diff --git a/board/sunxi/dram_sun4i_auto.c b/board/sunxi/dram_sun4i_auto.c index 826bacf94a..09e0c9ae2e 100644 --- a/board/sunxi/dram_sun4i_auto.c +++ b/board/sunxi/dram_sun4i_auto.c @@ -8,19 +8,25 @@ static struct dram_para dram_para = { .density = 0, .io_width = 0, .bus_width = 0, - .cas = 6, .zq = CONFIG_DRAM_ZQ, - .odt_en = 0, + .odt_en = CONFIG_DRAM_ODT_EN, .size = 0, +#ifdef CONFIG_DRAM_TIMINGS_VENDOR_MAGIC + .cas = 6, .tpr0 = 0x30926692, .tpr1 = 0x1090, .tpr2 = 0x1a0c8, - .tpr3 = 0, + .emr2 = 0, +#else +# include "dram_timings_sun4i.h" + .active_windowing = 1, +#endif + .tpr3 = CONFIG_DRAM_TPR3, .tpr4 = 0, .tpr5 = 0, .emr1 = CONFIG_DRAM_EMR1, - .emr2 = 0, .emr3 = 0, + .dqs_gating_delay = CONFIG_DRAM_DQS_GATING_DELAY, }; unsigned long sunxi_dram_init(void) diff --git a/board/sunxi/dram_sun5i_auto.c b/board/sunxi/dram_sun5i_auto.c index e86b08e67b..e52d54c32e 100644 --- a/board/sunxi/dram_sun5i_auto.c +++ b/board/sunxi/dram_sun5i_auto.c @@ -5,24 +5,31 @@ static struct dram_para dram_para = { .clock = CONFIG_DRAM_CLK, + .mbus_clock = CONFIG_DRAM_MBUS_CLK, .type = 3, .rank_num = 1, .density = 0, .io_width = 0, .bus_width = 0, - .cas = 9, .zq = CONFIG_DRAM_ZQ, - .odt_en = 0, + .odt_en = CONFIG_DRAM_ODT_EN, .size = 0, +#ifdef CONFIG_DRAM_TIMINGS_VENDOR_MAGIC + .cas = 9, .tpr0 = 0x42d899b7, .tpr1 = 0xa090, .tpr2 = 0x22a00, + .emr2 = 0x10, +#else +# include "dram_timings_sun4i.h" + .active_windowing = 1, +#endif .tpr3 = 0, .tpr4 = 0, .tpr5 = 0, .emr1 = CONFIG_DRAM_EMR1, - .emr2 = 0x10, .emr3 = 0, + .dqs_gating_delay = CONFIG_DRAM_DQS_GATING_DELAY, }; unsigned long sunxi_dram_init(void) diff --git a/board/sunxi/dram_timings_sun4i.h b/board/sunxi/dram_timings_sun4i.h new file mode 100644 index 0000000000..29b934da63 --- /dev/null +++ b/board/sunxi/dram_timings_sun4i.h @@ -0,0 +1,205 @@ +/* This file is automatically generated, do not edit */ + +#if defined(CONFIG_DRAM_TIMINGS_DDR3_1066F_1333H) +# if CONFIG_DRAM_CLK <= 360 /* DDR3-1066F @360MHz, timings: 6-5-5-14 */ + .cas = 6, + .tpr0 = 0x268e5590, + .tpr1 = 0xa090, + .tpr2 = 0x22a00, + .emr2 = 0x0, +# elif CONFIG_DRAM_CLK <= 384 /* DDR3-1066F @384MHz, timings: 6-6-6-15 */ + .cas = 6, + .tpr0 = 0x288f6690, + .tpr1 = 0xa0a0, + .tpr2 = 0x22a00, + .emr2 = 0x0, +# elif CONFIG_DRAM_CLK <= 396 /* DDR3-1066F @396MHz, timings: 6-6-6-15 */ + .cas = 6, + .tpr0 = 0x2a8f6690, + .tpr1 = 0xa0a0, + .tpr2 = 0x22a00, + .emr2 = 0x0, +# elif CONFIG_DRAM_CLK <= 408 /* DDR3-1066F @408MHz, timings: 7-6-6-16 */ + .cas = 7, + .tpr0 = 0x2ab06690, + .tpr1 = 0xa0a8, + .tpr2 = 0x22a00, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 432 /* DDR3-1066F @432MHz, timings: 7-6-6-17 */ + .cas = 7, + .tpr0 = 0x2cb16690, + .tpr1 = 0xa0b0, + .tpr2 = 0x22e00, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 456 /* DDR3-1066F @456MHz, timings: 7-6-6-18 */ + .cas = 7, + .tpr0 = 0x30b26690, + .tpr1 = 0xa0b8, + .tpr2 = 0x22e00, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 468 /* DDR3-1066F @468MHz, timings: 7-7-7-18 */ + .cas = 7, + .tpr0 = 0x30b27790, + .tpr1 = 0xa0c0, + .tpr2 = 0x23200, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 480 /* DDR3-1066F @480MHz, timings: 7-7-7-18 */ + .cas = 7, + .tpr0 = 0x32b27790, + .tpr1 = 0xa0c0, + .tpr2 = 0x23200, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 504 /* DDR3-1066F @504MHz, timings: 7-7-7-19 */ + .cas = 7, + .tpr0 = 0x34d37790, + .tpr1 = 0xa0d0, + .tpr2 = 0x23600, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 528 /* DDR3-1066F @528MHz, timings: 7-7-7-20 */ + .cas = 7, + .tpr0 = 0x36d47790, + .tpr1 = 0xa0d8, + .tpr2 = 0x23600, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 540 /* DDR3-1333H @540MHz, timings: 9-8-8-20 */ + .cas = 9, + .tpr0 = 0x36b488b4, + .tpr1 = 0xa0c8, + .tpr2 = 0x2b600, + .emr2 = 0x10, +# elif CONFIG_DRAM_CLK <= 552 /* DDR3-1333H @552MHz, timings: 9-8-8-20 */ + .cas = 9, + .tpr0 = 0x38b488b4, + .tpr1 = 0xa0c8, + .tpr2 = 0x2ba00, + .emr2 = 0x10, +# elif CONFIG_DRAM_CLK <= 576 /* DDR3-1333H @576MHz, timings: 9-8-8-21 */ + .cas = 9, + .tpr0 = 0x3ab588b4, + .tpr1 = 0xa0d0, + .tpr2 = 0x2ba00, + .emr2 = 0x10, +# elif CONFIG_DRAM_CLK <= 600 /* DDR3-1333H @600MHz, timings: 9-9-9-22 */ + .cas = 9, + .tpr0 = 0x3cb699b4, + .tpr1 = 0xa0d8, + .tpr2 = 0x2be00, + .emr2 = 0x10, +# elif CONFIG_DRAM_CLK <= 624 /* DDR3-1333H @624MHz, timings: 9-9-9-23 */ + .cas = 9, + .tpr0 = 0x3eb799b4, + .tpr1 = 0xa0e8, + .tpr2 = 0x2be00, + .emr2 = 0x10, +# elif CONFIG_DRAM_CLK <= 648 /* DDR3-1333H @648MHz, timings: 9-9-9-24 */ + .cas = 9, + .tpr0 = 0x42b899b4, + .tpr1 = 0xa0f0, + .tpr2 = 0x2c200, + .emr2 = 0x10, +# else +# error CONFIG_DRAM_CLK is set too high +# endif +#elif defined(CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J) +# if CONFIG_DRAM_CLK <= 360 /* DDR3-800E @360MHz, timings: 6-6-6-14 */ + .cas = 6, + .tpr0 = 0x268e6690, + .tpr1 = 0xa090, + .tpr2 = 0x22a00, + .emr2 = 0x0, +# elif CONFIG_DRAM_CLK <= 384 /* DDR3-800E @384MHz, timings: 6-6-6-15 */ + .cas = 6, + .tpr0 = 0x2a8f6690, + .tpr1 = 0xa0a0, + .tpr2 = 0x22a00, + .emr2 = 0x0, +# elif CONFIG_DRAM_CLK <= 396 /* DDR3-800E @396MHz, timings: 6-6-6-15 */ + .cas = 6, + .tpr0 = 0x2a8f6690, + .tpr1 = 0xa0a0, + .tpr2 = 0x22a00, + .emr2 = 0x0, +# elif CONFIG_DRAM_CLK <= 408 /* DDR3-1066G @408MHz, timings: 8-7-7-16 */ + .cas = 8, + .tpr0 = 0x2cb07790, + .tpr1 = 0xa0a8, + .tpr2 = 0x22a00, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 432 /* DDR3-1066G @432MHz, timings: 8-7-7-17 */ + .cas = 8, + .tpr0 = 0x2eb17790, + .tpr1 = 0xa0b0, + .tpr2 = 0x22e00, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 456 /* DDR3-1066G @456MHz, timings: 8-7-7-18 */ + .cas = 8, + .tpr0 = 0x30b27790, + .tpr1 = 0xa0b8, + .tpr2 = 0x22e00, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 468 /* DDR3-1066G @468MHz, timings: 8-8-8-18 */ + .cas = 8, + .tpr0 = 0x32b28890, + .tpr1 = 0xa0c0, + .tpr2 = 0x23200, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 480 /* DDR3-1066G @480MHz, timings: 8-8-8-18 */ + .cas = 8, + .tpr0 = 0x34b28890, + .tpr1 = 0xa0c0, + .tpr2 = 0x23200, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 504 /* DDR3-1066G @504MHz, timings: 8-8-8-19 */ + .cas = 8, + .tpr0 = 0x36d38890, + .tpr1 = 0xa0d0, + .tpr2 = 0x23600, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 528 /* DDR3-1066G @528MHz, timings: 8-8-8-20 */ + .cas = 8, + .tpr0 = 0x38d48890, + .tpr1 = 0xa0d8, + .tpr2 = 0x23600, + .emr2 = 0x8, +# elif CONFIG_DRAM_CLK <= 540 /* DDR3-1333J @540MHz, timings: 10-9-9-20 */ + .cas = 10, + .tpr0 = 0x38b499b4, + .tpr1 = 0xa0c8, + .tpr2 = 0x2b600, + .emr2 = 0x10, +# elif CONFIG_DRAM_CLK <= 552 /* DDR3-1333J @552MHz, timings: 10-9-9-20 */ + .cas = 10, + .tpr0 = 0x3ab499b4, + .tpr1 = 0xa0c8, + .tpr2 = 0x2ba00, + .emr2 = 0x10, +# elif CONFIG_DRAM_CLK <= 576 /* DDR3-1333J @576MHz, timings: 10-9-9-21 */ + .cas = 10, + .tpr0 = 0x3cb599b4, + .tpr1 = 0xa0d0, + .tpr2 = 0x2ba00, + .emr2 = 0x10, +# elif CONFIG_DRAM_CLK <= 600 /* DDR3-1333J @600MHz, timings: 10-9-9-22 */ + .cas = 10, + .tpr0 = 0x3eb699b4, + .tpr1 = 0xa0d8, + .tpr2 = 0x2be00, + .emr2 = 0x10, +# elif CONFIG_DRAM_CLK <= 624 /* DDR3-1333J @624MHz, timings: 10-10-10-23 */ + .cas = 10, + .tpr0 = 0x40b7aab4, + .tpr1 = 0xa0e8, + .tpr2 = 0x2be00, + .emr2 = 0x10, +# elif CONFIG_DRAM_CLK <= 648 /* DDR3-1333J @648MHz, timings: 10-10-10-24 */ + .cas = 10, + .tpr0 = 0x44b8aab4, + .tpr1 = 0xa0f0, + .tpr2 = 0x2c200, + .emr2 = 0x10, +# else +# error CONFIG_DRAM_CLK is set too high +# endif +#else +# error CONFIG_DRAM_TIMINGS_* is not defined +#endif diff --git a/board/sunxi/gmac.c b/board/sunxi/gmac.c index 4e4615e12f..8849132627 100644 --- a/board/sunxi/gmac.c +++ b/board/sunxi/gmac.c @@ -24,20 +24,13 @@ int sunxi_gmac_initialize(bd_t *bis) #ifdef CONFIG_RGMII setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII | CCM_GMAC_CTRL_GPIT_RGMII); + setbits_le32(&ccm->gmac_clk_cfg, + CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY)); #else setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII | CCM_GMAC_CTRL_GPIT_MII); #endif - /* - * In order for the gmac nic to work reliable on the Bananapi, we - * need to set bits 10-12 GTXDC "GMAC Transmit Clock Delay Chain" - * of the GMAC clk register to 3. - */ -#if defined CONFIG_TARGET_BANANAPI || defined CONFIG_TARGET_BANANAPRO - setbits_le32(&ccm->gmac_clk_cfg, 0x3 << 10); -#endif - #ifndef CONFIG_MACH_SUN6I /* Configure pin mux settings for GMAC */ for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) { diff --git a/board/synopsys/Kconfig b/board/synopsys/Kconfig index f614f88cc6..8ab48cd91c 100644 --- a/board/synopsys/Kconfig +++ b/board/synopsys/Kconfig @@ -7,13 +7,3 @@ config SYS_CONFIG_NAME default "arcangel4" endif - -if TARGET_ARCANGEL4_BE - -config SYS_VENDOR - default "synopsys" - -config SYS_CONFIG_NAME - default "arcangel4-be" - -endif diff --git a/board/synopsys/MAINTAINERS b/board/synopsys/MAINTAINERS index 720edd8893..43114cea5e 100644 --- a/board/synopsys/MAINTAINERS +++ b/board/synopsys/MAINTAINERS @@ -3,5 +3,4 @@ M: Alexey Brodkin <abrodkin@synopsys.com> S: Maintained F: include/configs/arcangel4.h F: configs/arcangel4_defconfig -F: include/configs/arcangel4-be.h F: configs/arcangel4-be_defconfig diff --git a/board/taskit/stamp9g20/Kconfig b/board/taskit/stamp9g20/Kconfig index 3139f9af86..1121dacfc7 100644 --- a/board/taskit/stamp9g20/Kconfig +++ b/board/taskit/stamp9g20/Kconfig @@ -6,9 +6,6 @@ config SYS_BOARD config SYS_VENDOR default "taskit" -config SYS_SOC - default "at91" - config SYS_CONFIG_NAME default "stamp9g20" diff --git a/board/ti/am335x/Kconfig b/board/ti/am335x/Kconfig index 1ddbb2c67c..a20e0c1ab9 100644 --- a/board/ti/am335x/Kconfig +++ b/board/ti/am335x/Kconfig @@ -37,4 +37,20 @@ config NOR_BOOT booted via NOR. In this case we will enable certain pinmux early as the ROM only partially sets up pinmux. We also default to using NOR for environment. + +config DM + default y if !SPL_BUILD + +config DM_GPIO + default y if DM && !SPL_BUILD + +config DM_SERIAL + default y if DM && !SPL_BUILD + +config SYS_MALLOC_F + default y if DM && !SPL_BUILD + +config SYS_MALLOC_F_LEN + default 0x400 if DM && !SPL_BUILD + endif diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c index db96e347e7..3a7e04d542 100644 --- a/board/ti/beagle_x15/board.c +++ b/board/ti/beagle_x15/board.c @@ -47,7 +47,8 @@ static const struct emif_regs beagle_x15_emif1_ddr3_532mhz_emif_regs = { .sdram_config_init = 0x61851b32, .sdram_config = 0x61851b32, .sdram_config2 = 0x00000000, - .ref_ctrl = 0x00001035, + .ref_ctrl = 0x000040F1, + .ref_ctrl_final = 0x00001035, .sdram_tim1 = 0xceef266b, .sdram_tim2 = 0x328f7fda, .sdram_tim3 = 0x027f88a8, @@ -103,7 +104,8 @@ static const struct emif_regs beagle_x15_emif2_ddr3_532mhz_emif_regs = { .sdram_config_init = 0x61851b32, .sdram_config = 0x61851b32, .sdram_config2 = 0x00000000, - .ref_ctrl = 0x00001035, + .ref_ctrl = 0x000040F1, + .ref_ctrl_final = 0x00001035, .sdram_tim1 = 0xceef266b, .sdram_tim2 = 0x328f7fda, .sdram_tim3 = 0x027f88a8, diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c index 04ec675103..8892a2843d 100644 --- a/board/ti/ks2_evm/board.c +++ b/board/ti/ks2_evm/board.c @@ -35,12 +35,14 @@ static struct aemif_config aemif_configs[] = { int dram_init(void) { - ddr3_init(); + u32 ddr3_size; + + ddr3_size = ddr3_init(); gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, CONFIG_MAX_RAM_BANK_SIZE); aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs); - ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE); + ddr3_init_ecc(KS2_DDR3A_EMIF_CTRL_BASE, ddr3_size); return 0; } diff --git a/board/ti/ks2_evm/ddr3_k2e.c b/board/ti/ks2_evm/ddr3_k2e.c index 40fd96607d..35ffb42056 100644 --- a/board/ti/ks2_evm/ddr3_k2e.c +++ b/board/ti/ks2_evm/ddr3_k2e.c @@ -11,11 +11,11 @@ #include "ddr3_cfg.h" #include <asm/arch/ddr3.h> -static int ddr3_size; static struct pll_init_data ddr3_400 = DDR3_PLL_400; -void ddr3_init(void) +u32 ddr3_init(void) { + u32 ddr3_size; char dimm_name[32]; if (~(readl(KS2_PLL_CNTRL_BASE + KS2_RSTCTRL_RSTYPE) & 0x1)) @@ -43,13 +43,11 @@ void ddr3_init(void) printf("DRAM: 4 GiB\n"); ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_4g); ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_4g); + } else { + printf("Unknown SO-DIMM. Cannot configure DDR3\n"); + while (1) + ; } -} -/** - * ddr3_get_size - return ddr3 size in GiB - */ -int ddr3_get_size(void) -{ return ddr3_size; } diff --git a/board/ti/ks2_evm/ddr3_k2hk.c b/board/ti/ks2_evm/ddr3_k2hk.c index a1c3d05f8e..b36eb27bfa 100644 --- a/board/ti/ks2_evm/ddr3_k2hk.c +++ b/board/ti/ks2_evm/ddr3_k2hk.c @@ -12,14 +12,13 @@ #include <asm/arch/ddr3.h> #include <asm/arch/hardware.h> -static int ddr3_size; - struct pll_init_data ddr3a_333 = DDR3_PLL_333(A); struct pll_init_data ddr3a_400 = DDR3_PLL_400(A); -void ddr3_init(void) +u32 ddr3_init(void) { char dimm_name[32]; + u32 ddr3_size; ddr3_get_dimm_params(dimm_name); @@ -93,12 +92,6 @@ void ddr3_init(void) /* Apply the workaround for PG 1.0 and 1.1 Silicons */ if (cpu_revision() <= 1) ddr3_err_reset_workaround(); -} -/** - * ddr3_get_size - return ddr3 size in GiB - */ -int ddr3_get_size(void) -{ return ddr3_size; } diff --git a/board/ti/ks2_evm/ddr3_k2l.c b/board/ti/ks2_evm/ddr3_k2l.c index 15a14f2aaf..00fc1943f5 100644 --- a/board/ti/ks2_evm/ddr3_k2l.c +++ b/board/ti/ks2_evm/ddr3_k2l.c @@ -11,28 +11,20 @@ #include "ddr3_cfg.h" #include <asm/arch/ddr3.h> -static int ddr3_size; static struct pll_init_data ddr3_400 = DDR3_PLL_400; -void ddr3_init(void) +u32 ddr3_init(void) { init_pll(&ddr3_400); /* No SO-DIMM, 2GB discreet DDR */ printf("DRAM: 2 GiB\n"); - ddr3_size = 2; /* Reset DDR3 PHY after PLL enabled */ ddr3_reset_ddrphy(); ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_2g); ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_2g); -} -/** - * ddr3_get_size - return ddr3 size in GiB - */ -int ddr3_get_size(void) -{ - return ddr3_size; + return 2; } diff --git a/board/toradex/apalis_t30/apalis_t30.c b/board/toradex/apalis_t30/apalis_t30.c index 5d2c024e89..624421496a 100644 --- a/board/toradex/apalis_t30/apalis_t30.c +++ b/board/toradex/apalis_t30/apalis_t30.c @@ -42,7 +42,7 @@ int tegra_pcie_board_init(void) u8 addr, data[1]; int err; - err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, &dev); + err = i2c_get_chip_for_busnum(0, PMU_I2C_ADDRESS, 1, &dev); if (err) { debug("%s: Cannot find PMIC I2C chip\n", __func__); return err; @@ -51,7 +51,7 @@ int tegra_pcie_board_init(void) data[0] = 0x27; addr = 0x25; - err = i2c_write(dev, addr, data, 1); + err = dm_i2c_write(dev, addr, data, 1); if (err) { debug("failed to set VDD supply\n"); return err; @@ -61,7 +61,7 @@ int tegra_pcie_board_init(void) data[0] = 0x0D; addr = 0x24; - err = i2c_write(dev, addr, data, 1); + err = dm_i2c_write(dev, addr, data, 1); if (err) { debug("failed to enable VDD supply\n"); return err; @@ -71,7 +71,7 @@ int tegra_pcie_board_init(void) data[0] = 0x0D; addr = 0x35; - err = i2c_write(dev, addr, data, 1); + err = dm_i2c_write(dev, addr, data, 1); if (err) { debug("failed to set AVDD supply\n"); return err; diff --git a/board/xilinx/microblaze-generic/microblaze-generic.c b/board/xilinx/microblaze-generic/microblaze-generic.c index 42a8d0c400..3110405a1b 100644 --- a/board/xilinx/microblaze-generic/microblaze-generic.c +++ b/board/xilinx/microblaze-generic/microblaze-generic.c @@ -11,16 +11,62 @@ #include <common.h> #include <config.h> +#include <fdtdec.h> #include <netdev.h> #include <asm/processor.h> #include <asm/microblaze_intc.h> #include <asm/asm.h> #include <asm/gpio.h> +DECLARE_GLOBAL_DATA_PTR; + #ifdef CONFIG_XILINX_GPIO static int reset_pin = -1; #endif +#ifdef CONFIG_OF_CONTROL +ulong ram_base; + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = ram_base; + gd->bd->bi_dram[0].size = get_effective_memsize(); +} + +int dram_init(void) +{ + int node; + fdt_addr_t addr; + fdt_size_t size; + const void *blob = gd->fdt_blob; + + node = fdt_node_offset_by_prop_value(blob, -1, "device_type", + "memory", 7); + if (node == -FDT_ERR_NOTFOUND) { + debug("DRAM: Can't get memory node\n"); + return 1; + } + addr = fdtdec_get_addr_size(blob, node, "reg", &size); + if (addr == FDT_ADDR_T_NONE || size == 0) { + debug("DRAM: Can't get base address or size\n"); + return 1; + } + ram_base = addr; + + gd->ram_top = addr; /* In setup_dest_addr() is done +ram_size */ + gd->ram_size = size; + + return 0; +}; +#else +int dram_init(void) +{ + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + + return 0; +} +#endif + int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { #ifdef CONFIG_XILINX_GPIO |
