diff options
Diffstat (limited to 'board')
61 files changed, 2299 insertions, 1073 deletions
diff --git a/board/BuS/eb_cpu5282/Makefile b/board/BuS/eb_cpu5282/Makefile index 0f14699c5e..ac860c1348 100644 --- a/board/BuS/eb_cpu5282/Makefile +++ b/board/BuS/eb_cpu5282/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS = $(BOARD).o cfm_flash.o flash.o +COBJS = $(BOARD).o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/BuS/eb_cpu5282/cfm_flash.c b/board/BuS/eb_cpu5282/cfm_flash.c deleted file mode 100644 index fe03b17581..0000000000 --- a/board/BuS/eb_cpu5282/cfm_flash.c +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Basic Flash Driver for Freescale MCF 5281/5282 internal FLASH - * - * (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/m5282.h> -#include "cfm_flash.h" - -#if defined(CONFIG_M5281) || defined(CONFIG_M5282) - -#if (CONFIG_SYS_CLK>20000000) - #define CFM_CLK (((long) CONFIG_SYS_CLK / (400000 * 8) + 1) | 0x40) -#else - #define CFM_CLK ((long) CONFIG_SYS_CLK / 400000 + 1) -#endif - -#define cmf_backdoor_address(addr) (((addr) & 0x0007FFFF) | 0x04000000 | \ - (CONFIG_SYS_MBAR & 0xC0000000)) - -void cfm_flash_print_info (flash_info_t * info) -{ - printf ("Freescale: "); - switch (info->flash_id & FLASH_TYPEMASK) { - case FREESCALE_ID_MCF5281 & FLASH_TYPEMASK: - printf ("MCF5281 internal FLASH\n"); - break; - case FREESCALE_ID_MCF5282 & FLASH_TYPEMASK: - printf ("MCF5282 internal FLASH\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } -} - -void cfm_flash_init (flash_info_t * info) -{ - int sector; - ulong protection; - MCFCFM_MCR = 0; - MCFCFM_CLKD = CFM_CLK; - debug ("CFM Clock divider: %ld (%d Hz @ %ld Hz)\n",CFM_CLK,\ - CONFIG_SYS_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\ - CONFIG_SYS_CLK); - MCFCFM_SACC = 0; - MCFCFM_DACC = 0; - - if (MCFCFM_SEC & MCFCFM_SEC_KEYEN) - puts("CFM backdoor access is enabled\n"); - if (MCFCFM_SEC & MCFCFM_SEC_SECSTAT) - puts("CFM securety is enabled\n"); - - #ifdef CONFIG_M5281 - info->flash_id = (FREESCALE_MANUFACT & FLASH_VENDMASK) | - (FREESCALE_ID_MCF5281 & FLASH_TYPEMASK); - info->size = 256*1024; - info->sector_count = 16; - #else - info->flash_id = (FREESCALE_MANUFACT & FLASH_VENDMASK) | - (FREESCALE_ID_MCF5282 & FLASH_TYPEMASK); - info->size = 512*1024; - info->sector_count = 32; - #endif - protection = MCFCFM_PROT; - for (sector = 0; sector < info->sector_count; sector++) - { - if (sector == 0) - { - info->start[sector] = CONFIG_SYS_INT_FLASH_BASE; - } - else - { - info->start[sector] = info->start[sector-1] + 0x04000; - } - info->protect[sector] = protection & 1; - protection >>= 1; - } -} - -int cfm_flash_readycheck(int checkblank) -{ - int rc; - unsigned char state; - - rc = ERR_OK; - while (!(MCFCFM_USTAT & MCFCFM_USTAT_CCIF)); - state = MCFCFM_USTAT; - if (state & MCFCFM_USTAT_ACCERR) - { - debug ("%s(): CFM access error",__FUNCTION__); - rc = ERR_PROG_ERROR; - } - if (state & MCFCFM_USTAT_PVIOL) - { - debug ("%s(): CFM protection violation",__FUNCTION__); - rc = ERR_PROTECTED; - } - if (checkblank) - { - if (!(state & MCFCFM_USTAT_BLANK)) - { - debug ("%s(): CFM erras error",__FUNCTION__); - rc = ERR_NOT_ERASED; - } - } - MCFCFM_USTAT = state & 0x34; /* reset state */ - return rc; -} - -/* Erase 16KiB = 8 2KiB pages */ - -int cfm_flash_erase_sector (flash_info_t * info, int sector) -{ - ulong address; - int page; - int rc; - rc= ERR_OK; - address = cmf_backdoor_address(info->start[sector]); - for (page=0; (page<8) && (rc==ERR_OK); page++) - { - *(volatile __u32*) address = 0; - MCFCFM_CMD = MCFCFM_CMD_PGERS; - MCFCFM_USTAT = MCFCFM_USTAT_CBEIF; - rc = cfm_flash_readycheck(0); - if (rc==ERR_OK) - { - *(volatile __u32*) address = 0; - MCFCFM_CMD = MCFCFM_CMD_PGERSVER; - MCFCFM_USTAT = MCFCFM_USTAT_CBEIF; - rc = cfm_flash_readycheck(1); - } - address += 0x800; - } - return rc; -} - -int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - int rc; - ulong dest, data; - - rc = ERR_OK; - if (addr & 3) - { - debug ("Byte and Word alignment not supported\n"); - rc = ERR_ALIGN; - } - if (cnt & 3) - { - debug ("Byte and Word transfer not supported\n"); - rc = ERR_ALIGN; - } - dest = cmf_backdoor_address(addr); - while ((cnt>=4) && (rc == ERR_OK)) - { - data = *((volatile u32 *) src); - *(volatile u32*) dest = data; - MCFCFM_CMD = MCFCFM_CMD_PGM; - MCFCFM_USTAT = MCFCFM_USTAT_CBEIF; - rc = cfm_flash_readycheck(0); - if (*(volatile u32*) addr != data) rc = ERR_PROG_ERROR; - src +=4; - dest +=4; - addr +=4; - cnt -=4; - } - return rc; -} - -#ifdef CONFIG_SYS_FLASH_PROTECTION - -int cfm_flash_protect(flash_info_t * info,long sector,int prot) -{ - int rc; - - rc= ERR_OK; - if (prot) - { - MCFCFM_PROT |= (1<<sector); - info->protect[sector]=1; - } - else - { - MCFCFM_PROT &= ~(1<<sector); - info->protect[sector]=0; - } - return rc; -} - -#endif - -#endif diff --git a/board/BuS/eb_cpu5282/cfm_flash.h b/board/BuS/eb_cpu5282/cfm_flash.h deleted file mode 100644 index ed4e7943e7..0000000000 --- a/board/BuS/eb_cpu5282/cfm_flash.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Basic Flash Driver for Freescale MCF 5282 internal FLASH - * - * (C) Copyright 2005 BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CFM_FLASH_H_ -#define __CFM_FLASH_H_ - -#define FREESCALE_MANUFACT 0xFACFFACF -#define FREESCALE_ID_MCF5281 0x5281 -#define FREESCALE_ID_MCF5282 0x5282 - -extern void cfm_flash_print_info (flash_info_t * info); -extern int cfm_flash_erase_sector (flash_info_t * info, int sector); -extern void cfm_flash_init (flash_info_t * info); -extern int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt); -#ifdef CONFIG_SYS_FLASH_PROTECTION -extern int cfm_flash_protect(flash_info_t * info,long sector,int prot); -#endif - -#endif diff --git a/board/BuS/eb_cpu5282/eb_cpu5282.c b/board/BuS/eb_cpu5282/eb_cpu5282.c index d64ad1b705..f73431eff5 100644 --- a/board/BuS/eb_cpu5282/eb_cpu5282.c +++ b/board/BuS/eb_cpu5282/eb_cpu5282.c @@ -35,18 +35,19 @@ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_VIDEO unsigned long display_width; unsigned long display_height; +#endif /*---------------------------------------------------------------------------*/ int checkboard (void) { - puts ("Board: MCF-EV1 + MCF-EV23 (BuS Elektronik GmbH & Co. KG)\n"); + puts("Board: EB+CPU5282 (BuS Elektronik GmbH & Co. KG)\n"); #if (CONFIG_SYS_TEXT_BASE == CONFIG_SYS_INT_FLASH_BASE) - puts (" Boot from Internal FLASH\n"); + puts(" Boot from Internal FLASH\n"); #endif - return 0; } @@ -55,29 +56,39 @@ phys_size_t initdram (int board_type) int size, i; size = 0; - MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6 - | MCFSDRAMC_DCR_RC ((15 * CONFIG_SYS_CLK) >> 4); + MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6 | + MCFSDRAMC_DCR_RC((15 * CONFIG_SYS_CLK / 1000000) >> 4); + asm (" nop"); #ifdef CONFIG_SYS_SDRAM_BASE0 - - MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE0) - | MCFSDRAMC_DACR_CASL (1) - | MCFSDRAMC_DACR_CBM (3) - | MCFSDRAMC_DACR_PS_16; + MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE0)| + MCFSDRAMC_DACR_CASL(1) | MCFSDRAMC_DACR_CBM(3) | + MCFSDRAMC_DACR_PS_32; + asm (" nop"); MCFSDRAMC_DMR0 = MCFSDRAMC_DMR_BAM_16M | MCFSDRAMC_DMR_V; + asm (" nop"); MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP; + asm (" nop"); + for (i = 0; i < 10; i++) + asm (" nop"); - *(unsigned short *) (CONFIG_SYS_SDRAM_BASE0) = 0xA5A5; + *(unsigned long *)(CONFIG_SYS_SDRAM_BASE0) = 0xA5A5A5A5; + asm (" nop"); MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE; + asm (" nop"); + for (i = 0; i < 2000; i++) asm (" nop"); - mbar_writeLong (MCFSDRAMC_DACR0, - mbar_readLong (MCFSDRAMC_DACR0) | MCFSDRAMC_DACR_IMRS); - *(unsigned int *) (CONFIG_SYS_SDRAM_BASE0 + 0x220) = 0xA5A5; - size += CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; + + MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS; + asm (" nop"); + /* write SDRAM mode register */ + *(unsigned long *)(CONFIG_SYS_SDRAM_BASE0 + 0x80440) = 0xA5A5A5A5; + asm (" nop"); + size += CONFIG_SYS_SDRAM_SIZE0 * 1024 * 1024; #endif -#ifdef CONFIG_SYS_SDRAM_BASE1 +#ifdef CONFIG_SYS_SDRAM_BASE1xx MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE1) | MCFSDRAMC_DACR_CASL (1) | MCFSDRAMC_DACR_CBM (3) @@ -134,38 +145,74 @@ int testdram (void) } #endif +#if defined(CONFIG_HW_WATCHDOG) + +void hw_watchdog_init(void) +{ + char *s; + int enable; + + enable = 1; + s = getenv("watchdog"); + if (s != NULL) + if ((strncmp(s, "off", 3) == 0) || (strncmp(s, "0", 1) == 0)) + enable = 0; + if (enable) + MCFGPTA_GPTDDR |= (1<<2); + else + MCFGPTA_GPTDDR &= ~(1<<2); +} + +void hw_watchdog_reset(void) +{ + MCFGPTA_GPTPORT ^= (1<<2); +} +#endif + int misc_init_r(void) { #ifdef CONFIG_HW_WATCHDOG hw_watchdog_init(); #endif -#ifndef CONFIG_VIDEO - vcxk_init(16, 16); -#endif return 1; } -#if defined(CONFIG_VIDEO) +void __led_toggle(led_id_t mask) +{ + MCFGPTA_GPTPORT ^= (1 << 3); +} -/* - ****h* EB+CPU5282-T1/drv_video_init - * FUNCTION - *** - */ +void __led_init(led_id_t mask, int state) +{ + __led_set(mask, state); + MCFGPTA_GPTDDR |= (1 << 3); +} + +void __led_set(led_id_t mask, int state) +{ + if (state == STATUS_LED_ON) + MCFGPTA_GPTPORT |= (1 << 3); + else + MCFGPTA_GPTPORT &= ~(1 << 3); +} + +#if defined(CONFIG_VIDEO) int drv_video_init(void) { char *s; +#ifdef CONFIG_SPLASH_SCREEN unsigned long splash; - +#endif printf("Init Video as "); - - if ((s = getenv("displaywidth")) != NULL) + s = getenv("displaywidth"); + if (s != NULL) display_width = simple_strtoul(s, NULL, 10); else display_width = 256; - if ((s = getenv("displayheight")) != NULL) + s = getenv("displayheight"); + if (s != NULL) display_height = simple_strtoul(s, NULL, 10); else display_height = 256; @@ -178,10 +225,9 @@ int drv_video_init(void) vcxk_init(display_width, display_height); #ifdef CONFIG_SPLASH_SCREEN - if ((s = getenv("splashimage")) != NULL) { - debug("use splashimage: %s\n", s); + s = getenv("splashimage"); + if (s != NULL) { splash = simple_strtoul(s, NULL, 16); - debug("use splashimage: %x\n", splash); vcxk_acknowledge_wait(); video_display_bitmap(splash, 0, 0); } diff --git a/board/BuS/eb_cpu5282/flash.c b/board/BuS/eb_cpu5282/flash.c deleted file mode 100644 index 8b7f9578fc..0000000000 --- a/board/BuS/eb_cpu5282/flash.c +++ /dev/null @@ -1,415 +0,0 @@ -/* - * (C) Copyright 2005 - * BuS Elektronik GmbH & Co.KG <esw@bus-elektonik.de> - * - * Based On - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include "cfm_flash.h" - -#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE -#define FLASH_BANK_SIZE 0x200000 - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (AMD_MANUFACT & FLASH_VENDMASK): - printf ("AMD: "); - switch (info->flash_id & FLASH_TYPEMASK) { - case (AMD_ID_LV160B & FLASH_TYPEMASK): - printf ("AM29LV160B (16Bit)\n"); - break; - default: - printf ("Unknown Chip Type\n"); - break; - } - break; - case FREESCALE_MANUFACT & FLASH_VENDMASK: - cfm_flash_print_info (info); - break; - default: - printf ("Unknown Vendor "); - break; - } - - puts (" Size: "); - if ((info->size >> 20) > 0) - { - printf ("%ld MiB",info->size >> 20); - } - else - { - printf ("%ld KiB",info->size >> 10); - } - printf (" in %d Sectors\n", info->sector_count); - - printf (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 4) == 0) { - printf ("\n "); - } - printf ("%02d: %08lX%s ", i,info->start[i], - info->protect[i] ? " P" : " "); - } - printf ("\n\n"); -} - -unsigned long flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - switch (i) - { - case 1: - flash_info[i].flash_id = - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_LV160B & FLASH_TYPEMASK); - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - flashbase = PHYS_FLASH_1; - for (j = 0; j < flash_info[i].sector_count; j++) { - if (j == 0) { - /* 1st is 16 KiB */ - flash_info[i].start[j] = flashbase; - } - if ((j >= 1) && (j <= 2)) { - /* 2nd and 3rd are 8 KiB */ - flash_info[i].start[j] = - flashbase + 0x4000 + 0x2000 * (j - 1); - } - if (j == 3) { - /* 4th is 32 KiB */ - flash_info[i].start[j] = flashbase + 0x8000; - } - if ((j >= 4) && (j <= 34)) { - /* rest is 256 KiB */ - flash_info[i].start[j] = - flashbase + 0x10000 + 0x10000 * (j - 4); - } - } - break; - case 0: - cfm_flash_init (&flash_info[i]); - break; - default: - panic ("configured to many flash banks!\n"); - } - - size += flash_info[i].size; - } - - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + 0xffff, &flash_info[0]); - - return size; -} - -#define CMD_READ_ARRAY 0x00F0 -#define CMD_UNLOCK1 0x00AA -#define CMD_UNLOCK2 0x0055 -#define CMD_ERASE_SETUP 0x0080 -#define CMD_ERASE_CONFIRM 0x0030 -#define CMD_PROGRAM 0x00A0 -#define CMD_UNLOCK_BYPASS 0x0020 - -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(info->start[0] + (0x00000555<<1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(info->start[0] + (0x000002AA<<1))) - - -#define BIT_ERASE_DONE 0x0080 -#define BIT_RDY_MASK 0x0080 -#define BIT_PROGRAM_ERROR 0x0020 -#define BIT_TIMEOUT 0x80000000 /* our flag */ - -#define ERR_READY -1 - -int amd_flash_erase_sector(flash_info_t * info, int sector) -{ - int state; - ulong result; - ulong start; - - volatile u16 *addr = - (volatile u16 *) (info->start[sector]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - state = 0; - start = get_timer(0); - - do { - result = *addr; - - /* check timeout */ - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - state = ERR_TIMOUT; - } - - if (!state && (result & 0xFFFF) & BIT_ERASE_DONE) - state = ERR_READY; - } - while (!state); - if (state == ERR_READY) - state = ERR_OK; - - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - - return state; -} - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - int iflag, cflag; - int sector; - int rc; - - rc = ERR_OK; - - if (info->flash_id == FLASH_UNKNOWN) - { - rc = ERR_UNKNOWN_FLASH_TYPE; - } /* (info->flash_id == FLASH_UNKNOWN) */ - - if ((s_first < 0) || (s_first > s_last) || s_last >= info->sector_count) - { - rc = ERR_INVAL; - } - - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - for (sector = s_first; (sector <= s_last) && (rc == ERR_OK); sector++) { - - if (info->protect[sector]) - { - putc('P'); /* protected sector will not erase */ - } - else - { - /* erase on unprotected sector */ - puts("E\b"); - switch (info->flash_id & FLASH_VENDMASK) - { - case (AMD_MANUFACT & FLASH_VENDMASK): - rc = amd_flash_erase_sector(info,sector); - break; - case (FREESCALE_MANUFACT & FLASH_VENDMASK): - rc = cfm_flash_erase_sector(info,sector); - break; - default: - return ERR_UNKNOWN_FLASH_VENDOR; - } - putc('.'); - } - } - if (rc!=ERR_OK) - { - printf ("\n "); - flash_perror (rc); - } - else - { - printf (" done\n"); - } - - udelay (10000); /* allow flash to settle - wait 10 ms */ - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -volatile static int amd_write_word (flash_info_t * info, ulong dest, u16 data) -{ - volatile u16 *addr; - ulong result; - int cflag, iflag; - int state; - ulong start; - - /* - * Check if Flash is (sufficiently) erased - */ - addr = (volatile u16 *) dest; - - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - start = get_timer(0); - - /* wait until flash is ready */ - state = 0; - do { - result = *addr; - - /* check timeout */ - if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) { - state = ERR_TIMOUT; - } - if (!state && ((result & BIT_RDY_MASK) == (data & BIT_RDY_MASK))) - state = ERR_READY; - - } while (!state); - - *addr = CMD_READ_ARRAY; - - if (state == ERR_READY) - state = ERR_OK; - if ((*addr != data) && (state != ERR_TIMOUT)) - state = ERR_PROG_ERROR; - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return state; -} - -int amd_flash_write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - int rc; - ulong dest; - u16 data; - - rc = ERR_OK; - if (addr & 1) - { - debug ("Byte alignment not supported\n"); - rc = ERR_ALIGN; - } - if (cnt & 1) - { - debug ("Byte transfer not supported\n"); - rc = ERR_ALIGN; - } - - dest = addr; - while ((cnt>=2) && (rc == ERR_OK)) - { - data = *((volatile u16 *) src); - rc=amd_write_word (info,dest,data); - src +=2; - dest +=2; - cnt -=2; - } - return rc; -} - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - int rc; - - switch (info->flash_id & FLASH_VENDMASK) - { - case (AMD_MANUFACT & FLASH_VENDMASK): - rc = amd_flash_write_buff(info,src,addr,cnt); - break; - case (FREESCALE_MANUFACT & FLASH_VENDMASK): - rc = cfm_flash_write_buff(info,src,addr,cnt); - break; - default: - rc = ERR_UNKNOWN_FLASH_VENDOR; - } - return rc; - -} -int amd_flash_protect(flash_info_t * info,long sector,int prot) -{ - int rc; - rc= ERR_OK; - if (prot) - { - info->protect[sector]=1; - } - else - { - info->protect[sector]=0; - } - return rc; -} - -#ifdef CONFIG_SYS_FLASH_PROTECTION - -int flash_real_protect(flash_info_t * info,long sector,int prot) -{ - int rc; - - switch (info->flash_id & FLASH_VENDMASK) - { - case (AMD_MANUFACT & FLASH_VENDMASK): - rc = amd_flash_protect(info,sector,prot); - break; - case (FREESCALE_MANUFACT & FLASH_VENDMASK): - rc = cfm_flash_protect(info,sector,prot); - break; - default: - rc = ERR_UNKNOWN_FLASH_VENDOR; - } - return rc; -} - -#endif diff --git a/board/BuS/eb_cpu5282/config.mk b/board/a3m071/Makefile index 18fb84eb3b..6f961fb6e3 100644 --- a/board/BuS/eb_cpu5282/config.mk +++ b/board/a3m071/Makefile @@ -1,8 +1,4 @@ # -# (C) Copyright 2000-2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# Coldfire contribution by Bernhard Kuhn <bkuhn@metrowerks.com> -# # See file CREDITS for list of people who contributed to this # project. # @@ -16,12 +12,25 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -ifndef CONFIG_SYS_TEXT_BASE -CONFIG_SYS_TEXT_BASE = 0xFE000000 -endif +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/a3m071/README b/board/a3m071/README new file mode 100644 index 0000000000..7698614a62 --- /dev/null +++ b/board/a3m071/README @@ -0,0 +1,80 @@ +------------------------------------------------------------------------ +A3M071 board support +------------------------------------------------------------------------ + + +SPL NOR flash support: +---------------------- +To boot fast into the OS (Linux), this board port integrates the SPL +framework. This means, that a special, stripped-down version of +U-Boot runs in the beginning. In the case of the A3M071 board, this +SPL U-Boot version is less than 16 KiB big. This SPL U-Boot can either +boot the OS (Linux) or a "real", full-blown U-Boot. This detection +on whether to boot Linux or U-Boot is done by using the "boot_os" +environment variable. If "boot_os" is set to "yes", Linux will be +loaded and booted from the SPL U-Boot version. Otherwise, the +full-blown U-Boot version will be loaded and run. + +Enabling Linux booting: +----------------------- +From U-Boot: +=> setenv boot_os yes +=> saveenv + +From Linux: +$ fw_setenv boot_os yes + +Enabling U-Boot booting: +------------------------ +From U-Boot: +=> setenv boot_os no +=> saveenv + +From Linux: +$ fw_setenv boot_os no + + +Preparing Linux image(s) for booting from SPL U-Boot: +----------------------------------------------------- +To boot the Linux kernel from the SPL, the DT blob (fdt) needs to get +prepard/patched first. U-Boot usually inserts some dynamic values into +the DT binary (blob), e.g. autodetected memory size, MAC addresses, +clocks speeds etc. To generate this patched DT blob, you can use +the following command: + +1. Load fdt blob to SDRAM: +=> tftp 1800000 a3m071/a3m071.dtb + +2. Set bootargs as desired for Linux booting (e.g. flash_mtd): +=> run mtdargs addip2 addtty + +3. Use "fdt" commands to patch the DT blob: +=> fdt addr 1800000 +=> fdt boardsetup +=> fdt chosen + +4. Display patched DT blob (optional): +=> fdt print + +5. Save fdt to NOR flash: +=> erase fc060000 fc07ffff +=> cp.b 1800000 fc060000 10000 + +All this can be integrated into an environment command: +=> setenv upd_fdt 'tftp 1800000 a3m071/a3m071.dtb;run mtdargs addip2 addtty; \ + fdt addr 1800000;fdt boardsetup;erase fc060000 fc07ffff; \ + cp.b 1800000 fc060000 10000' +=> saveenv + +After this, only "run upd_fdt" needs to get called to load, patch +and save the DT blob into NOR flash. + +Additionally, the Linux kernel image has to be saved uncompressed in +its uImage file (and not gzip compressed). This can be done with this +command: + +$ mkimage -A ppc -O linux -T kernel -C none -a 0 -e 0 \ + -n "Linux Kernel Image" -d vmlinux.bin uImage.uncompressed + +------------------------------------------------------------------------ +Stefan Roese, 2012-08-23 diff --git a/board/a3m071/a3m071.c b/board/a3m071/a3m071.c new file mode 100644 index 0000000000..89ced824eb --- /dev/null +++ b/board/a3m071/a3m071.c @@ -0,0 +1,335 @@ +/* + * (C) Copyright 2003-2004 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. + * + * (C) Copyright 2006 + * MicroSys GmbH + * + * Copyright 2012 Stefan Roese <sr@denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + */ + +#include <common.h> +#include <command.h> +#include <mpc5xxx.h> +#include <pci.h> +#include <miiphy.h> +#include <asm/processor.h> +#include <asm/io.h> + +#include "mt46v16m16-75.h" + +DECLARE_GLOBAL_DATA_PTR; + +#if !defined(CONFIG_SYS_RAMBOOT) && \ + (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD)) +static void sdram_start(int hi_addr) +{ + long hi_addr_bit = hi_addr ? 0x01000000 : 0; + long control = SDRAM_CONTROL | hi_addr_bit; + + /* unlock mode register */ + out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000); + + /* precharge all banks */ + out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002); + +#ifdef SDRAM_DDR + /* set mode register: extended mode */ + out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE); + + /* set mode register: reset DLL */ + out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000); +#endif + + /* precharge all banks */ + out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002); + + /* auto refresh */ + out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004); + + /* set mode register */ + out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE); + + /* normal operation */ + out_be32((void *)MPC5XXX_SDRAM_CTRL, control); +} +#endif + +/* + * ATTENTION: Although partially referenced initdram does NOT make real use + * use of CONFIG_SYS_SDRAM_BASE. The code does not work if + * CONFIG_SYS_SDRAM_BASE is something else than 0x00000000. + */ +phys_size_t initdram(int board_type) +{ + ulong dramsize = 0; + ulong dramsize2 = 0; + uint svr, pvr; +#if !defined(CONFIG_SYS_RAMBOOT) && \ + (defined(CONFIG_SPL) && defined(CONFIG_SPL_BUILD)) + ulong test1, test2; + + /* setup SDRAM chip selects */ + out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */ + out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */ + + /* setup config registers */ + out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1); + out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2); + +#ifdef SDRAM_DDR + /* set tap delay */ + out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY); +#endif + + /* find RAM size using SDRAM CS0 only */ + sdram_start(0); + test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); + sdram_start(1); + test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); + if (test1 > test2) { + sdram_start(0); + dramsize = test1; + } else { + dramsize = test2; + } + + /* memory smaller than 1MB is impossible */ + if (dramsize < (1 << 20)) + dramsize = 0; + + /* set SDRAM CS0 size according to the amount of RAM found */ + if (dramsize > 0) { + out_be32((void *)MPC5XXX_SDRAM_CS0CFG, + 0x13 + __builtin_ffs(dramsize >> 20) - 1); + } else { + out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */ + } +#else /* CONFIG_SYS_RAMBOOT */ + + /* retrieve size of memory connected to SDRAM CS0 */ + dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF; + if (dramsize >= 0x13) + dramsize = (1 << (dramsize - 0x13)) << 20; + else + dramsize = 0; + + /* retrieve size of memory connected to SDRAM CS1 */ + dramsize2 = in_be32((void *)MPC5XXX_SDRAM_CS1CFG) & 0xFF; + if (dramsize2 >= 0x13) + dramsize2 = (1 << (dramsize2 - 0x13)) << 20; + else + dramsize2 = 0; + +#endif /* CONFIG_SYS_RAMBOOT */ + + /* + * On MPC5200B we need to set the special configuration delay in the + * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM + * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: + * + * "The SDelay should be written to a value of 0x00000004. It is + * required to account for changes caused by normal wafer processing + * parameters." + */ + svr = get_svr(); + pvr = get_pvr(); + if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) + out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04); + + return dramsize + dramsize2; +} + +static void get_revisions(int *failsavelevel, int *digiboardversion, + int *fpgaversion) +{ + struct mpc5xxx_gpt_0_7 *gpt = (struct mpc5xxx_gpt_0_7 *)MPC5XXX_GPT; + u8 val; + + /* + * Figure out failsavelevel + * see ticket dsvk#59 + */ + *failsavelevel = 0; /* 0=failsave, 1=board ok, 2=fpga ok */ + + /* read digitalboard-version from TMR[2..4] */ + val = 0; + val |= (gpt->gpt2.sr & (1 << (31 - 23))) ? (1) : 0; + val |= (gpt->gpt3.sr & (1 << (31 - 23))) ? (1 << 1) : 0; + val |= (gpt->gpt4.sr & (1 << (31 - 23))) ? (1 << 2) : 0; + *digiboardversion = val; + + if (*digiboardversion == 0) { + *failsavelevel = 1; /* digiboard-version ok */ + + /* read fpga-version from TMR[5..7] */ + val = 0; + val |= (gpt->gpt5.sr & (1 << (31 - 23))) ? (1) : 0; + val |= (gpt->gpt6.sr & (1 << (31 - 23))) ? (1 << 1) : 0; + val |= (gpt->gpt7.sr & (1 << (31 - 23))) ? (1 << 2) : 0; + *fpgaversion = val; + + if (*fpgaversion == 1) + *failsavelevel = 2; /* fpga-version ok */ + } +} + +/* + * This function is called from the SPL U-Boot version for + * early init stuff, that needs to be done for OS (e.g. Linux) + * booting. Doing it later in the real U-Boot would not work + * in case that the SPL U-Boot boots Linux directly. + */ +void spl_board_init(void) +{ + struct mpc5xxx_gpio *gpio = (struct mpc5xxx_gpio *)MPC5XXX_GPIO; + struct mpc5xxx_mmap_ctl *mm = + (struct mpc5xxx_mmap_ctl *)CONFIG_SYS_MBAR; + int digiboardversion; + int failsavelevel; + int fpgaversion; + u32 val; + + get_revisions(&failsavelevel, &digiboardversion, &fpgaversion); + + val = in_be32(&mm->ipbi_ws_ctrl); + + /* first clear bits 19..21 (CS3...5) */ + val &= ~((1 << 19) | (1 << 20) | (1 << 21)); + if (failsavelevel == 2) { + /* FPGA ok */ + val |= (1 << 19) | (1 << 21); + } + + if (failsavelevel >= 1) { + /* at least digiboard-version ok */ + val |= (1 << 20); + } + + /* And write new value back to register */ + out_be32(&mm->ipbi_ws_ctrl, val); + + /* + * No need to change the pin multiplexing (MPC5XXX_GPS_PORT_CONFIG) + * as all 3 config versions (failsave level) have the same setup. + */ + + /* + * Setup gpio_wkup_7 as watchdog AS INPUT to disable it - see + * ticket #60 + * + * MPC5XXX_WU_GPIO_DIR direction is already 0 (INPUT) + * set bit 0(msb) to 1 + */ + setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, 1 << (31 - 0)); + + /* setup GPIOs for status-leds if needed - see ticket #57 */ + if (failsavelevel > 0) { + /* digiboard-version is OK */ + /* LED is LOW ACTIVE - so deactivate by set output to 1 */ + gpio->simple_dvo |= 1 << (31 - 12); + gpio->simple_dvo |= 1 << (31 - 13); + /* set GPIO direction to output */ + gpio->simple_ddr |= 1 << (31 - 12); + gpio->simple_ddr |= 1 << (31 - 13); + /* open drain config is set to "normal output" at reset */ + /* gpio->simple_ode &=~ ( 1 << (31-12) ); */ + /* gpio->simple_ode &=~ ( 1 << (31-13) ); */ + /* enable as GPIO */ + gpio->simple_gpioe |= 1 << (31 - 12); + gpio->simple_gpioe |= 1 << (31 - 13); + } + + /* setup fpga irq - see ticket #65 */ + if (failsavelevel > 1) { + /* + * The main irq initialisation is done in interrupts.c + * mpc5xxx_init_irq + */ + struct mpc5xxx_intr *intr = + (struct mpc5xxx_intr *)(MPC5XXX_ICTL); + + setbits_be32(&intr->ctrl, 0x08C01801); + + /* + * The MBAR+0x0524 Bit 21:23 CSe are ignored here due to the + * already cleared (intr_ctrl) MBAR+0x0510 ECLR[0] bit above + */ + } + +} + +int checkboard(void) +{ + int digiboardversion; + int failsavelevel; + int fpgaversion; + + get_revisions(&failsavelevel, &digiboardversion, &fpgaversion); + + puts("Board: A3M071\n"); + printf("Rev: failsave level %u\n", failsavelevel); + printf(" digiboard IO version %u\n", digiboardversion); + if (failsavelevel > 0) /* only if fpga-version red */ + printf(" fpga IO version %u\n", fpgaversion); + + return 0; +} + +/* miscellaneous platform dependent initialisations */ +int misc_init_r(void) +{ + /* adjust flash start and offset to detected values */ + gd->bd->bi_flashstart = flash_info[0].start[0]; + gd->bd->bi_flashoffset = 0; + + /* adjust mapping */ + out_be32((void *)MPC5XXX_BOOTCS_START, + START_REG(gd->bd->bi_flashstart)); + out_be32((void *)MPC5XXX_CS0_START, START_REG(gd->bd->bi_flashstart)); + out_be32((void *)MPC5XXX_BOOTCS_STOP, + STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize)); + out_be32((void *)MPC5XXX_CS0_STOP, + STOP_REG(gd->bd->bi_flashstart, gd->bd->bi_flashsize)); + + return 0; +} + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t * bd) +{ + ft_cpu_setup(blob, bd); +} +#endif /* defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP) */ + +#ifdef CONFIG_SPL_OS_BOOT +/* + * A3M071 specific implementation of spl_start_uboot() + * + * RETURN + * 0 if booting into OS is selected (default) + * 1 if booting into U-Boot is selected + */ +int spl_start_uboot(void) +{ + char s[8]; + + env_init(); + getenv_f("boot_os", s, sizeof(s)); + if ((s != NULL) && (strcmp(s, "yes") == 0)) + return 0; + + return 1; +} +#endif diff --git a/board/chromebook-x86/coreboot/coreboot_pci.c b/board/a3m071/mt46v16m16-75.h index 732ca3ceaf..e49e99618a 100644 --- a/board/chromebook-x86/coreboot/coreboot_pci.c +++ b/board/a3m071/mt46v16m16-75.h @@ -1,10 +1,6 @@ /* - * Copyright (c) 2011 The Chromium OS Authors. - * (C) Copyright 2008,2009 - * Graeme Russ, <graeme.russ@gmail.com> - * - * (C) Copyright 2002 - * Daniel Engström, Omicron Ceti AB, <daniel@omicron.se> + * (C) Copyright 2004 + * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. * * See file CREDITS for list of people who contributed to this * project. @@ -16,15 +12,21 @@ * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA */ -void pci_init_board(void) -{ -} +#define SDRAM_DDR /* is DDR */ + +#if defined(CONFIG_MPC5200) +/* Settings for XLB = 132 MHz */ +#define SDRAM_MODE 0x018D0000 +#define SDRAM_EMODE 0x40090000 +#define SDRAM_CONTROL 0x704f0f00 +#define SDRAM_CONFIG1 0x73722930 +#define SDRAM_CONFIG2 0x47770000 +#define SDRAM_TAPDELAY 0x10000000 + +#else +#error CONFIG_MPC5200 not defined +#endif diff --git a/board/chromebook-x86/coreboot/Makefile b/board/chromebook-x86/coreboot/Makefile index cfcc0dfbe5..886baf6c96 100644 --- a/board/chromebook-x86/coreboot/Makefile +++ b/board/chromebook-x86/coreboot/Makefile @@ -32,9 +32,6 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS-y += coreboot.o -COBJS-$(CONFIG_PCI) += coreboot_pci.o -SOBJS-y += coreboot_start16.o SOBJS-y += coreboot_start.o SRCS := $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c) diff --git a/board/chromebook-x86/coreboot/config.mk b/board/chromebook-x86/coreboot/config.mk new file mode 100644 index 0000000000..f720851aac --- /dev/null +++ b/board/chromebook-x86/coreboot/config.mk @@ -0,0 +1,37 @@ +# +# Copyright (c) 2011 The Chromium OS Authors. All rights reserved. +# Use of this source code is governed by a BSD-style license that can be +# found in the LICENSE file. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above +# copyright notice, this list of conditions and the following disclaimer +# in the documentation and/or other materials provided with the +# distribution. +# * Neither the name of Google Inc. nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# +# Alternatively, this software may be distributed under the terms of the +# GNU General Public License ("GPL") version 2 as published by the Free +# Software Foundation. +# + +HOSTCFLAGS_autoconf.mk.dep = -Wno-variadic-macros diff --git a/board/chromebook-x86/coreboot/coreboot.c b/board/chromebook-x86/coreboot/coreboot.c deleted file mode 100644 index 22a643c9d6..0000000000 --- a/board/chromebook-x86/coreboot/coreboot.c +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * (C) Copyright 2008 - * Graeme Russ, graeme.russ@gmail.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/u-boot-x86.h> -#include <flash.h> -#include <netdev.h> -#include <asm/arch-coreboot/tables.h> -#include <asm/arch-coreboot/sysinfo.h> - -DECLARE_GLOBAL_DATA_PTR; - -unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN; - -/* - * Miscellaneous platform dependent initializations - */ -int cpu_init_f(void) -{ - int ret = get_coreboot_info(&lib_sysinfo); - if (ret != 0) - printf("Failed to parse coreboot tables.\n"); - return ret; -} - -int board_early_init_f(void) -{ - return 0; -} - -int board_early_init_r(void) -{ - /* CPU Speed to 100MHz */ - gd->cpu_clk = 100000000; - - /* Crystal is 33.000MHz */ - gd->bus_clk = 33000000; - - return 0; -} - -void show_boot_progress(int val) -{ -} - - -int last_stage_init(void) -{ - return 0; -} - -#ifndef CONFIG_SYS_NO_FLASH -ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) -{ - return 0; -} -#endif - -int board_eth_init(bd_t *bis) -{ - return pci_eth_init(bis); -} - -void setup_pcat_compatibility() -{ -} diff --git a/board/chromebook-x86/coreboot/coreboot_start16.S b/board/chromebook-x86/coreboot/coreboot_start16.S deleted file mode 100644 index 9ad06df8bc..0000000000 --- a/board/chromebook-x86/coreboot/coreboot_start16.S +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright (c) 2011 The Chromium OS Authors. - * (C) Copyright 2008 - * Graeme Russ, graeme.russ@gmail.com. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * 16bit initialization code. - * This code have to map the area of the boot flash - * that is used by U-boot to its final destination. - */ - -.text -.section .start16, "ax" -.code16 -.globl board_init16 -board_init16: - jmp board_init16_ret - -.section .bios, "ax" -.code16 -.globl realmode_reset -.hidden realmode_reset -.type realmode_reset, @function -realmode_reset: - -1: hlt - jmp 1 diff --git a/board/chromebook-x86/dts/alex.dts b/board/chromebook-x86/dts/alex.dts new file mode 100644 index 0000000000..cb6a9e41ee --- /dev/null +++ b/board/chromebook-x86/dts/alex.dts @@ -0,0 +1,24 @@ +/dts-v1/; + +/include/ "coreboot.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "Google Alex"; + compatible = "google,alex", "intel,atom-pineview"; + + config { + silent_console = <0>; + }; + + gpio: gpio {}; + + serial { + reg = <0x3f8 8>; + clock-frequency = <115200>; + }; + + chosen { }; + memory { device_type = "memory"; reg = <0 0>; }; +}; diff --git a/board/chromebook-x86/dts/link.dts b/board/chromebook-x86/dts/link.dts new file mode 100644 index 0000000000..af60f59de7 --- /dev/null +++ b/board/chromebook-x86/dts/link.dts @@ -0,0 +1,24 @@ +/dts-v1/; + +/include/ "coreboot.dtsi" + +/ { + #address-cells = <1>; + #size-cells = <1>; + model = "Google Link"; + compatible = "google,link", "intel,celeron-ivybridge"; + + config { + silent_console = <0>; + }; + + gpio: gpio {}; + + serial { + reg = <0x3f8 8>; + clock-frequency = <115200>; + }; + + chosen { }; + memory { device_type = "memory"; reg = <0 0>; }; +}; diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c index c41f11d60c..a3079dbca3 100644 --- a/board/davedenx/qong/qong.c +++ b/board/davedenx/qong/qong.c @@ -28,11 +28,12 @@ #include <asm/arch/sys_proto.h> #include <asm/io.h> #include <nand.h> -#include <pmic.h> +#include <power/pmic.h> #include <fsl_pmic.h> #include <asm/gpio.h> #include "qong_fpga.h" #include <watchdog.h> +#include <errno.h> DECLARE_GLOBAL_DATA_PTR; @@ -172,10 +173,15 @@ int board_late_init(void) { u32 val; struct pmic *p; + int ret; - pmic_init(); - p = get_pmic(); + ret = pmic_init(I2C_PMIC); + if (ret) + return ret; + p = pmic_get("FSL_PMIC"); + if (!p) + return -ENODEV; /* Enable RTC battery */ pmic_reg_read(p, REG_POWER_CTL0, &val); pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN); diff --git a/board/exmeritus/hww1u1a/hww1u1a.c b/board/exmeritus/hww1u1a/hww1u1a.c index 52c22faaa0..89cfaad91f 100644 --- a/board/exmeritus/hww1u1a/hww1u1a.c +++ b/board/exmeritus/hww1u1a/hww1u1a.c @@ -105,7 +105,7 @@ int checkboard(void) * and delay a while before we continue. */ if (mpc85xx_gpio_get(GPIO_RESETS)) { - ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; + ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; puts("Debugger detected... extra device reset enabled!\n"); diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index 36f7c4f30f..75725b49ad 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -53,6 +53,7 @@ COBJS-$(CONFIG_P2020DS) += ics307_clk.o COBJS-$(CONFIG_P3041DS) += ics307_clk.o COBJS-$(CONFIG_P4080DS) += ics307_clk.o COBJS-$(CONFIG_P5020DS) += ics307_clk.o +COBJS-$(CONFIG_P5040DS) += ics307_clk.o COBJS-$(CONFIG_VSC_CROSSBAR) += vsc3316_3308.o # deal with common files for P-series corenet based devices @@ -60,6 +61,7 @@ SUBLIB-$(CONFIG_P2041RDB) += p_corenet/libp_corenet.o SUBLIB-$(CONFIG_P3041DS) += p_corenet/libp_corenet.o SUBLIB-$(CONFIG_P4080DS) += p_corenet/libp_corenet.o SUBLIB-$(CONFIG_P5020DS) += p_corenet/libp_corenet.o +SUBLIB-$(CONFIG_P5040DS) += p_corenet/libp_corenet.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/freescale/common/ngpixis.h b/board/freescale/common/ngpixis.h index 1d4483d8b9..a239ee31df 100644 --- a/board/freescale/common/ngpixis.h +++ b/board/freescale/common/ngpixis.h @@ -45,7 +45,7 @@ typedef struct ngpixis { struct { u8 sw; u8 en; - } s[8]; + } s[9]; /* s[0]..s[7] is SW1..SW8, and s[8] is SW11 */ } __attribute__ ((packed)) ngpixis_t; /* Pointer to the PIXIS register set */ diff --git a/board/freescale/corenet_ds/Makefile b/board/freescale/corenet_ds/Makefile index 1fdf8b706b..d79193af2a 100644 --- a/board/freescale/corenet_ds/Makefile +++ b/board/freescale/corenet_ds/Makefile @@ -31,9 +31,11 @@ COBJS-y += ddr.o COBJS-$(CONFIG_P3041DS) += eth_hydra.o COBJS-$(CONFIG_P4080DS) += eth_p4080.o COBJS-$(CONFIG_P5020DS) += eth_hydra.o +COBJS-$(CONFIG_P5040DS) += eth_superhydra.o COBJS-$(CONFIG_P3041DS) += p3041ds_ddr.o COBJS-$(CONFIG_P4080DS) += p4080ds_ddr.o COBJS-$(CONFIG_P5020DS) += p5020ds_ddr.o +COBJS-$(CONFIG_P5040DS) += p5040ds_ddr.o SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) diff --git a/board/freescale/corenet_ds/corenet_ds.c b/board/freescale/corenet_ds/corenet_ds.c index a33c936fa0..21428e3347 100644 --- a/board/freescale/corenet_ds/corenet_ds.c +++ b/board/freescale/corenet_ds/corenet_ds.c @@ -45,6 +45,7 @@ int checkboard (void) struct cpu_type *cpu = gd->cpu; ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; unsigned int i; + static const char * const freq[] = {"100", "125", "156.25", "212.5" }; printf("Board: %sDS, ", cpu->name); printf("Sys ID: 0x%02x, Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ", @@ -83,20 +84,28 @@ int checkboard (void) * don't match. */ puts("SERDES Reference Clocks: "); -#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) +#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \ + || defined(CONFIG_P5040DS) sw = in_8(&PIXIS_SW(5)); for (i = 0; i < 3; i++) { - static const char *freq[] = {"100", "125", "156.25", "212.5" }; unsigned int clock = (sw >> (6 - (2 * i))) & 3; printf("Bank%u=%sMhz ", i+1, freq[clock]); } +#ifdef CONFIG_P5040DS + /* On P5040DS, SW11[7:8] determines the Bank 4 frequency */ + sw = in_8(&PIXIS_SW(9)); + printf("Bank4=%sMhz ", freq[sw & 3]); +#endif puts("\n"); #else sw = in_8(&PIXIS_SW(3)); - printf("Bank1=%uMHz ", (sw & 0x40) ? 125 : 100); - printf("Bank2=%sMHz ", (sw & 0x20) ? "156.25" : "125"); - printf("Bank3=%sMHz\n", (sw & 0x10) ? "156.25" : "125"); + /* SW3[2]: 0 = 100 Mhz, 1 = 125 MHz */ + /* SW3[3]: 0 = 125 Mhz, 1 = 156.25 MHz */ + /* SW3[4]: 0 = 125 Mhz, 1 = 156.25 MHz */ + printf("Bank1=%sMHz ", freq[!!(sw & 0x40)]); + printf("Bank2=%sMHz ", freq[1 + !!(sw & 0x20)]); + printf("Bank3=%sMHz\n", freq[1 + !!(sw & 0x10)]); #endif return 0; @@ -168,7 +177,8 @@ int misc_init_r(void) unsigned int i; u8 sw; -#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) +#if defined(CONFIG_P3041DS) || defined(CONFIG_P5020DS) \ + || defined(CONFIG_P5040DS) sw = in_8(&PIXIS_SW(5)); for (i = 0; i < 3; i++) { unsigned int clock = (sw >> (6 - (2 * i))) & 3; diff --git a/board/freescale/corenet_ds/ddr.c b/board/freescale/corenet_ds/ddr.c index 4a53b8d933..da284cde95 100644 --- a/board/freescale/corenet_ds/ddr.c +++ b/board/freescale/corenet_ds/ddr.c @@ -139,8 +139,8 @@ static const struct board_specific_parameters udimm0[] = { {2, 1250, 4, 6, 0xff, 2, 0}, {2, 1350, 5, 7, 0xff, 2, 0}, {2, 1666, 5, 8, 0xff, 2, 0}, - {1, 850, 4, 5, 0xff, 2, 0}, - {1, 950, 4, 7, 0xff, 2, 0}, + {1, 1250, 4, 6, 0xff, 2, 0}, + {1, 1335, 4, 7, 0xff, 2, 0}, {1, 1666, 4, 8, 0xff, 2, 0}, {} }; diff --git a/board/freescale/corenet_ds/eth_superhydra.c b/board/freescale/corenet_ds/eth_superhydra.c new file mode 100644 index 0000000000..ef9de25bd8 --- /dev/null +++ b/board/freescale/corenet_ds/eth_superhydra.c @@ -0,0 +1,722 @@ +/* + * Copyright 2009-2011 Freescale Semiconductor, Inc. + * Author: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * This file handles the board muxing between the Fman Ethernet MACs and + * the RGMII/SGMII/XGMII PHYs on a Freescale P5040 "Super Hydra" reference + * board. The RGMII PHYs are the two on-board 1Gb ports. The SGMII PHYs are + * provided by the standard Freescale four-port SGMII riser card. The 10Gb + * XGMII PHYs are provided via the XAUI riser card. The P5040 has 2 FMans + * and 5 1G interfaces and 10G interface per FMan. Based on the options in + * the RCW, we could have upto 3 SGMII cards and 1 XAUI card at a time. + * + * Muxing is handled via the PIXIS BRDCFG1 register. The EMI1 bits control + * muxing among the RGMII PHYs and the SGMII PHYs. The value for RGMII is + * always the same (0). The value for SGMII depends on which slot the riser is + * inserted in. The EMI2 bits control muxing for the the XGMII. Like SGMII, + * the value is based on which slot the XAUI is inserted in. + * + * The SERDES configuration is used to determine where the SGMII and XAUI cards + * exist, and also which Fman's MACs are routed to which PHYs. So for a given + * Fman MAC, there is one and only PHY it connects to. MACs cannot be routed + * to PHYs dynamically. + * + * + * This file also updates the device tree in three ways: + * + * 1) The status of each virtual MDIO node that is referenced by an Ethernet + * node is set to "okay". + * + * 2) The phy-handle property of each active Ethernet MAC node is set to the + * appropriate PHY node. + * + * 3) The "mux value" for each virtual MDIO node is set to the correct value, + * if necessary. Some virtual MDIO nodes do not have configurable mux + * values, so those values are hard-coded in the DTS. On the HYDRA board, + * the virtual MDIO node for the SGMII card needs to be updated. + * + * For all this to work, the device tree needs to have the following: + * + * 1) An alias for each PHY node that an Ethernet node could be routed to. + * + * 2) An alias for each real and virtual MDIO node that is disabled by default + * and might need to be enabled, and also might need to have its mux-value + * updated. + */ + +#include <common.h> +#include <netdev.h> +#include <asm/fsl_serdes.h> +#include <fm_eth.h> +#include <fsl_mdio.h> +#include <malloc.h> +#include <fdt_support.h> +#include <asm/fsl_dtsec.h> + +#include "../common/ngpixis.h" +#include "../common/fman.h" + +#ifdef CONFIG_FMAN_ENET + +#define BRDCFG1_EMI1_SEL_MASK 0x70 +#define BRDCFG1_EMI1_SEL_SLOT1 0x10 +#define BRDCFG1_EMI1_SEL_SLOT2 0x20 +#define BRDCFG1_EMI1_SEL_SLOT5 0x30 +#define BRDCFG1_EMI1_SEL_SLOT6 0x40 +#define BRDCFG1_EMI1_SEL_SLOT7 0x50 +#define BRDCFG1_EMI1_SEL_SLOT3 0x60 +#define BRDCFG1_EMI1_SEL_RGMII 0x00 +#define BRDCFG1_EMI1_EN 0x08 +#define BRDCFG1_EMI2_SEL_MASK 0x06 +#define BRDCFG1_EMI2_SEL_SLOT1 0x00 +#define BRDCFG1_EMI2_SEL_SLOT2 0x02 + +#define BRDCFG2_REG_GPIO_SEL 0x20 + +/* + * BRDCFG1 mask and value for each MAC + * + * This array contains the BRDCFG1 values (in mask/val format) that route the + * MDIO bus to a particular RGMII or SGMII PHY. + */ +static struct { + u8 mask; + u8 val; +} mdio_mux[NUM_FM_PORTS]; + +/* + * Mapping of all 18 SERDES lanes to board slots. A value of '0' here means + * that the mapping must be determined dynamically, or that the lane maps to + * something other than a board slot + */ +static u8 lane_to_slot[] = { + 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 2, 2, 1, 1, 0, 0, 0, 0 +}; + +/* + * Set the board muxing for a given MAC + * + * The MDIO layer calls this function every time it wants to talk to a PHY. + */ +void super_hydra_mux_mdio(u8 mask, u8 val) +{ + clrsetbits_8(&pixis->brdcfg1, mask, val); +} + +struct super_hydra_mdio { + u8 mask; + u8 val; + struct mii_dev *realbus; +}; + +static int super_hydra_mdio_read(struct mii_dev *bus, int addr, int devad, + int regnum) +{ + struct super_hydra_mdio *priv = bus->priv; + + super_hydra_mux_mdio(priv->mask, priv->val); + + return priv->realbus->read(priv->realbus, addr, devad, regnum); +} + +static int super_hydra_mdio_write(struct mii_dev *bus, int addr, int devad, + int regnum, u16 value) +{ + struct super_hydra_mdio *priv = bus->priv; + + super_hydra_mux_mdio(priv->mask, priv->val); + + return priv->realbus->write(priv->realbus, addr, devad, regnum, value); +} + +static int super_hydra_mdio_reset(struct mii_dev *bus) +{ + struct super_hydra_mdio *priv = bus->priv; + + return priv->realbus->reset(priv->realbus); +} + +static void super_hydra_mdio_set_mux(char *name, u8 mask, u8 val) +{ + struct mii_dev *bus = miiphy_get_dev_by_name(name); + struct super_hydra_mdio *priv = bus->priv; + + priv->mask = mask; + priv->val = val; +} + +static int super_hydra_mdio_init(char *realbusname, char *fakebusname) +{ + struct super_hydra_mdio *hmdio; + struct mii_dev *bus = mdio_alloc(); + + if (!bus) { + printf("Failed to allocate Hydra MDIO bus\n"); + return -1; + } + + hmdio = malloc(sizeof(*hmdio)); + if (!hmdio) { + printf("Failed to allocate Hydra private data\n"); + free(bus); + return -1; + } + + bus->read = super_hydra_mdio_read; + bus->write = super_hydra_mdio_write; + bus->reset = super_hydra_mdio_reset; + sprintf(bus->name, fakebusname); + + hmdio->realbus = miiphy_get_dev_by_name(realbusname); + + if (!hmdio->realbus) { + printf("No bus with name %s\n", realbusname); + free(bus); + free(hmdio); + return -1; + } + + bus->priv = hmdio; + + return mdio_register(bus); +} + +/* + * Given the following ... + * + * 1) A pointer to an Fman Ethernet node (as identified by the 'compat' + * compatible string and 'addr' physical address) + * + * 2) An Fman port + * + * ... update the phy-handle property of the Ethernet node to point to the + * right PHY. This assumes that we already know the PHY for each port. That + * information is stored in mdio_mux[]. + * + * The offset of the Fman Ethernet node is also passed in for convenience, but + * it is not used. + * + * Note that what we call "Fman ports" (enum fm_port) is really an Fman MAC. + * Inside the Fman, "ports" are things that connect to MACs. We only call them + * ports in U-Boot because on previous Ethernet devices (e.g. Gianfar), MACs + * and ports are the same thing. + */ +void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, + enum fm_port port, int offset) +{ + enum srds_prtcl device; + int lane, slot, phy; + char alias[32]; + + /* RGMII and XGMII are already mapped correctly in the DTS */ + + if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) { + device = serdes_device_from_fm_port(port); + lane = serdes_get_first_lane(device); + slot = lane_to_slot[lane]; + phy = fm_info_get_phy_address(port); + + sprintf(alias, "phy_sgmii_slot%u_%x", slot, phy); + fdt_set_phy_handle(fdt, compat, addr, alias); + } +} + +#define PIXIS_SW2_LANE_23_SEL 0x80 +#define PIXIS_SW2_LANE_45_SEL 0x40 +#define PIXIS_SW2_LANE_67_SEL_MASK 0x30 +#define PIXIS_SW2_LANE_67_SEL_5 0x00 +#define PIXIS_SW2_LANE_67_SEL_6 0x20 +#define PIXIS_SW2_LANE_67_SEL_7 0x10 +#define PIXIS_SW2_LANE_8_SEL 0x08 +#define PIXIS_SW2_LANE_1617_SEL 0x04 +#define PIXIS_SW11_LANE_9_SEL 0x04 +/* + * Initialize the lane_to_slot[] array. + * + * On the P4080DS "Expedition" board, the mapping of SERDES lanes to board + * slots is hard-coded. On the Hydra board, however, the mapping is controlled + * by board switch SW2, so the lane_to_slot[] array needs to be dynamically + * initialized. + */ +static void initialize_lane_to_slot(void) +{ + u8 sw2 = in_8(&PIXIS_SW(2)); + /* SW11 appears in the programming model as SW9 */ + u8 sw11 = in_8(&PIXIS_SW(9)); + + lane_to_slot[2] = (sw2 & PIXIS_SW2_LANE_23_SEL) ? 7 : 4; + lane_to_slot[3] = lane_to_slot[2]; + + lane_to_slot[4] = (sw2 & PIXIS_SW2_LANE_45_SEL) ? 7 : 6; + lane_to_slot[5] = lane_to_slot[4]; + + switch (sw2 & PIXIS_SW2_LANE_67_SEL_MASK) { + case PIXIS_SW2_LANE_67_SEL_5: + lane_to_slot[6] = 5; + break; + case PIXIS_SW2_LANE_67_SEL_6: + lane_to_slot[6] = 6; + break; + case PIXIS_SW2_LANE_67_SEL_7: + lane_to_slot[6] = 7; + break; + } + lane_to_slot[7] = lane_to_slot[6]; + + lane_to_slot[8] = (sw2 & PIXIS_SW2_LANE_8_SEL) ? 3 : 0; + lane_to_slot[9] = (sw11 & PIXIS_SW11_LANE_9_SEL) ? 0 : 3; + + lane_to_slot[16] = (sw2 & PIXIS_SW2_LANE_1617_SEL) ? 1 : 0; + lane_to_slot[17] = lane_to_slot[16]; +} + +#endif /* #ifdef CONFIG_FMAN_ENET */ + +/* + * Configure the status for the virtual MDIO nodes + * + * Rather than create the virtual MDIO nodes from scratch for each active + * virtual MDIO, we expect the DTS to have the nodes defined already, and we + * only enable the ones that are actually active. + * + * We assume that the DTS already hard-codes the status for all the + * virtual MDIO nodes to "disabled", so all we need to do is enable the + * active ones. + */ +void fdt_fixup_board_enet(void *fdt) +{ +#ifdef CONFIG_FMAN_ENET + enum fm_port i; + int lane, slot; + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + int idx = i - FM1_DTSEC1; + + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); + if (lane >= 0) { + char alias[32]; + + slot = lane_to_slot[lane]; + sprintf(alias, "hydra_sg_slot%u", slot); + fdt_status_okay_by_alias(fdt, alias); + debug("Enabled MDIO node %s (slot %i)\n", + alias, slot); + } + break; + case PHY_INTERFACE_MODE_RGMII: + fdt_status_okay_by_alias(fdt, "hydra_rg"); + debug("Enabled MDIO node hydra_rg\n"); + break; + default: + break; + } + } + + lane = serdes_get_first_lane(XAUI_FM1); + if (lane >= 0) { + char alias[32]; + + slot = lane_to_slot[lane]; + sprintf(alias, "hydra_xg_slot%u", slot); + fdt_status_okay_by_alias(fdt, alias); + debug("Enabled MDIO node %s (slot %i)\n", alias, slot); + } + +#if CONFIG_SYS_NUM_FMAN == 2 + for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { + int idx = i - FM2_DTSEC1; + + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); + if (lane >= 0) { + char alias[32]; + + slot = lane_to_slot[lane]; + sprintf(alias, "hydra_sg_slot%u", slot); + fdt_status_okay_by_alias(fdt, alias); + debug("Enabled MDIO node %s (slot %i)\n", + alias, slot); + } + break; + case PHY_INTERFACE_MODE_RGMII: + fdt_status_okay_by_alias(fdt, "hydra_rg"); + debug("Enabled MDIO node hydra_rg\n"); + break; + default: + break; + } + } + + lane = serdes_get_first_lane(XAUI_FM2); + if (lane >= 0) { + char alias[32]; + + slot = lane_to_slot[lane]; + sprintf(alias, "hydra_xg_slot%u", slot); + fdt_status_okay_by_alias(fdt, alias); + debug("Enabled MDIO node %s (slot %i)\n", alias, slot); + } +#endif /* CONFIG_SYS_NUM_FMAN == 2 */ +#endif /* CONFIG_FMAN_ENET */ +} + +/* + * Mapping of SerDes Protocol to MDIO MUX value and PHY address. + * + * Fman 1: + * DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4 + * Mux Phy | Mux Phy | Mux Phy | Mux Phy + * Value Addr | Value Addr | Value Addr | Value Addr + * 0x00 2 1c | 2 1d | 2 1e | 2 1f + * 0x01 | | 6 1c | + * 0x02 | | 3 1c | 3 1d + * 0x03 2 1c | 2 1d | 2 1e | 2 1f + * 0x04 2 1c | 2 1d | 2 1e | 2 1f + * 0x05 | | 3 1c | 3 1d + * 0x06 2 1c | 2 1d | 2 1e | 2 1f + * 0x07 | | 6 1c | + * 0x11 2 1c | 2 1d | 2 1e | 2 1f + * 0x2a 2 | | 2 1e | 2 1f + * 0x34 6 1c | 6 1d | 4 1e | 4 1f + * 0x35 | | 3 1c | 3 1d + * 0x36 6 1c | 6 1d | 4 1e | 4 1f + * | | | + * Fman 2: | | | + * DTSEC1 | DTSEC2 | DTSEC3 | DTSEC4 + * EMI1 | EMI1 | EMI1 | EMI1 + * Mux Phy | Mux Phy | Mux Phy | Mux Phy + * Value Addr | Value Addr | Value Addr | Value Addr + * 0x00 | | 6 1c | 6 1d + * 0x01 | | | + * 0x02 | | 6 1c | 6 1d + * 0x03 3 1c | 3 1d | 6 1c | 6 1d + * 0x04 3 1c | 3 1d | 6 1c | 6 1d + * 0x05 | | 6 1c | 6 1d + * 0x06 | | 6 1c | 6 1d + * 0x07 | | | + * 0x11 | | | + * 0x2a | | | + * 0x34 | | | + * 0x35 | | | + * 0x36 | | | + */ + +int board_eth_init(bd_t *bis) +{ +#ifdef CONFIG_FMAN_ENET + struct fsl_pq_mdio_info dtsec_mdio_info; + struct tgec_mdio_info tgec_mdio_info; + unsigned int i, slot; + int lane; + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + int srds_prtcl = (in_be32(&gur->rcwsr[4]) & + FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; + + printf("Initializing Fman\n"); + + initialize_lane_to_slot(); + + /* We want to use the PIXIS to configure MUX routing, not GPIOs. */ + setbits_8(&pixis->brdcfg2, BRDCFG2_REG_GPIO_SEL); + + memset(mdio_mux, 0, sizeof(mdio_mux)); + + dtsec_mdio_info.regs = + (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR; + dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME; + + /* Register the real 1G MDIO bus */ + fsl_pq_mdio_init(bis, &dtsec_mdio_info); + + tgec_mdio_info.regs = + (struct tgec_mdio_controller *)CONFIG_SYS_FM1_TGEC_MDIO_ADDR; + tgec_mdio_info.name = DEFAULT_FM_TGEC_MDIO_NAME; + + /* Register the real 10G MDIO bus */ + fm_tgec_mdio_init(bis, &tgec_mdio_info); + + /* Register the three virtual MDIO front-ends */ + super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, + "SUPER_HYDRA_RGMII_MDIO"); + super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, + "SUPER_HYDRA_FM1_SGMII_MDIO"); + super_hydra_mdio_init(DEFAULT_FM_MDIO_NAME, + "SUPER_HYDRA_FM2_SGMII_MDIO"); + super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, + "SUPER_HYDRA_FM1_TGEC_MDIO"); + super_hydra_mdio_init(DEFAULT_FM_TGEC_MDIO_NAME, + "SUPER_HYDRA_FM2_TGEC_MDIO"); + + /* + * Program the DTSEC PHY addresses assuming that they are all SGMII. + * For any DTSEC that's RGMII, we'll override its PHY address later. + * We assume that DTSEC5 is only used for RGMII. + */ + fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); + fm_info_set_phy_address(FM1_10GEC1, CONFIG_SYS_FM2_10GEC1_PHY_ADDR); + +#if (CONFIG_SYS_NUM_FMAN == 2) + fm_info_set_phy_address(FM2_DTSEC1, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC2, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC3, CONFIG_SYS_FM2_DTSEC1_PHY_ADDR); + fm_info_set_phy_address(FM2_DTSEC4, CONFIG_SYS_FM2_DTSEC2_PHY_ADDR); + fm_info_set_phy_address(FM2_10GEC1, CONFIG_SYS_FM1_10GEC1_PHY_ADDR); +#endif + + switch (srds_prtcl) { + case 0: + case 3: + case 4: + case 6: + case 0x11: + case 0x2a: + case 0x34: + case 0x36: + fm_info_set_phy_address(FM1_DTSEC3, + CONFIG_SYS_FM1_DTSEC3_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, + CONFIG_SYS_FM1_DTSEC4_PHY_ADDR); + break; + case 1: + case 2: + case 5: + case 7: + case 0x35: + fm_info_set_phy_address(FM1_DTSEC3, + CONFIG_SYS_FM1_DTSEC1_PHY_ADDR); + fm_info_set_phy_address(FM1_DTSEC4, + CONFIG_SYS_FM1_DTSEC2_PHY_ADDR); + break; + default: + printf("Fman: Unsupport SerDes Protocol 0x%02x\n", srds_prtcl); + break; + } + + for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) { + int idx = i - FM1_DTSEC1; + + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM1_DTSEC1 + idx); + if (lane < 0) + break; + slot = lane_to_slot[lane]; + mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; + debug("FM1@DTSEC%u expects SGMII in slot %u\n", + idx + 1, slot); + switch (slot) { + case 1: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | + BRDCFG1_EMI1_EN; + break; + case 2: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | + BRDCFG1_EMI1_EN; + break; + case 3: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 | + BRDCFG1_EMI1_EN; + break; + case 5: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | + BRDCFG1_EMI1_EN; + break; + case 6: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | + BRDCFG1_EMI1_EN; + break; + case 7: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | + BRDCFG1_EMI1_EN; + break; + }; + + super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_SGMII_MDIO", + mdio_mux[i].mask, mdio_mux[i].val); + fm_info_set_mdio(i, + miiphy_get_dev_by_name("SUPER_HYDRA_FM1_SGMII_MDIO")); + break; + case PHY_INTERFACE_MODE_RGMII: + /* + * FM1 DTSEC5 is routed via EC1 to the first on-board + * RGMII port. FM2 DTSEC5 is routed via EC2 to the + * second on-board RGMII port. The other DTSECs cannot + * be routed to RGMII. + */ + debug("FM1@DTSEC%u is RGMII at address %u\n", + idx + 1, 0); + fm_info_set_phy_address(i, 0); + mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; + mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | + BRDCFG1_EMI1_EN; + super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO", + mdio_mux[i].mask, mdio_mux[i].val); + fm_info_set_mdio(i, + miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO")); + break; + case PHY_INTERFACE_MODE_NONE: + fm_info_set_phy_address(i, 0); + break; + default: + printf("Fman1: DTSEC%u set to unknown interface %i\n", + idx + 1, fm_info_get_enet_if(i)); + fm_info_set_phy_address(i, 0); + break; + } + } + + /* + * For 10G, we only support one XAUI card per Fman. If present, then we + * force its routing and never touch those bits again, which removes the + * need for Linux to do any muxing. This works because of the way + * BRDCFG1 is defined, but it's a bit hackish. + * + * The PHY address for the XAUI card depends on which slot it's in. The + * macros we use imply that the PHY address is based on which FM, but + * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, + * and FM2 could only use a XAUI in slot 4. On the Hydra board, we + * check the actual slot and just use the macros as-is, even though + * the P3041 and P5020 only have one Fman. + */ + lane = serdes_get_first_lane(XAUI_FM1); + if (lane >= 0) { + debug("FM1@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]); + mdio_mux[FM1_10GEC1].mask = BRDCFG1_EMI2_SEL_MASK; + mdio_mux[FM1_10GEC1].val = BRDCFG1_EMI2_SEL_SLOT2; + super_hydra_mdio_set_mux("SUPER_HYDRA_FM1_TGEC_MDIO", + mdio_mux[i].mask, mdio_mux[i].val); + } + + fm_info_set_mdio(FM1_10GEC1, + miiphy_get_dev_by_name("SUPER_HYDRA_FM1_TGEC_MDIO")); + +#if (CONFIG_SYS_NUM_FMAN == 2) + for (i = FM2_DTSEC1; i < FM2_DTSEC1 + CONFIG_SYS_NUM_FM2_DTSEC; i++) { + int idx = i - FM2_DTSEC1; + + switch (fm_info_get_enet_if(i)) { + case PHY_INTERFACE_MODE_SGMII: + lane = serdes_get_first_lane(SGMII_FM2_DTSEC1 + idx); + if (lane < 0) + break; + slot = lane_to_slot[lane]; + mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; + debug("FM2@DTSEC%u expects SGMII in slot %u\n", + idx + 1, slot); + switch (slot) { + case 1: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT1 | + BRDCFG1_EMI1_EN; + break; + case 2: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT2 | + BRDCFG1_EMI1_EN; + break; + case 3: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT3 | + BRDCFG1_EMI1_EN; + break; + case 5: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT5 | + BRDCFG1_EMI1_EN; + break; + case 6: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT6 | + BRDCFG1_EMI1_EN; + break; + case 7: + mdio_mux[i].val = BRDCFG1_EMI1_SEL_SLOT7 | + BRDCFG1_EMI1_EN; + break; + }; + + super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_SGMII_MDIO", + mdio_mux[i].mask, mdio_mux[i].val); + fm_info_set_mdio(i, + miiphy_get_dev_by_name("SUPER_HYDRA_FM2_SGMII_MDIO")); + break; + case PHY_INTERFACE_MODE_RGMII: + /* + * FM1 DTSEC5 is routed via EC1 to the first on-board + * RGMII port. FM2 DTSEC5 is routed via EC2 to the + * second on-board RGMII port. The other DTSECs cannot + * be routed to RGMII. + */ + debug("FM2@DTSEC%u is RGMII at address %u\n", + idx + 1, 1); + fm_info_set_phy_address(i, 1); + mdio_mux[i].mask = BRDCFG1_EMI1_SEL_MASK; + mdio_mux[i].val = BRDCFG1_EMI1_SEL_RGMII | + BRDCFG1_EMI1_EN; + super_hydra_mdio_set_mux("SUPER_HYDRA_RGMII_MDIO", + mdio_mux[i].mask, mdio_mux[i].val); + fm_info_set_mdio(i, + miiphy_get_dev_by_name("SUPER_HYDRA_RGMII_MDIO")); + break; + case PHY_INTERFACE_MODE_NONE: + fm_info_set_phy_address(i, 0); + break; + default: + printf("Fman2: DTSEC%u set to unknown interface %i\n", + idx + 1, fm_info_get_enet_if(i)); + fm_info_set_phy_address(i, 0); + break; + } + } + + /* + * For 10G, we only support one XAUI card per Fman. If present, then we + * force its routing and never touch those bits again, which removes the + * need for Linux to do any muxing. This works because of the way + * BRDCFG1 is defined, but it's a bit hackish. + * + * The PHY address for the XAUI card depends on which slot it's in. The + * macros we use imply that the PHY address is based on which FM, but + * that's not true. On the P4080DS, FM1 could only use XAUI in slot 5, + * and FM2 could only use a XAUI in slot 4. On the Hydra board, we + * check the actual slot and just use the macros as-is, even though + * the P3041 and P5020 only have one Fman. + */ + lane = serdes_get_first_lane(XAUI_FM2); + if (lane >= 0) { + debug("FM2@TGEC1 expects XAUI in slot %u\n", lane_to_slot[lane]); + mdio_mux[FM2_10GEC1].mask = BRDCFG1_EMI2_SEL_MASK; + mdio_mux[FM2_10GEC1].val = BRDCFG1_EMI2_SEL_SLOT1; + super_hydra_mdio_set_mux("SUPER_HYDRA_FM2_TGEC_MDIO", + mdio_mux[i].mask, mdio_mux[i].val); + } + + fm_info_set_mdio(FM2_10GEC1, + miiphy_get_dev_by_name("SUPER_HYDRA_FM2_TGEC_MDIO")); + +#endif + + cpu_eth_init(bis); +#endif + + return pci_eth_init(bis); +} diff --git a/board/freescale/corenet_ds/p5040ds_ddr.c b/board/freescale/corenet_ds/p5040ds_ddr.c new file mode 100644 index 0000000000..e65de364d7 --- /dev/null +++ b/board/freescale/corenet_ds/p5040ds_ddr.c @@ -0,0 +1,18 @@ +/* + * Copyright 2009-2010 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * Version 2 as published by the Free Software Foundation. + */ + +#include <common.h> +#include <asm/fsl_ddr_sdram.h> + +fixed_ddr_parm_t fixed_ddr_parm_0[] = { + {0, 0, NULL} +}; + +fixed_ddr_parm_t fixed_ddr_parm_1[] = { + {0, 0, NULL} +}; diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c index a275d3a074..418c06b655 100644 --- a/board/freescale/mpc8540ads/mpc8540ads.c +++ b/board/freescale/mpc8540ads/mpc8540ads.c @@ -184,7 +184,7 @@ void lbc_sdram_init(void) phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT - volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); + volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR); ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index 285edbce6b..a4f48bb234 100644 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -389,7 +389,7 @@ void lbc_sdram_init(void) phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT - volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); + volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR); ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index d119c6517f..0d3b418625 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -247,7 +247,7 @@ int checkboard (void) #if !defined(CONFIG_SPD_EEPROM) phys_size_t fixed_sdram(void) { - volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; + volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; uint d_init; out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); diff --git a/board/freescale/mx31pdk/mx31pdk.c b/board/freescale/mx31pdk/mx31pdk.c index 9f8bc53e71..bc60632aa0 100644 --- a/board/freescale/mx31pdk/mx31pdk.c +++ b/board/freescale/mx31pdk/mx31pdk.c @@ -30,8 +30,9 @@ #include <asm/arch/imx-regs.h> #include <asm/arch/sys_proto.h> #include <watchdog.h> -#include <pmic.h> +#include <power/pmic.h> #include <fsl_pmic.h> +#include <errno.h> DECLARE_GLOBAL_DATA_PTR; @@ -83,10 +84,15 @@ int board_late_init(void) { u32 val; struct pmic *p; + int ret; - pmic_init(); - p = get_pmic(); + ret = pmic_init(I2C_PMIC); + if (ret) + return ret; + p = pmic_get("FSL_PMIC"); + if (!p) + return -ENODEV; /* Enable RTC battery */ pmic_reg_read(p, REG_POWER_CTL0, &val); pmic_reg_write(p, REG_POWER_CTL0, val | COINCHEN); diff --git a/board/freescale/mx35pdk/mx35pdk.c b/board/freescale/mx35pdk/mx35pdk.c index 4d8f2f5eea..2aa000f238 100644 --- a/board/freescale/mx35pdk/mx35pdk.c +++ b/board/freescale/mx35pdk/mx35pdk.c @@ -31,7 +31,7 @@ #include <asm/arch/mx35_pins.h> #include <asm/arch/iomux.h> #include <i2c.h> -#include <pmic.h> +#include <power/pmic.h> #include <fsl_pmic.h> #include <mmc.h> #include <fsl_esdhc.h> @@ -228,7 +228,9 @@ int board_init(void) static inline int pmic_detect(void) { unsigned int id; - struct pmic *p = get_pmic(); + struct pmic *p = pmic_get("FSL_PMIC"); + if (!p) + return -ENODEV; pmic_reg_read(p, REG_IDENTIFICATION, &id); @@ -252,10 +254,14 @@ int board_late_init(void) u8 val; u32 pmic_val; struct pmic *p; + int ret; + + ret = pmic_init(I2C_PMIC); + if (ret) + return ret; - pmic_init(); if (pmic_detect()) { - p = get_pmic(); + p = pmic_get("FSL_PMIC"); mxc_request_iomux(MX35_PIN_WATCHDOG_RST, MUX_CONFIG_SION | MUX_CONFIG_ALT1); diff --git a/board/freescale/mx51evk/Makefile b/board/freescale/mx51evk/Makefile index 224eaa3c73..2310fe137d 100644 --- a/board/freescale/mx51evk/Makefile +++ b/board/freescale/mx51evk/Makefile @@ -23,8 +23,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS := mx51evk.o +COBJS-y += mx51evk.o +COBJS-$(CONFIG_VIDEO) += mx51evk_video.o +COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/mx51evk/mx51evk.c b/board/freescale/mx51evk/mx51evk.c index 421d8c2244..d1ef431895 100644 --- a/board/freescale/mx51evk/mx51evk.c +++ b/board/freescale/mx51evk/mx51evk.c @@ -30,19 +30,14 @@ #include <asm/arch/sys_proto.h> #include <asm/arch/crm_regs.h> #include <asm/arch/clock.h> +#include <asm/imx-common/mx5_video.h> #include <i2c.h> #include <mmc.h> #include <fsl_esdhc.h> -#include <pmic.h> +#include <power/pmic.h> #include <fsl_pmic.h> #include <mc13892.h> #include <usb/ehci-fsl.h> -#include <linux/fb.h> -#include <ipu_pixfmt.h> - -#define MX51EVK_LCD_3V3 IMX_GPIO_NR(4, 9) -#define MX51EVK_LCD_5V IMX_GPIO_NR(4, 10) -#define MX51EVK_LCD_BACKLIGHT IMX_GPIO_NR(3, 4) DECLARE_GLOBAL_DATA_PTR; @@ -252,9 +247,15 @@ static void power_init(void) unsigned int val; struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; struct pmic *p; + int ret; + + ret = pmic_init(I2C_PMIC); + if (ret) + return; - pmic_init(); - p = get_pmic(); + p = pmic_get("FSL_PMIC"); + if (!p) + return; /* Write needed to Power Gate 2 register */ pmic_reg_read(p, REG_POWER_MISC, &val); @@ -471,54 +472,6 @@ int board_mmc_init(bd_t *bis) } #endif -static struct fb_videomode const claa_wvga = { - .name = "CLAA07LC0ACW", - .refresh = 57, - .xres = 800, - .yres = 480, - .pixclock = 37037, - .left_margin = 40, - .right_margin = 60, - .upper_margin = 10, - .lower_margin = 10, - .hsync_len = 20, - .vsync_len = 10, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED -}; - -void lcd_iomux(void) -{ - /* DI2_PIN15 */ - mxc_request_iomux(MX51_PIN_DI_GP4, IOMUX_CONFIG_ALT4); - - /* Pad settings for MX51_PIN_DI2_DISP_CLK */ - mxc_iomux_set_pad(MX51_PIN_DI2_DISP_CLK, PAD_CTL_HYS_NONE | - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_MAX | PAD_CTL_SRE_SLOW); - - /* Turn on 3.3V voltage for LCD */ - mxc_request_iomux(MX51_PIN_CSI2_D12, IOMUX_CONFIG_ALT3); - gpio_direction_output(MX51EVK_LCD_3V3, 1); - - /* Turn on 5V voltage for LCD */ - mxc_request_iomux(MX51_PIN_CSI2_D13, IOMUX_CONFIG_ALT3); - gpio_direction_output(MX51EVK_LCD_5V, 1); - - /* Turn on GPIO backlight */ - mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4); - mxc_iomux_set_input(MX51_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT, - INPUT_CTL_PATH1); - gpio_direction_output(MX51EVK_LCD_BACKLIGHT, 1); -} - -void lcd_enable(void) -{ - int ret = ipuv3_fb_init(&claa_wvga, 1, IPU_PIX_FMT_RGB565); - if (ret) - printf("LCD cannot be configured: %d\n", ret); -} - int board_early_init_f(void) { setup_iomux_uart(); @@ -526,7 +479,7 @@ int board_early_init_f(void) #ifdef CONFIG_USB_EHCI_MX5 setup_usb_h1(); #endif - lcd_iomux(); + setup_iomux_lcd(); return 0; } diff --git a/board/freescale/mx51evk/mx51evk_video.c b/board/freescale/mx51evk/mx51evk_video.c new file mode 100644 index 0000000000..f036cf73b2 --- /dev/null +++ b/board/freescale/mx51evk/mx51evk_video.c @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Fabio Estevam <fabio.estevam@freescale.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <linux/list.h> +#include <asm/gpio.h> +#include <asm/arch/iomux.h> +#include <linux/fb.h> +#include <ipu_pixfmt.h> + +#define MX51EVK_LCD_3V3 IMX_GPIO_NR(4, 9) +#define MX51EVK_LCD_5V IMX_GPIO_NR(4, 10) +#define MX51EVK_LCD_BACKLIGHT IMX_GPIO_NR(3, 4) + +static struct fb_videomode const claa_wvga = { + .name = "CLAA07LC0ACW", + .refresh = 57, + .xres = 800, + .yres = 480, + .pixclock = 37037, + .left_margin = 40, + .right_margin = 60, + .upper_margin = 10, + .lower_margin = 10, + .hsync_len = 20, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +}; + +void setup_iomux_lcd(void) +{ + /* DI2_PIN15 */ + mxc_request_iomux(MX51_PIN_DI_GP4, IOMUX_CONFIG_ALT4); + + /* Pad settings for MX51_PIN_DI2_DISP_CLK */ + mxc_iomux_set_pad(MX51_PIN_DI2_DISP_CLK, PAD_CTL_HYS_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_MAX | PAD_CTL_SRE_SLOW); + + /* Turn on 3.3V voltage for LCD */ + mxc_request_iomux(MX51_PIN_CSI2_D12, IOMUX_CONFIG_ALT3); + gpio_direction_output(MX51EVK_LCD_3V3, 1); + + /* Turn on 5V voltage for LCD */ + mxc_request_iomux(MX51_PIN_CSI2_D13, IOMUX_CONFIG_ALT3); + gpio_direction_output(MX51EVK_LCD_5V, 1); + + /* Turn on GPIO backlight */ + mxc_request_iomux(MX51_PIN_DI1_D1_CS, IOMUX_CONFIG_ALT4); + mxc_iomux_set_input(MX51_GPIO3_IPP_IND_G_IN_4_SELECT_INPUT, + INPUT_CTL_PATH1); + gpio_direction_output(MX51EVK_LCD_BACKLIGHT, 1); +} + +void lcd_enable(void) +{ + int ret = ipuv3_fb_init(&claa_wvga, 1, IPU_PIX_FMT_RGB565); + if (ret) + printf("LCD cannot be configured: %d\n", ret); +} diff --git a/board/freescale/mx53evk/mx53evk.c b/board/freescale/mx53evk/mx53evk.c index bb4621d62e..1273501476 100644 --- a/board/freescale/mx53evk/mx53evk.c +++ b/board/freescale/mx53evk/mx53evk.c @@ -34,7 +34,7 @@ #include <i2c.h> #include <mmc.h> #include <fsl_esdhc.h> -#include <pmic.h> +#include <power/pmic.h> #include <fsl_pmic.h> #include <asm/gpio.h> #include <mc13892.h> @@ -123,9 +123,15 @@ void power_init(void) { unsigned int val; struct pmic *p; + int ret; + + ret = pmic_init(I2C_PMIC); + if (ret) + return; - pmic_init(); - p = get_pmic(); + p = pmic_get("FSL_PMIC"); + if (!p) + return; /* Set VDDA to 1.25V */ pmic_reg_read(p, REG_SW_2, &val); diff --git a/board/freescale/mx53loco/Makefile b/board/freescale/mx53loco/Makefile index 8bc69a92c1..3be17c5917 100644 --- a/board/freescale/mx53loco/Makefile +++ b/board/freescale/mx53loco/Makefile @@ -22,8 +22,10 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o -COBJS := mx53loco.o +COBJS-y += mx53loco.o +COBJS-$(CONFIG_VIDEO) += mx53loco_video.o +COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index a11e883186..81c511cdc1 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -31,12 +31,13 @@ #include <asm/arch/iomux.h> #include <asm/arch/clock.h> #include <asm/errno.h> +#include <asm/imx-common/mx5_video.h> #include <netdev.h> #include <i2c.h> #include <mmc.h> #include <fsl_esdhc.h> #include <asm/gpio.h> -#include <pmic.h> +#include <power/pmic.h> #include <dialog_pmic.h> #include <fsl_pmic.h> #include <linux/fb.h> @@ -344,10 +345,16 @@ static int power_init(void) unsigned int val; int ret = -1; struct pmic *p; + int retval; if (!i2c_probe(CONFIG_SYS_DIALOG_PMIC_I2C_ADDR)) { - pmic_dialog_init(); - p = get_pmic(); + retval = pmic_dialog_init(I2C_PMIC); + if (retval) + return retval; + + p = pmic_get("DIALOG_PMIC"); + if (!p) + return -ENODEV; /* Set VDDA to 1.25V */ val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V; @@ -363,8 +370,13 @@ static int power_init(void) } if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) { - pmic_init(); - p = get_pmic(); + retval = pmic_init(I2C_PMIC); + if (retval) + return retval; + + p = pmic_get("DIALOG_PMIC"); + if (!p) + return -ENODEV; /* Set VDDGP to 1.25V for 1GHz on SW1 */ pmic_reg_read(p, REG_SW_0, &val); @@ -412,74 +424,11 @@ static void clock_1GHz(void) printf("CPU: Switch DDR clock to 400MHz failed\n"); } -static struct fb_videomode const claa_wvga = { - .name = "CLAA07LC0ACW", - .refresh = 57, - .xres = 800, - .yres = 480, - .pixclock = 37037, - .left_margin = 40, - .right_margin = 60, - .upper_margin = 10, - .lower_margin = 10, - .hsync_len = 20, - .vsync_len = 10, - .sync = 0, - .vmode = FB_VMODE_NONINTERLACED -}; - -void lcd_iomux(void) -{ - mxc_request_iomux(MX53_PIN_DI0_DISP_CLK, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DI0_PIN15, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DI0_PIN2, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DI0_PIN3, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT0, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT1, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT2, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT3, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT4, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT5, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT6, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT7, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT8, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT9, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT10, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT11, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT12, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT13, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT14, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT15, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT16, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT17, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT18, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT19, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT20, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT21, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT22, IOMUX_CONFIG_ALT0); - mxc_request_iomux(MX53_PIN_DISP0_DAT23, IOMUX_CONFIG_ALT0); - - /* Turn on GPIO backlight */ - mxc_request_iomux(MX53_PIN_EIM_D24, IOMUX_CONFIG_ALT1); - gpio_direction_output(MX53LOCO_LCD_POWER, 1); - - /* Turn on display contrast */ - mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1); - gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_1), 1); -} - -void lcd_enable(void) -{ - int ret = ipuv3_fb_init(&claa_wvga, 0, IPU_PIX_FMT_RGB565); - if (ret) - printf("LCD cannot be configured: %d\n", ret); -} - int board_early_init_f(void) { setup_iomux_uart(); setup_iomux_fec(); - lcd_iomux(); + setup_iomux_lcd(); return 0; } diff --git a/board/freescale/mx53loco/mx53loco_video.c b/board/freescale/mx53loco/mx53loco_video.c new file mode 100644 index 0000000000..69991e8511 --- /dev/null +++ b/board/freescale/mx53loco/mx53loco_video.c @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2012 Freescale Semiconductor, Inc. + * Fabio Estevam <fabio.estevam@freescale.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <linux/list.h> +#include <asm/gpio.h> +#include <asm/arch/iomux.h> +#include <linux/fb.h> +#include <ipu_pixfmt.h> + +#define MX53LOCO_LCD_POWER IMX_GPIO_NR(3, 24) + +static struct fb_videomode const claa_wvga = { + .name = "CLAA07LC0ACW", + .refresh = 57, + .xres = 800, + .yres = 480, + .pixclock = 37037, + .left_margin = 40, + .right_margin = 60, + .upper_margin = 10, + .lower_margin = 10, + .hsync_len = 20, + .vsync_len = 10, + .sync = 0, + .vmode = FB_VMODE_NONINTERLACED +}; + +void setup_iomux_lcd(void) +{ + mxc_request_iomux(MX53_PIN_DI0_DISP_CLK, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_DI0_PIN15, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_DI0_PIN2, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_DI0_PIN3, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_DISP0_DAT0, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_DISP0_DAT1, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_DISP0_DAT2, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_DISP0_DAT3, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_DISP0_DAT4, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_DISP0_DAT5, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_DISP0_DAT6, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_DISP0_DAT7, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_DISP0_DAT8, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_DISP0_DAT9, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_DISP0_DAT10, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_DISP0_DAT11, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_DISP0_DAT12, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_DISP0_DAT13, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_DISP0_DAT14, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_DISP0_DAT15, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_DISP0_DAT16, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_DISP0_DAT17, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_DISP0_DAT18, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_DISP0_DAT19, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_DISP0_DAT20, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_DISP0_DAT21, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_DISP0_DAT22, IOMUX_CONFIG_ALT0); + mxc_request_iomux(MX53_PIN_DISP0_DAT23, IOMUX_CONFIG_ALT0); + + /* Turn on GPIO backlight */ + mxc_request_iomux(MX53_PIN_EIM_D24, IOMUX_CONFIG_ALT1); + gpio_direction_output(MX53LOCO_LCD_POWER, 1); + + /* Turn on display contrast */ + mxc_request_iomux(MX53_PIN_GPIO_1, IOMUX_CONFIG_ALT1); + gpio_direction_output(IOMUX_TO_GPIO(MX53_PIN_GPIO_1), 1); +} + +void lcd_enable(void) +{ + int ret = ipuv3_fb_init(&claa_wvga, 0, IPU_PIX_FMT_RGB565); + if (ret) + printf("LCD cannot be configured: %d\n", ret); +} diff --git a/board/freescale/p1023rds/p1023rds.c b/board/freescale/p1023rds/p1023rds.c index eb11f3fe12..9110767a14 100644 --- a/board/freescale/p1023rds/p1023rds.c +++ b/board/freescale/p1023rds/p1023rds.c @@ -74,7 +74,7 @@ int checkboard(void) phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT - ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; + ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1); diff --git a/board/freescale/p1_p2_rdb_pc/Makefile b/board/freescale/p1_p2_rdb_pc/Makefile index 0dcf7d1ab1..5b45d72f51 100644 --- a/board/freescale/p1_p2_rdb_pc/Makefile +++ b/board/freescale/p1_p2_rdb_pc/Makefile @@ -24,11 +24,27 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).o +MINIMAL= + +ifdef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_INIT_MINIMAL +MINIMAL=y +endif +endif + +ifdef MINIMAL + +COBJS-y += spl_minimal.o tlb.o law.o + +else + COBJS-y += $(BOARD).o COBJS-y += ddr.o COBJS-y += law.o COBJS-y += tlb.o +endif + SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) OBJS := $(addprefix $(obj),$(COBJS-y)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/freescale/p1_p2_rdb_pc/ddr.c b/board/freescale/p1_p2_rdb_pc/ddr.c index 88ba56f457..9355536b35 100644 --- a/board/freescale/p1_p2_rdb_pc/ddr.c +++ b/board/freescale/p1_p2_rdb_pc/ddr.c @@ -206,6 +206,7 @@ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, } #endif /* CONFIG_SYS_DDR_RAW_TIMING */ +#ifdef CONFIG_SYS_DDR_CS0_BNDS /* Fixed sdram init -- doesn't use serial presence detect. */ phys_size_t fixed_sdram(void) { @@ -260,6 +261,7 @@ phys_size_t fixed_sdram(void) return ddr_size; } +#endif void fsl_ddr_board_options(memctl_options_t *popts, dimm_params_t *pdimm, diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c index 0da8300c6f..cb5e7b7c0c 100644 --- a/board/freescale/p1_p2_rdb_pc/law.c +++ b/board/freescale/p1_p2_rdb_pc/law.c @@ -32,7 +32,7 @@ struct law_entry law_table[] = { #endif SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC), #ifdef CONFIG_SYS_NAND_BASE_PHYS - SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC), #endif }; diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index aa39260ca7..5b5b86c822 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -177,7 +177,7 @@ void board_gpio_init(void) */ setbits_be32(&pgpio->gpdir, 0x02130000); -#ifndef CONFIG_SYS_RAMBOOT +#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SPL) /* init DDR3 reset signal */ setbits_be32(&pgpio->gpdir, 0x00200000); setbits_be32(&pgpio->gpodr, 0x00200000); diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c new file mode 100644 index 0000000000..09019e98af --- /dev/null +++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c @@ -0,0 +1,136 @@ +/* + * Copyright 2011 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <ns16550.h> +#include <asm/io.h> +#include <nand.h> +#include <linux/compiler.h> +#include <asm/fsl_law.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/global_data.h> + +DECLARE_GLOBAL_DATA_PTR; + +#ifndef CONFIG_SYS_INIT_L2_ADDR +/* + * Fixed sdram init -- doesn't use serial presence detect. + */ +static void sdram_init(void) +{ + ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; + + __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); + __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); +#if CONFIG_CHIP_SELECTS_PER_CTRL > 1 + __raw_writel(CONFIG_SYS_DDR_CS1_BNDS, &ddr->cs1_bnds); + __raw_writel(CONFIG_SYS_DDR_CS1_CONFIG, &ddr->cs1_config); +#endif + __raw_writel(CONFIG_SYS_DDR_TIMING_3, &ddr->timing_cfg_3); + __raw_writel(CONFIG_SYS_DDR_TIMING_0, &ddr->timing_cfg_0); + __raw_writel(CONFIG_SYS_DDR_TIMING_1, &ddr->timing_cfg_1); + __raw_writel(CONFIG_SYS_DDR_TIMING_2, &ddr->timing_cfg_2); + + __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); + __raw_writel(CONFIG_SYS_DDR_MODE_1, &ddr->sdram_mode); + __raw_writel(CONFIG_SYS_DDR_MODE_2, &ddr->sdram_mode_2); + + __raw_writel(CONFIG_SYS_DDR_INTERVAL, &ddr->sdram_interval); + __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); + __raw_writel(CONFIG_SYS_DDR_CLK_CTRL, &ddr->sdram_clk_cntl); + + __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); + __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); + __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); + __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL, &ddr->ddr_wrlvl_cntl); + + /* Set, but do not enable the memory */ + __raw_writel(CONFIG_SYS_DDR_CONTROL & ~SDRAM_CFG_MEM_EN, &ddr->sdram_cfg); + + asm volatile("sync;isync"); + udelay(500); + + /* Let the controller go */ + out_be32(&ddr->sdram_cfg, in_be32(&ddr->sdram_cfg) | SDRAM_CFG_MEM_EN); + + set_next_law(0, CONFIG_SYS_SDRAM_SIZE_LAW, LAW_TRGT_IF_DDR_1); +} +#endif + +void board_init_f(ulong bootflag) +{ + u32 plat_ratio; + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; +#ifndef CONFIG_QE + ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); +#endif + + /* initialize selected port with appropriate baud rate */ + plat_ratio = in_be32(&gur->porpllsr) & MPC85xx_PORPLLSR_PLAT_RATIO; + plat_ratio >>= 1; + gd->bus_clk = CONFIG_SYS_CLK_FREQ * plat_ratio; + + NS16550_init((NS16550_t)CONFIG_SYS_NS16550_COM1, + gd->bus_clk / 16 / CONFIG_BAUDRATE); + + puts("\nNAND boot... "); + +#ifndef CONFIG_QE + /* init DDR3 reset signal */ + __raw_writel(0x02000000, &pgpio->gpdir); + __raw_writel(0x00200000, &pgpio->gpodr); + __raw_writel(0x00000000, &pgpio->gpdat); + udelay(1000); + __raw_writel(0x00200000, &pgpio->gpdat); + udelay(1000); + __raw_writel(0x00000000, &pgpio->gpdir); +#endif + +#ifndef CONFIG_SYS_INIT_L2_ADDR + /* Initialize the DDR3 */ + sdram_init(); +#endif + + /* copy code to RAM and jump to it - this should not return */ + /* NOTE - code has to be copied out of NAND buffer before + * other blocks can be read. + */ + relocate_code(CONFIG_SPL_RELOC_STACK, 0, CONFIG_SPL_RELOC_TEXT_BASE); +} + +void board_init_r(gd_t *gd, ulong dest_addr) +{ + nand_boot(); +} + +void putc(char c) +{ + if (c == '\n') + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, '\r'); + + NS16550_putc((NS16550_t)CONFIG_SYS_NS16550_COM1, c); +} + +void puts(const char *str) +{ + while (*str) + putc(*str++); +} diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c index 6d2246387a..3e4dffd237 100644 --- a/board/freescale/p1_p2_rdb_pc/tlb.c +++ b/board/freescale/p1_p2_rdb_pc/tlb.c @@ -53,7 +53,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1), -#ifndef CONFIG_NAND_SPL +#ifndef CONFIG_SPL_BUILD /* W**G* - Flash/promjet, localbus */ /* This will be changed to *I*G* after relocation to RAM. */ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, @@ -85,7 +85,7 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_PMC_BASE, CONFIG_SYS_PMC_BASE_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 10, BOOKE_PAGESZ_64K, 1), -#endif +#endif /* not SPL */ #ifdef CONFIG_SYS_NAND_BASE /* *I*G - NAND */ @@ -94,7 +94,17 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 7, BOOKE_PAGESZ_1M, 1), #endif -#ifdef CONFIG_SYS_RAMBOOT +#if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL) +#ifdef CONFIG_SYS_INIT_L2_ADDR + /* L2SRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_256K, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000, + CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 12, BOOKE_PAGESZ_256K, 1), +#else /* *I*G - eSDHC/eSPI/NAND boot */ SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, @@ -106,9 +116,9 @@ struct fsl_e_tlb_entry tlb_table[] = { CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 9, BOOKE_PAGESZ_1G, 1), -#endif -#endif - +#endif /* P1020MBG */ +#endif /* not L2 SRAM */ +#endif /* RAMBOOT/SPL */ }; int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index 3188f59e4b..d4a445108a 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -84,7 +84,7 @@ int checkboard(void) phys_size_t fixed_sdram(void) { - volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; + volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; uint d_init; ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c index c2b2823ef9..69d41db530 100644 --- a/board/genesi/mx51_efikamx/efikamx.c +++ b/board/genesi/mx51_efikamx/efikamx.c @@ -33,7 +33,7 @@ #include <i2c.h> #include <mmc.h> #include <fsl_esdhc.h> -#include <pmic.h> +#include <power/pmic.h> #include <fsl_pmic.h> #include <mc13892.h> @@ -173,9 +173,15 @@ static void power_init(void) unsigned int val; struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; struct pmic *p; + int ret; + + ret = pmic_init(I2C_PMIC); + if (ret) + return; - pmic_init(); - p = get_pmic(); + p = pmic_get("FSL_PMIC"); + if (!p) + return; /* Write needed to Power Gate 2 register */ pmic_reg_read(p, REG_POWER_MISC, &val); diff --git a/board/hale/tt01/tt01.c b/board/hale/tt01/tt01.c index 143fcefedf..0c2cb795dd 100644 --- a/board/hale/tt01/tt01.c +++ b/board/hale/tt01/tt01.c @@ -25,12 +25,13 @@ #include <common.h> #include <netdev.h> #include <command.h> -#include <pmic.h> +#include <power/pmic.h> #include <fsl_pmic.h> #include <mc13783.h> #include <asm/arch/clock.h> #include <asm/arch/sys_proto.h> #include <asm/io.h> +#include <errno.h> DECLARE_GLOBAL_DATA_PTR; @@ -195,14 +196,21 @@ int board_mmc_init(bd_t *bis) { u32 val; struct pmic *p; + int ret; /* * this is the first driver to use the pmic, so call * pmic_init() here. board_late_init() is too late for * the MMC driver. */ - pmic_init(); - p = get_pmic(); + + ret = pmic_init(I2C_PMIC); + if (ret) + return ret; + + p = pmic_get("FSL_PMIC"); + if (!p) + return -ENODEV; /* configure pins for SDHC1 only */ mx31_gpio_mux(IOMUX_MODE(MUX_CTL_SD1_CLK, MUX_CTL_FUNC)); diff --git a/board/iomega/iconnect/iconnect.c b/board/iomega/iconnect/iconnect.c index 6ee2128aab..8cfb4e6620 100644 --- a/board/iomega/iconnect/iconnect.c +++ b/board/iomega/iconnect/iconnect.c @@ -1,7 +1,7 @@ /* * Copyright (C) 2009-2012 * Wojciech Dubowik <wojciech.dubowik@neratec.com> - * Luka Perkov <uboot@lukaperkov.net> + * Luka Perkov <luka@openwrt.org> * * See file CREDITS for list of people who contributed to this * project. diff --git a/board/iomega/iconnect/iconnect.h b/board/iomega/iconnect/iconnect.h index 2fb3e5ed8f..8b6fe1bcad 100644 --- a/board/iomega/iconnect/iconnect.h +++ b/board/iomega/iconnect/iconnect.h @@ -1,7 +1,7 @@ /* * Copyright (C) 2009-2012 * Wojciech Dubowik <wojciech.dubowik@neratec.com> - * Luka Perkov <uboot@lukaperkov.net> + * Luka Perkov <luka@openwrt.org> * * See file CREDITS for list of people who contributed to this * project. diff --git a/board/iomega/iconnect/kwbimage.cfg b/board/iomega/iconnect/kwbimage.cfg index 6c9dfe3d31..4b64dab592 100644 --- a/board/iomega/iconnect/kwbimage.cfg +++ b/board/iomega/iconnect/kwbimage.cfg @@ -1,7 +1,7 @@ # # (C) Copyright 2009-2012 # Wojciech Dubowik <wojciech.dubowik@neratec.com> -# Luka Perkov <uboot@lukaperkov.net> +# Luka Perkov <luka@openwrt.org> # # See file CREDITS for list of people who contributed to this # project. diff --git a/board/logicpd/am3517evm/am3517evm.c b/board/logicpd/am3517evm/am3517evm.c index d316f33cd1..0b3721ed85 100644 --- a/board/logicpd/am3517evm/am3517evm.c +++ b/board/logicpd/am3517evm/am3517evm.c @@ -25,12 +25,20 @@ #include <common.h> #include <asm/io.h> +#include <asm/omap_musb.h> +#include <asm/arch/am35x_def.h> #include <asm/arch/mem.h> #include <asm/arch/mux.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mmc_host_def.h> +#include <asm/arch/musb.h> #include <asm/mach-types.h> +#include <asm/errno.h> +#include <linux/usb/ch9.h> +#include <linux/usb/gadget.h> +#include <linux/usb/musb.h> #include <i2c.h> +#include <netdev.h> #include "am3517evm.h" DECLARE_GLOBAL_DATA_PTR; @@ -50,6 +58,52 @@ int board_init(void) return 0; } +#ifdef CONFIG_USB_MUSB_AM35X +static struct musb_hdrc_config musb_config = { + .multipoint = 1, + .dyn_fifo = 1, + .num_eps = 16, + .ram_bits = 12, +}; + +static struct omap_musb_board_data musb_board_data = { + .set_phy_power = am35x_musb_phy_power, + .clear_irq = am35x_musb_clear_irq, + .reset = am35x_musb_reset, +}; + +static struct musb_hdrc_platform_data musb_plat = { +#if defined(CONFIG_MUSB_HOST) + .mode = MUSB_HOST, +#elif defined(CONFIG_MUSB_GADGET) + .mode = MUSB_PERIPHERAL, +#else +#error "Please define either CONFIG_MUSB_HOST or CONFIG_MUSB_GADGET" +#endif + .config = &musb_config, + .power = 250, + .platform_ops = &am35x_ops, + .board_data = &musb_board_data, +}; + +static void am3517_evm_musb_init(void) +{ + /* + * Set up USB clock/mode in the DEVCONF2 register. + * USB2.0 PHY reference clock is 13 MHz + */ + clrsetbits_le32(&am35x_scm_general_regs->devconf2, + CONF2_REFFREQ | CONF2_OTGMODE | CONF2_PHY_GPIOMODE, + CONF2_REFFREQ_13MHZ | CONF2_SESENDEN | + CONF2_VBDTCTEN | CONF2_DATPOL); + + musb_register(&musb_plat, &musb_board_data, + (void *)AM35XX_IPSS_USBOTGSS_BASE); +} +#else +#define am3517_evm_musb_init() do {} while (0) +#endif + /* * Routine: misc_init_r * Description: Init i2c, ethernet, etc... (done here so udelay works) @@ -62,6 +116,8 @@ int misc_init_r(void) dieid_num_r(); + am3517_evm_musb_init(); + return 0; } @@ -83,3 +139,21 @@ int board_mmc_init(bd_t *bis) return 0; } #endif + +#if defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET) +int board_eth_init(bd_t *bis) +{ + int rv, n = 0; + + rv = cpu_eth_init(bis); + if (rv > 0) + n += rv; + + rv = usb_eth_initialize(bis); + if (rv > 0) + n += rv; + + return n; +} +#endif + diff --git a/board/raidsonic/ib62x0/ib62x0.c b/board/raidsonic/ib62x0/ib62x0.c index b7e6e4107c..5f0f3961d3 100644 --- a/board/raidsonic/ib62x0/ib62x0.c +++ b/board/raidsonic/ib62x0/ib62x0.c @@ -1,7 +1,7 @@ /* * Copyright (C) 2011-2012 * Gerald Kerma <dreagle@doukki.net> - * Luka Perkov <uboot@lukaperkov.net> + * Luka Perkov <luka@openwrt.org> * Simon Baatz <gmbnomis@gmail.com> * * See file CREDITS for list of people who contributed to this diff --git a/board/raidsonic/ib62x0/ib62x0.h b/board/raidsonic/ib62x0/ib62x0.h index 0118c2b69a..3315696dda 100644 --- a/board/raidsonic/ib62x0/ib62x0.h +++ b/board/raidsonic/ib62x0/ib62x0.h @@ -2,7 +2,7 @@ * Copyright (C) 2011-2012 * Gerald Kerma <dreagle@doukki.net> * Simon Baatz <gmbnomis@gmail.com> - * Luka Perkov <uboot@lukaperkov.net> + * Luka Perkov <luka@openwrt.org> * * See file CREDITS for list of people who contributed to this * project. diff --git a/board/raidsonic/ib62x0/kwbimage.cfg b/board/raidsonic/ib62x0/kwbimage.cfg index bd594ebd5d..bade627ccf 100644 --- a/board/raidsonic/ib62x0/kwbimage.cfg +++ b/board/raidsonic/ib62x0/kwbimage.cfg @@ -2,7 +2,7 @@ # Copyright (C) 2011-2012 # Gerald Kerma <dreagle@doukki.net> # Simon Baatz <gmbnomis@gmail.com> -# Luka Perkov <uboot@lukaperkov.net> +# Luka Perkov <luka@openwrt.org> # # See file CREDITS for list of people who contributed to this # project. diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index e8fb1ea413..ff76963925 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -25,10 +25,10 @@ #include <common.h> #include <asm/arch/gpio.h> #include <asm/arch/mmc.h> -#include <pmic.h> +#include <power/pmic.h> #include <usb/s3c_udc.h> #include <asm/arch/cpu.h> -#include <max8998_pmic.h> +#include <power/max8998_pmic.h> DECLARE_GLOBAL_DATA_PTR; static struct s5pc110_gpio *s5pc110_gpio; @@ -41,9 +41,17 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_GONI; gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; -#if defined(CONFIG_PMIC) - pmic_init(); -#endif + return 0; +} + +int power_init_board(void) +{ + int ret; + + ret = pmic_init(I2C_5); + if (ret) + return ret; + return 0; } @@ -108,7 +116,9 @@ static int s5pc1xx_phy_control(int on) { int ret; static int status; - struct pmic *p = get_pmic(); + struct pmic *p = pmic_get("MAX8998_PMIC"); + if (!p) + return -ENODEV; if (pmic_probe(p)) return -1; diff --git a/board/samsung/trats/trats.c b/board/samsung/trats/trats.c index d5c681c05e..4724029424 100644 --- a/board/samsung/trats/trats.c +++ b/board/samsung/trats/trats.c @@ -35,10 +35,13 @@ #include <asm/arch/mipi_dsim.h> #include <asm/arch/watchdog.h> #include <asm/arch/power.h> -#include <pmic.h> +#include <power/pmic.h> #include <usb/s3c_udc.h> -#include <max8997_pmic.h> +#include <power/max8997_pmic.h> #include <libtizen.h> +#include <power/max8997_muic.h> +#include <power/battery.h> +#include <power/max17042_fg.h> #include "setup.h" @@ -69,10 +72,6 @@ int board_init(void) check_hw_revision(); printf("HW Revision:\t0x%x\n", board_rev); -#if defined(CONFIG_PMIC) - pmic_init(); -#endif - return 0; } @@ -91,6 +90,275 @@ void i2c_init_board(void) s5p_gpio_direction_output(&gpio2->y4, 1, 1); } +static void trats_low_power_mode(void) +{ + struct exynos4_clock *clk = + (struct exynos4_clock *)samsung_get_base_clock(); + struct exynos4_power *pwr = + (struct exynos4_power *)samsung_get_base_power(); + + /* Power down CORE1 */ + /* LOCAL_PWR_CFG [1:0] 0x3 EN, 0x0 DIS */ + writel(0x0, &pwr->arm_core1_configuration); + + /* Change the APLL frequency */ + /* ENABLE (1 enable) | LOCKED (1 locked) */ + /* [31] | [29] */ + /* FSEL | MDIV | PDIV | SDIV */ + /* [27] | [25:16] | [13:8] | [2:0] */ + writel(0xa0c80604, &clk->apll_con0); + + /* Change CPU0 clock divider */ + /* CORE2_RATIO | APLL_RATIO | PCLK_DBG_RATIO | ATB_RATIO */ + /* [30:28] | [26:24] | [22:20] | [18:16] */ + /* PERIPH_RATIO | COREM1_RATIO | COREM0_RATIO | CORE_RATIO */ + /* [14:12] | [10:8] | [6:4] | [2:0] */ + writel(0x00000100, &clk->div_cpu0); + + /* CLK_DIV_STAT_CPU0 - wait until clock gets stable (0 = stable) */ + while (readl(&clk->div_stat_cpu0) & 0x1111111) + continue; + + /* Change clock divider ratio for DMC */ + /* DMCP_RATIO | DMCD_RATIO */ + /* [22:20] | [18:16] */ + /* DMC_RATIO | DPHY_RATIO | ACP_PCLK_RATIO | ACP_RATIO */ + /* [14:12] | [10:8] | [6:4] | [2:0] */ + writel(0x13113117, &clk->div_dmc0); + + /* CLK_DIV_STAT_DMC0 - wait until clock gets stable (0 = stable) */ + while (readl(&clk->div_stat_dmc0) & 0x11111111) + continue; + + /* Turn off unnecessary power domains */ + writel(0x0, &pwr->xxti_configuration); /* XXTI */ + writel(0x0, &pwr->cam_configuration); /* CAM */ + writel(0x0, &pwr->tv_configuration); /* TV */ + writel(0x0, &pwr->mfc_configuration); /* MFC */ + writel(0x0, &pwr->g3d_configuration); /* G3D */ + writel(0x0, &pwr->gps_configuration); /* GPS */ + writel(0x0, &pwr->gps_alive_configuration); /* GPS_ALIVE */ + + /* Turn off unnecessary clocks */ + writel(0x0, &clk->gate_ip_cam); /* CAM */ + writel(0x0, &clk->gate_ip_tv); /* TV */ + writel(0x0, &clk->gate_ip_mfc); /* MFC */ + writel(0x0, &clk->gate_ip_g3d); /* G3D */ + writel(0x0, &clk->gate_ip_image); /* IMAGE */ + writel(0x0, &clk->gate_ip_gps); /* GPS */ +} + +static int pmic_init_max8997(void) +{ + struct pmic *p = pmic_get("MAX8997_PMIC"); + int i = 0, ret = 0; + u32 val; + + if (pmic_probe(p)) + return -1; + + /* BUCK1 VARM: 1.2V */ + val = (1200000 - 650000) / 25000; + ret |= pmic_reg_write(p, MAX8997_REG_BUCK1DVS1, val); + val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */ + ret |= pmic_reg_write(p, MAX8997_REG_BUCK1CTRL, val); + + /* BUCK2 VINT: 1.1V */ + val = (1100000 - 650000) / 25000; + ret |= pmic_reg_write(p, MAX8997_REG_BUCK2DVS1, val); + val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */ + ret |= pmic_reg_write(p, MAX8997_REG_BUCK2CTRL, val); + + + /* BUCK3 G3D: 1.1V - OFF */ + ret |= pmic_reg_read(p, MAX8997_REG_BUCK3CTRL, &val); + val &= ~ENBUCK; + ret |= pmic_reg_write(p, MAX8997_REG_BUCK3CTRL, val); + + val = (1100000 - 750000) / 50000; + ret |= pmic_reg_write(p, MAX8997_REG_BUCK3DVS, val); + + /* BUCK4 CAMISP: 1.2V - OFF */ + ret |= pmic_reg_read(p, MAX8997_REG_BUCK4CTRL, &val); + val &= ~ENBUCK; + ret |= pmic_reg_write(p, MAX8997_REG_BUCK4CTRL, val); + + val = (1200000 - 650000) / 25000; + ret |= pmic_reg_write(p, MAX8997_REG_BUCK4DVS, val); + + /* BUCK5 VMEM: 1.2V */ + val = (1200000 - 650000) / 25000; + for (i = 0; i < 8; i++) + ret |= pmic_reg_write(p, MAX8997_REG_BUCK5DVS1 + i, val); + + val = ENBUCK | ACTIVE_DISCHARGE; /* DVS OFF */ + ret |= pmic_reg_write(p, MAX8997_REG_BUCK5CTRL, val); + + /* BUCK6 CAM AF: 2.8V */ + /* No Voltage Setting Register */ + /* GNSLCT 3.0X */ + val = GNSLCT; + ret |= pmic_reg_write(p, MAX8997_REG_BUCK6CTRL, val); + + /* BUCK7 VCC_SUB: 2.0V */ + val = (2000000 - 750000) / 50000; + ret |= pmic_reg_write(p, MAX8997_REG_BUCK7DVS, val); + + /* LDO1 VADC: 3.3V */ + val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */ + ret |= pmic_reg_write(p, MAX8997_REG_LDO1CTRL, val); + + /* LDO1 Disable active discharging */ + ret |= pmic_reg_read(p, MAX8997_REG_LDO1CONFIG, &val); + val &= ~LDO_ADE; + ret |= pmic_reg_write(p, MAX8997_REG_LDO1CONFIG, val); + + /* LDO2 VALIVE: 1.1V */ + val = max8997_reg_ldo(1100000) | EN_LDO; + ret |= pmic_reg_write(p, MAX8997_REG_LDO2CTRL, val); + + /* LDO3 VUSB/MIPI: 1.1V */ + val = max8997_reg_ldo(1100000) | DIS_LDO; /* OFF */ + ret |= pmic_reg_write(p, MAX8997_REG_LDO3CTRL, val); + + /* LDO4 VMIPI: 1.8V */ + val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */ + ret |= pmic_reg_write(p, MAX8997_REG_LDO4CTRL, val); + + /* LDO5 VHSIC: 1.2V */ + val = max8997_reg_ldo(1200000) | DIS_LDO; /* OFF */ + ret |= pmic_reg_write(p, MAX8997_REG_LDO5CTRL, val); + + /* LDO6 VCC_1.8V_PDA: 1.8V */ + val = max8997_reg_ldo(1800000) | EN_LDO; + ret |= pmic_reg_write(p, MAX8997_REG_LDO6CTRL, val); + + /* LDO7 CAM_ISP: 1.8V */ + val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */ + ret |= pmic_reg_write(p, MAX8997_REG_LDO7CTRL, val); + + /* LDO8 VDAC/VUSB: 3.3V */ + val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */ + ret |= pmic_reg_write(p, MAX8997_REG_LDO8CTRL, val); + + /* LDO9 VCC_2.8V_PDA: 2.8V */ + val = max8997_reg_ldo(2800000) | EN_LDO; + ret |= pmic_reg_write(p, MAX8997_REG_LDO9CTRL, val); + + /* LDO10 VPLL: 1.1V */ + val = max8997_reg_ldo(1100000) | EN_LDO; + ret |= pmic_reg_write(p, MAX8997_REG_LDO10CTRL, val); + + /* LDO11 TOUCH: 2.8V */ + val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */ + ret |= pmic_reg_write(p, MAX8997_REG_LDO11CTRL, val); + + /* LDO12 VTCAM: 1.8V */ + val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */ + ret |= pmic_reg_write(p, MAX8997_REG_LDO12CTRL, val); + + /* LDO13 VCC_3.0_LCD: 3.0V */ + val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */ + ret |= pmic_reg_write(p, MAX8997_REG_LDO13CTRL, val); + + /* LDO14 MOTOR: 3.0V */ + val = max8997_reg_ldo(3000000) | DIS_LDO; /* OFF */ + ret |= pmic_reg_write(p, MAX8997_REG_LDO14CTRL, val); + + /* LDO15 LED_A: 2.8V */ + val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */ + ret |= pmic_reg_write(p, MAX8997_REG_LDO15CTRL, val); + + /* LDO16 CAM_SENSOR: 1.8V */ + val = max8997_reg_ldo(1800000) | DIS_LDO; /* OFF */ + ret |= pmic_reg_write(p, MAX8997_REG_LDO16CTRL, val); + + /* LDO17 VTF: 2.8V */ + val = max8997_reg_ldo(2800000) | DIS_LDO; /* OFF */ + ret |= pmic_reg_write(p, MAX8997_REG_LDO17CTRL, val); + + /* LDO18 TOUCH_LED 3.3V */ + val = max8997_reg_ldo(3300000) | DIS_LDO; /* OFF */ + ret |= pmic_reg_write(p, MAX8997_REG_LDO18CTRL, val); + + /* LDO21 VDDQ: 1.2V */ + val = max8997_reg_ldo(1200000) | EN_LDO; + ret |= pmic_reg_write(p, MAX8997_REG_LDO21CTRL, val); + + /* SAFEOUT for both 1 and 2: 4.9V, Active discharge, Enable */ + val = (SAFEOUT_4_90V << 0) | (SAFEOUT_4_90V << 2) | + ACTDISSAFEO1 | ACTDISSAFEO2 | ENSAFEOUT1 | ENSAFEOUT2; + ret |= pmic_reg_write(p, MAX8997_REG_SAFEOUTCTRL, val); + + if (ret) { + puts("MAX8997 PMIC setting error!\n"); + return -1; + } + return 0; +} + +int power_init_board(void) +{ + int chrg, ret; + struct power_battery *pb; + struct pmic *p_fg, *p_chrg, *p_muic, *p_bat; + + ret = pmic_init(I2C_5); + ret |= pmic_init_max8997(); + ret |= power_fg_init(I2C_9); + ret |= power_muic_init(I2C_5); + ret |= power_bat_init(0); + if (ret) + return ret; + + p_fg = pmic_get("MAX17042_FG"); + if (!p_fg) { + puts("MAX17042_FG: Not found\n"); + return -ENODEV; + } + + p_chrg = pmic_get("MAX8997_PMIC"); + if (!p_chrg) { + puts("MAX8997_PMIC: Not found\n"); + return -ENODEV; + } + + p_muic = pmic_get("MAX8997_MUIC"); + if (!p_muic) { + puts("MAX8997_MUIC: Not found\n"); + return -ENODEV; + } + + p_bat = pmic_get("BAT_TRATS"); + if (!p_bat) { + puts("BAT_TRATS: Not found\n"); + return -ENODEV; + } + + p_fg->parent = p_bat; + p_chrg->parent = p_bat; + p_muic->parent = p_bat; + + p_bat->low_power_mode = trats_low_power_mode; + p_bat->pbat->battery_init(p_bat, p_fg, p_chrg, p_muic); + + pb = p_bat->pbat; + chrg = p_muic->chrg->chrg_type(p_muic); + debug("CHARGER TYPE: %d\n", chrg); + + if (!p_chrg->chrg->chrg_bat_present(p_chrg)) { + puts("No battery detected\n"); + return -1; + } + + p_fg->fg->fg_battery_check(p_fg, p_bat); + + if (pb->bat->state == CHARGE && chrg == CHARGER_USB) + puts("CHARGE Battery !\n"); + + return 0; +} + int dram_init(void) { gd->ram_size = get_ram_size((long *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE) + @@ -200,7 +468,9 @@ static int s5pc210_phy_control(int on) { int ret = 0; u32 val = 0; - struct pmic *p = get_pmic(); + struct pmic *p = pmic_get("MAX8997_PMIC"); + if (!p) + return -ENODEV; if (pmic_probe(p)) return -1; @@ -379,7 +649,9 @@ static void lcd_reset(void) static int lcd_power(void) { int ret = 0; - struct pmic *p = get_pmic(); + struct pmic *p = pmic_get("MAX8997_PMIC"); + if (!p) + return -ENODEV; if (pmic_probe(p)) return 0; @@ -439,7 +711,9 @@ static struct mipi_dsim_lcd_device mipi_lcd_device = { static int mipi_power(void) { int ret = 0; - struct pmic *p = get_pmic(); + struct pmic *p = pmic_get("MAX8997_PMIC"); + if (!p) + return -ENODEV; if (pmic_probe(p)) return 0; diff --git a/board/samsung/universal_c210/universal.c b/board/samsung/universal_c210/universal.c index afe3bb0aeb..3d508bea23 100644 --- a/board/samsung/universal_c210/universal.c +++ b/board/samsung/universal_c210/universal.c @@ -31,13 +31,13 @@ #include <asm/arch/gpio.h> #include <asm/arch/mmc.h> #include <asm/arch/pinmux.h> -#include <pmic.h> -#include <usb/s3c_udc.h> -#include <asm/arch/cpu.h> -#include <max8998_pmic.h> #include <asm/arch/watchdog.h> #include <libtizen.h> #include <ld9040.h> +#include <power/pmic.h> +#include <usb/s3c_udc.h> +#include <asm/arch/cpu.h> +#include <power/max8998_pmic.h> DECLARE_GLOBAL_DATA_PTR; @@ -55,7 +55,16 @@ static int get_hwrev(void) return board_rev & 0xFF; } -static void check_hw_revision(void); +int power_init_board(void) +{ + int ret; + + ret = pmic_init(I2C_5); + if (ret) + return ret; + + return 0; +} int dram_init(void) { @@ -101,7 +110,9 @@ static unsigned short get_adc_value(int channel) static int adc_power_control(int on) { int ret; - struct pmic *p = get_pmic(); + struct pmic *p = pmic_get("MAX8998_PMIC"); + if (!p) + return -ENODEV; if (pmic_probe(p)) return -1; @@ -224,7 +235,9 @@ int board_mmc_init(bd_t *bis) static int s5pc210_phy_control(int on) { int ret = 0; - struct pmic *p = get_pmic(); + struct pmic *p = pmic_get("MAX8998_PMIC"); + if (!p) + return -ENODEV; if (pmic_probe(p)) return -1; @@ -489,10 +502,6 @@ int board_init(void) gd->bd->bi_arch_number = MACH_TYPE_UNIVERSAL_C210; gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; -#if defined(CONFIG_PMIC) - pmic_init(); - init_pmic_lcd(); -#endif #ifdef CONFIG_SOFT_SPI soft_spi_init(); #endif diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c index 45ec485c50..9508561133 100644 --- a/board/sbc8548/ddr.c +++ b/board/sbc8548/ddr.c @@ -91,7 +91,7 @@ void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address) */ phys_size_t fixed_sdram(void) { - volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); + volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR); out_be32(&ddr->cs0_bnds, 0x0000007f); out_be32(&ddr->cs1_bnds, 0x008000ff); diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c index c8235f4a9b..8a9ce790f1 100644 --- a/board/socrates/sdram.c +++ b/board/socrates/sdram.c @@ -41,7 +41,7 @@ */ phys_size_t fixed_sdram(void) { - volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); + volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR); /* * Disable memory controller. diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index b56a801a4d..f0eca54c9e 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -379,9 +379,14 @@ static struct cpsw_platform_data cpsw_data = { .host_port_num = 0, .version = CPSW_CTRL_VERSION_2, }; +#endif +#if defined(CONFIG_DRIVER_TI_CPSW) || \ + (defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) int board_eth_init(bd_t *bis) { + int rv, n = 0; +#ifdef CONFIG_DRIVER_TI_CPSW uint8_t mac_addr[6]; uint32_t mac_hi, mac_lo; @@ -400,7 +405,7 @@ int board_eth_init(bd_t *bis) if (is_valid_ether_addr(mac_addr)) eth_setenv_enetaddr("ethaddr", mac_addr); else - return -1; + goto try_usbether; } if (board_is_bone() || board_is_bone_lt() || board_is_idk()) { @@ -413,6 +418,20 @@ int board_eth_init(bd_t *bis) PHY_INTERFACE_MODE_RGMII; } - return cpsw_register(&cpsw_data); + rv = cpsw_register(&cpsw_data); + if (rv < 0) + printf("Error %d registering CPSW switch\n", rv); + else + n += rv; +#endif +try_usbether: +#if defined(CONFIG_USB_ETHER) && !defined(CONFIG_SPL_BUILD) + rv = usb_eth_initialize(bis); + if (rv < 0) + printf("Error %d registering USB_ETHER\n", rv); + else + n += rv; +#endif + return n; } #endif diff --git a/board/ti/beagle/beagle.c b/board/ti/beagle/beagle.c index 6175e1d1ac..f20ebed452 100644 --- a/board/ti/beagle/beagle.c +++ b/board/ti/beagle/beagle.c @@ -42,6 +42,11 @@ #include <asm/arch/sys_proto.h> #include <asm/gpio.h> #include <asm/mach-types.h> +#include <asm/omap_musb.h> +#include <asm/errno.h> +#include <linux/usb/ch9.h> +#include <linux/usb/gadget.h> +#include <linux/usb/musb.h> #include "beagle.h" #include <command.h> @@ -285,6 +290,33 @@ static void beagle_dvi_pup(void) } #endif +#ifdef CONFIG_USB_MUSB_OMAP2PLUS +static struct musb_hdrc_config musb_config = { + .multipoint = 1, + .dyn_fifo = 1, + .num_eps = 16, + .ram_bits = 12, +}; + +static struct omap_musb_board_data musb_board_data = { + .interface_type = MUSB_INTERFACE_ULPI, +}; + +static struct musb_hdrc_platform_data musb_plat = { +#if defined(CONFIG_MUSB_HOST) + .mode = MUSB_HOST, +#elif defined(CONFIG_MUSB_GADGET) + .mode = MUSB_PERIPHERAL, +#else +#error "Please define either CONFIG_MUSB_HOST or CONFIG_MUSB_GADGET" +#endif + .config = &musb_config, + .power = 100, + .platform_ops = &omap2430_ops, + .board_data = &musb_board_data, +}; +#endif + /* * Routine: misc_init_r * Description: Configure board specific parts @@ -466,6 +498,10 @@ int misc_init_r(void) omap3_dss_enable(); #endif +#ifdef CONFIG_USB_MUSB_OMAP2PLUS + musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE); +#endif + return 0; } @@ -513,3 +549,10 @@ int ehci_hcd_stop(int index) } #endif /* CONFIG_USB_EHCI */ + +#if defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET) +int board_eth_init(bd_t *bis) +{ + return usb_eth_initialize(bis); +} +#endif diff --git a/board/ttcontrol/vision2/vision2.c b/board/ttcontrol/vision2/vision2.c index abdd1aac2b..a471fec23d 100644 --- a/board/ttcontrol/vision2/vision2.c +++ b/board/ttcontrol/vision2/vision2.c @@ -34,7 +34,7 @@ #include <asm/arch/sys_proto.h> #include <i2c.h> #include <mmc.h> -#include <pmic.h> +#include <power/pmic.h> #include <fsl_esdhc.h> #include <fsl_pmic.h> #include <mc13892.h> @@ -306,9 +306,15 @@ static void power_init_mx51(void) { unsigned int val; struct pmic *p; + int ret; + + ret = pmic_init(I2C_PMIC); + if (ret) + return; - pmic_init(); - p = get_pmic(); + p = pmic_get("FSL_PMIC"); + if (!p) + return; /* Write needed to Power Gate 2 register */ pmic_reg_read(p, REG_POWER_MISC, &val); |
