diff options
Diffstat (limited to 'board/ti/ks2_evm')
| -rw-r--r-- | board/ti/ks2_evm/Makefile | 13 | ||||
| -rw-r--r-- | board/ti/ks2_evm/README_K2HK | 148 | ||||
| -rw-r--r-- | board/ti/ks2_evm/board.c | 229 | ||||
| -rw-r--r-- | board/ti/ks2_evm/board.h | 19 | ||||
| -rw-r--r-- | board/ti/ks2_evm/board_k2e.c | 39 | ||||
| -rw-r--r-- | board/ti/ks2_evm/board_k2hk.c | 81 | ||||
| -rw-r--r-- | board/ti/ks2_evm/ddr3_cfg.c | 170 | ||||
| -rw-r--r-- | board/ti/ks2_evm/ddr3_cfg.h | 24 | ||||
| -rw-r--r-- | board/ti/ks2_evm/ddr3_k2e.c | 55 | ||||
| -rw-r--r-- | board/ti/ks2_evm/ddr3_k2hk.c | 84 |
10 files changed, 862 insertions, 0 deletions
diff --git a/board/ti/ks2_evm/Makefile b/board/ti/ks2_evm/Makefile new file mode 100644 index 0000000000..00f1164833 --- /dev/null +++ b/board/ti/ks2_evm/Makefile @@ -0,0 +1,13 @@ +# +# KS2-EVM: board Makefile +# (C) Copyright 2012-2014 +# Texas Instruments Incorporated, <www.ti.com> +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += board.o +obj-y += ddr3_cfg.o +obj-$(CONFIG_K2HK_EVM) += board_k2hk.o +obj-$(CONFIG_K2HK_EVM) += ddr3_k2hk.o +obj-$(CONFIG_K2E_EVM) += board_k2e.o +obj-$(CONFIG_K2E_EVM) += ddr3_k2e.o diff --git a/board/ti/ks2_evm/README_K2HK b/board/ti/ks2_evm/README_K2HK new file mode 100644 index 0000000000..7426b8dc97 --- /dev/null +++ b/board/ti/ks2_evm/README_K2HK @@ -0,0 +1,148 @@ +U-Boot port for Texas Instruments XTCIEVMK2X +============================================ + +Author: Murali Karicheri <m-karicheri2@ti.com> + +This README has information on the u-boot port for XTCIEVMK2X EVM board. +Documentation for this board can be found at + http://www.advantech.com/Support/TI-EVM/EVMK2HX_sd.aspx + +The board is based on Texas Instruments Keystone2 family of SoCs : K2H, K2K. +More details on these SoCs are available at company websites + K2K: http://www.ti.com/product/tci6638k2k + K2H: http://www.ti.com/product/tci6638k2h + +Board configuration: +==================== + +Some of the peripherals that are configured by u-boot are:- + +1. 2GB DDR3 (can support 8GB SO DIMM as well) +2. 512M NAND (over ti emif16 bus) +3. 6MB MSM SRAM (part of the SoC) +4. two 1GBit Ethernet ports (SoC supports upto 4) +5. two UART ports +6. three i2c interfaces +7. three spi interfaces (only 1 interface supported in driver) + +There are seperate PLLs to drive clocks to Tetris ARM and Peripherals. +To bring up SMP Linux on this board, there is a boot monitor +code that will be installed in MSMC SRAM. There is command available +to install this image from u-boot. + +The port related files can be found at following folders + keystone2 SoC related files: arch/arm/cpu/armv7/keystone/ + K2HK evm board files: board/ti/k2hk_evm/ + +board configuration file: include/configs/k2hk_evm.h + +Supported boot modes: + - SPI NOR boot + - AEMIF NAND boot + +Supported image formats:- + - u-boot.bin: for loading and running u-boot.bin through Texas instruments + code composure studio (CCS) + - u-boot-spi.gph: gpimage for programming SPI NOR flash for SPI NOR boot + - u-boot-nand.gph: gpimage for programming AEMIF NAND flash for NAND boot + +Build instructions: +=================== + +To build u-boot.bin + >make k2hk_evm_config + >make u-boot-spi.gph + +To build u-boot-spi.gph + >make k2hk_evm_config + >make u-boot-spi.gph + +To build u-boot-nand.gph + >make k2hk_evm_config + >make u-boot-nand.gph + +Load and Run U-Boot on K2HK EVM using CCS +========================================= + +Need Code Composer Studio (CCS) installed on a PC to load and run u-boot.bin +on EVM. See instructions at below link for installing CCS on a Windows PC. +http://processors.wiki.ti.com/index.php/MCSDK_UG_Chapter_Getting_Started# +Installing_Code_Composer_Studio +Use u-boot.bin from the build folder for loading annd running u-boot binary +on EVM. Follow instructions at +http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup +to configure SW1 dip switch to use "No Boot/JTAG DSP Little Endian Boot Mode" +and Power ON the EVM. Follow instructions to connect serial port of EVM to +PC and start TeraTerm or Hyper Terminal. + +Start CCS on a Windows machine and Launch Target +configuration as instructed at http://processors.wiki.ti.com/index.php/ +MCSDK_UG_Chapter_Exploring#Loading_and_Running_U-Boot_on_EVM_through_CCS. +The instructions provided in the above link uses a script for +loading the u-boot binary on the target EVM. Instead do the following:- + +1. Right click to "Texas Instruments XDS2xx USB Emulator_0/CortexA15_1 core (D + isconnected: Unknown)" at the debug window (This is created once Target + configuration is launched) and select "Connect Target". +2. Once target connect is successful, choose Tools->Load Memory option from the + top level menu. At the Load Memory window, choose the file u-boot.bin + through "Browse" button and click "next >" button. In the next window, enter + Start address as 0xc001000, choose Type-size "32 bits" and click "Finish" + button. +3. Click View -> Registers from the top level menu to view registers window. +4. From Registers, window expand "Core Registers" to view PC. Edit PC value + to be 0xc001000. From the "Run" top level menu, select "Free Run" +5. The U-Boot prompt is shown at the Tera Term/ Hyper terminal console as + below and type any key to stop autoboot as instructed := + +U-Boot 2014.04-rc1-00201-gc215b5a (Mar 21 2014 - 12:47:59) + +I2C: ready +Detected SO-DIMM [SQR-SD3T-2G1333SED] +DRAM: 1.1 GiB +NAND: 512 MiB +Net: K2HK_EMAC +Warning: K2HK_EMAC using MAC address from net device +, K2HK_EMAC1, K2HK_EMAC2, K2HK_EMAC3 +Hit any key to stop autoboot: 0 + +SPI NOR Flash programming instructions +====================================== +U-Boot image can be flashed to first 512KB of the NOR flash using following +instructions:- + +1. Start CCS and run U-boot as described above. +2. Suspend Target. Select Run -> Suspend from top level menu + CortexA15_1 (Free Running)" +3. Load u-boot-spi.gph binary from build folder on to DDR address 0x87000000 + through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM + using CCS", but using address 0x87000000. +4. Free Run the target as desribed earlier (step 4) to get u-boot prompt +5. At the U-Boot console type following to setup u-boot environment variables. + setenv addr_uboot 0x87000000 + setenv filesize <size in hex of u-boot-spi.gph rounded to hex 0x10000> + run burn_uboot_spi + Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch + to "SPI Little Endian Boot mode" as per instruction at + http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup. +6. Power ON the EVM. The EVM now boots with u-boot image on the NOR flash. + +AEMIF NAND Flash programming instructions +====================================== +U-Boot image can be flashed to first 1024KB of the NAND flash using following +instructions:- + +1. Start CCS and run U-boot as described above. +2. Suspend Target. Select Run -> Suspend from top level menu + CortexA15_1 (Free Running)" +3. Load u-boot-nand.gph binary from build folder on to DDR address 0x87000000 + through CCS as described in step 2 of "Load and Run U-Boot on K2HK EVM + using CCS", but using address 0x87000000. +4. Free Run the target as desribed earlier (step 4) to get u-boot prompt +5. At the U-Boot console type following to setup u-boot environment variables. + setenv filesize <size in hex of u-boot-nand.gph rounded to hex 0x10000> + run burn_uboot_nand + Once u-boot prompt is available, Power OFF the EVM. Set the SW1 dip switch + to "ARM NAND Boot mode" as per instruction at + http://processors.wiki.ti.com/index.php/EVMK2H_Hardware_Setup. +6. Power ON the EVM. The EVM now boots with u-boot image on the NAND flash. diff --git a/board/ti/ks2_evm/board.c b/board/ti/ks2_evm/board.c new file mode 100644 index 0000000000..dfe7be60e7 --- /dev/null +++ b/board/ti/ks2_evm/board.c @@ -0,0 +1,229 @@ +/* + * Keystone : Board initialization + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include "board.h" +#include <common.h> +#include <exports.h> +#include <fdt_support.h> +#include <asm/arch/ddr3.h> +#include <asm/arch/emac_defs.h> +#include <asm/ti-common/ti-aemif.h> + +DECLARE_GLOBAL_DATA_PTR; + +static struct aemif_config aemif_configs[] = { + { /* CS0 */ + .mode = AEMIF_MODE_NAND, + .wr_setup = 0xf, + .wr_strobe = 0x3f, + .wr_hold = 7, + .rd_setup = 0xf, + .rd_strobe = 0x3f, + .rd_hold = 7, + .turn_around = 3, + .width = AEMIF_WIDTH_8, + }, +}; + +int dram_init(void) +{ + ddr3_init(); + + gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, + CONFIG_MAX_RAM_BANK_SIZE); + aemif_init(ARRAY_SIZE(aemif_configs), aemif_configs); + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = CONFIG_LINUX_BOOT_PARAM_ADDR; + + return 0; +} + +#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET +int get_eth_env_param(char *env_name) +{ + char *env; + int res = -1; + + env = getenv(env_name); + if (env) + res = simple_strtol(env, NULL, 0); + + return res; +} + +int board_eth_init(bd_t *bis) +{ + int j; + int res; + int port_num; + char link_type_name[32]; + + port_num = get_num_eth_ports(); + + for (j = 0; j < port_num; j++) { + sprintf(link_type_name, "sgmii%d_link_type", j); + res = get_eth_env_param(link_type_name); + if (res >= 0) + eth_priv_cfg[j].sgmii_link_type = res; + + keystone2_emac_initialize(ð_priv_cfg[j]); + } + + return 0; +} +#endif + +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + int lpae; + char *env; + char *endp; + int nbanks; + u64 size[2]; + u64 start[2]; + char name[32]; + int nodeoffset; + u32 ddr3a_size; + int unitrd_fixup = 0; + + env = getenv("mem_lpae"); + lpae = env && simple_strtol(env, NULL, 0); + env = getenv("uinitrd_fixup"); + unitrd_fixup = env && simple_strtol(env, NULL, 0); + + ddr3a_size = 0; + if (lpae) { + env = getenv("ddr3a_size"); + if (env) + ddr3a_size = simple_strtol(env, NULL, 10); + if ((ddr3a_size != 8) && (ddr3a_size != 4)) + ddr3a_size = 0; + } + + nbanks = 1; + start[0] = bd->bi_dram[0].start; + size[0] = bd->bi_dram[0].size; + + /* adjust memory start address for LPAE */ + if (lpae) { + start[0] -= CONFIG_SYS_SDRAM_BASE; + start[0] += CONFIG_SYS_LPAE_SDRAM_BASE; + } + + if ((size[0] == 0x80000000) && (ddr3a_size != 0)) { + size[1] = ((u64)ddr3a_size - 2) << 30; + start[1] = 0x880000000; + nbanks++; + } + + /* reserve memory at start of bank */ + sprintf(name, "mem_reserve_head"); + env = getenv(name); + if (env) { + start[0] += ustrtoul(env, &endp, 0); + size[0] -= ustrtoul(env, &endp, 0); + } + + sprintf(name, "mem_reserve"); + env = getenv(name); + if (env) + size[0] -= ustrtoul(env, &endp, 0); + + fdt_fixup_memory_banks(blob, start, size, nbanks); + + /* Fix up the initrd */ + if (lpae && unitrd_fixup) { + int err; + u32 *prop1, *prop2; + u64 initrd_start, initrd_end; + + nodeoffset = fdt_path_offset(blob, "/chosen"); + if (nodeoffset >= 0) { + prop1 = (u32 *)fdt_getprop(blob, nodeoffset, + "linux,initrd-start", NULL); + prop2 = (u32 *)fdt_getprop(blob, nodeoffset, + "linux,initrd-end", NULL); + if (prop1 && prop2) { + initrd_start = __be32_to_cpu(*prop1); + initrd_start -= CONFIG_SYS_SDRAM_BASE; + initrd_start += CONFIG_SYS_LPAE_SDRAM_BASE; + initrd_start = __cpu_to_be64(initrd_start); + initrd_end = __be32_to_cpu(*prop2); + initrd_end -= CONFIG_SYS_SDRAM_BASE; + initrd_end += CONFIG_SYS_LPAE_SDRAM_BASE; + initrd_end = __cpu_to_be64(initrd_end); + + err = fdt_delprop(blob, nodeoffset, + "linux,initrd-start"); + if (err < 0) + puts("error deleting initrd-start\n"); + + err = fdt_delprop(blob, nodeoffset, + "linux,initrd-end"); + if (err < 0) + puts("error deleting initrd-end\n"); + + err = fdt_setprop(blob, nodeoffset, + "linux,initrd-start", + &initrd_start, + sizeof(initrd_start)); + if (err < 0) + puts("error adding initrd-start\n"); + + err = fdt_setprop(blob, nodeoffset, + "linux,initrd-end", + &initrd_end, + sizeof(initrd_end)); + if (err < 0) + puts("error adding linux,initrd-end\n"); + } + } + } +} + +void ft_board_setup_ex(void *blob, bd_t *bd) +{ + int lpae; + u64 size; + char *env; + u64 *reserve_start; + + env = getenv("mem_lpae"); + lpae = env && simple_strtol(env, NULL, 0); + + if (lpae) { + /* + * the initrd and other reserved memory areas are + * embedded in in the DTB itslef. fix up these addresses + * to 36 bit format + */ + reserve_start = (u64 *)((char *)blob + + fdt_off_mem_rsvmap(blob)); + while (1) { + *reserve_start = __cpu_to_be64(*reserve_start); + size = __cpu_to_be64(*(reserve_start + 1)); + if (size) { + *reserve_start -= CONFIG_SYS_SDRAM_BASE; + *reserve_start += + CONFIG_SYS_LPAE_SDRAM_BASE; + *reserve_start = + __cpu_to_be64(*reserve_start); + } else { + break; + } + reserve_start += 2; + } + } +} +#endif diff --git a/board/ti/ks2_evm/board.h b/board/ti/ks2_evm/board.h new file mode 100644 index 0000000000..d91ef73612 --- /dev/null +++ b/board/ti/ks2_evm/board.h @@ -0,0 +1,19 @@ +/* + * K2HK EVM : Board common header + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _KS2_BOARD +#define _KS2_BOARD + +#include <asm/arch/emac_defs.h> + +extern struct eth_priv_t eth_priv_cfg[]; + +int get_num_eth_ports(void); + +#endif diff --git a/board/ti/ks2_evm/board_k2e.c b/board/ti/ks2_evm/board_k2e.c new file mode 100644 index 0000000000..d2499b7244 --- /dev/null +++ b/board/ti/ks2_evm/board_k2e.c @@ -0,0 +1,39 @@ +/* + * K2E EVM : Board initialization + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/ddr3.h> +#include <asm/arch/hardware.h> + +DECLARE_GLOBAL_DATA_PTR; + +unsigned int external_clk[ext_clk_count] = { + [sys_clk] = 100000000, + [alt_core_clk] = 100000000, + [pa_clk] = 100000000, + [ddr3_clk] = 100000000, + [mcm_clk] = 312500000, + [pcie_clk] = 100000000, + [sgmii_clk] = 156250000, + [xgmii_clk] = 156250000, + [usb_clk] = 100000000, +}; + +static struct pll_init_data pll_config[] = { + CORE_PLL_1200, + PASS_PLL_1000, +}; + +#if defined(CONFIG_BOARD_EARLY_INIT_F) +int board_early_init_f(void) +{ + init_plls(ARRAY_SIZE(pll_config), pll_config); + return 0; +} +#endif diff --git a/board/ti/ks2_evm/board_k2hk.c b/board/ti/ks2_evm/board_k2hk.c new file mode 100644 index 0000000000..a369d6bd63 --- /dev/null +++ b/board/ti/ks2_evm/board_k2hk.c @@ -0,0 +1,81 @@ +/* + * K2HK EVM : Board initialization + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/hardware.h> +#include <asm/arch/emac_defs.h> + +DECLARE_GLOBAL_DATA_PTR; + +unsigned int external_clk[ext_clk_count] = { + [sys_clk] = 122880000, + [alt_core_clk] = 125000000, + [pa_clk] = 122880000, + [tetris_clk] = 125000000, + [ddr3a_clk] = 100000000, + [ddr3b_clk] = 100000000, + [mcm_clk] = 312500000, + [pcie_clk] = 100000000, + [sgmii_srio_clk] = 156250000, + [xgmii_clk] = 156250000, + [usb_clk] = 100000000, + [rp1_clk] = 123456789 +}; + +static struct pll_init_data pll_config[] = { + CORE_PLL_1228, + PASS_PLL_983, + TETRIS_PLL_1200, +}; + +#ifdef CONFIG_DRIVER_TI_KEYSTONE_NET +struct eth_priv_t eth_priv_cfg[] = { + { + .int_name = "K2HK_EMAC", + .rx_flow = 22, + .phy_addr = 0, + .slave_port = 1, + .sgmii_link_type = SGMII_LINK_MAC_PHY, + }, + { + .int_name = "K2HK_EMAC1", + .rx_flow = 23, + .phy_addr = 1, + .slave_port = 2, + .sgmii_link_type = SGMII_LINK_MAC_PHY, + }, + { + .int_name = "K2HK_EMAC2", + .rx_flow = 24, + .phy_addr = 2, + .slave_port = 3, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, + { + .int_name = "K2HK_EMAC3", + .rx_flow = 25, + .phy_addr = 3, + .slave_port = 4, + .sgmii_link_type = SGMII_LINK_MAC_MAC_FORCED, + }, +}; + +int get_num_eth_ports(void) +{ + return sizeof(eth_priv_cfg) / sizeof(struct eth_priv_t); +} +#endif + +#ifdef CONFIG_BOARD_EARLY_INIT_F +int board_early_init_f(void) +{ + init_plls(ARRAY_SIZE(pll_config), pll_config); + return 0; +} +#endif diff --git a/board/ti/ks2_evm/ddr3_cfg.c b/board/ti/ks2_evm/ddr3_cfg.c new file mode 100644 index 0000000000..f7da9f2bcb --- /dev/null +++ b/board/ti/ks2_evm/ddr3_cfg.c @@ -0,0 +1,170 @@ +/* + * Keystone2: DDR3 configuration + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> + +#include <i2c.h> +#include <asm/arch/ddr3.h> +#include <asm/arch/hardware.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* DDR3 PHY configuration data with 1600M rate, 8GB size */ +struct ddr3_phy_config ddr3phy_1600_8g = { + .pllcr = 0x0001C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0D861A80ul, + .ptr4 = 0x0C827100ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), + .dcr_val = ((1 << 10)), + .dtpr0 = 0xA19DBB66ul, + .dtpr1 = 0x32868300ul, + .dtpr2 = 0x50035200ul, + .mr0 = 0x00001C70ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000018ul, + .dtcr = 0x730035C7ul, + .pgcr2 = 0x00F07A12ul, + .zq0cr1 = 0x0000005Dul, + .zq1cr1 = 0x0000005Bul, + .zq2cr1 = 0x0000005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +/* DDR3 EMIF configuration data with 1600M rate, 8GB size */ +struct ddr3_emif_config ddr3_1600_8g = { + .sdcfg = 0x6200CE6Aul, + .sdtim1 = 0x16709C55ul, + .sdtim2 = 0x00001D4Aul, + .sdtim3 = 0x435DFF54ul, + .sdtim4 = 0x553F0CFFul, + .zqcfg = 0xF0073200ul, + .sdrfc = 0x00001869ul, +}; + +#ifdef CONFIG_K2HK_EVM +/* DDR3 PHY configuration data with 1333M rate, and 2GB size */ +struct ddr3_phy_config ddr3phy_1333_2g = { + .pllcr = 0x0005C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x0B4515C2ul, + .ptr4 = 0x0A6E08B4ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), + .dcr_val = ((1 << 10)), + .dtpr0 = 0x8558AA55ul, + .dtpr1 = 0x32857280ul, + .dtpr2 = 0x5002C200ul, + .mr0 = 0x00001A60ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000010ul, + .dtcr = 0x710035C7ul, + .pgcr2 = 0x00F065B8ul, + .zq0cr1 = 0x0000005Dul, + .zq1cr1 = 0x0000005Bul, + .zq2cr1 = 0x0000005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +/* DDR3 EMIF configuration data with 1333M rate, and 2GB size */ +struct ddr3_emif_config ddr3_1333_2g = { + .sdcfg = 0x62008C62ul, + .sdtim1 = 0x125C8044ul, + .sdtim2 = 0x00001D29ul, + .sdtim3 = 0x32CDFF43ul, + .sdtim4 = 0x543F0ADFul, + .zqcfg = 0x70073200ul, + .sdrfc = 0x00001457ul, +}; +#endif + +#ifdef CONFIG_K2E_EVM +/* DDR3 PHY configuration data with 1600M rate, and 4GB size */ +struct ddr3_phy_config ddr3phy_1600_4g = { + .pllcr = 0x0001C000ul, + .pgcr1_mask = (IODDRM_MASK | ZCKSEL_MASK), + .pgcr1_val = ((1 << 2) | (1 << 7) | (1 << 23)), + .ptr0 = 0x42C21590ul, + .ptr1 = 0xD05612C0ul, + .ptr2 = 0, /* not set in gel */ + .ptr3 = 0x08861A80ul, + .ptr4 = 0x0C827100ul, + .dcr_mask = (PDQ_MASK | MPRDQ_MASK | BYTEMASK_MASK), + .dcr_val = ((1 << 10)), + .dtpr0 = 0x9D9CBB66ul, + .dtpr1 = 0x12840300ul, + .dtpr2 = 0x5002D200ul, + .mr0 = 0x00001C70ul, + .mr1 = 0x00000006ul, + .mr2 = 0x00000018ul, + .dtcr = 0x710035C7ul, + .pgcr2 = 0x00F07A12ul, + .zq0cr1 = 0x0001005Dul, + .zq1cr1 = 0x0001005Bul, + .zq2cr1 = 0x0001005Bul, + .pir_v1 = 0x00000033ul, + .pir_v2 = 0x0000FF81ul, +}; + +/* DDR3 EMIF configuration data with 1600M rate, and 4GB size */ +struct ddr3_emif_config ddr3_1600_4g = { + .sdcfg = 0x6200CE62ul, + .sdtim1 = 0x166C9855ul, + .sdtim2 = 0x00001D4Aul, + .sdtim3 = 0x421DFF53ul, + .sdtim4 = 0x543F07FFul, + .zqcfg = 0x70073200ul, + .sdrfc = 0x00001869ul, +}; +#endif + +int ddr3_get_dimm_params(char *dimm_name) +{ + int ret; + int old_bus; + u8 spd_params[256]; + + i2c_init(CONFIG_SYS_DAVINCI_I2C_SPEED, CONFIG_SYS_DAVINCI_I2C_SLAVE); + + old_bus = i2c_get_bus_num(); + i2c_set_bus_num(1); + + ret = i2c_read(0x53, 0, 1, spd_params, 256); + + i2c_set_bus_num(old_bus); + + dimm_name[0] = '\0'; + + if (ret) { + puts("Cannot read DIMM params\n"); + return 1; + } + + /* + * We need to convert spd data to dimm parameters + * and to DDR3 EMIF and PHY regirsters values. + * For now we just return DIMM type string value. + * Caller may use this value to choose appropriate + * a pre-set DDR3 configuration + */ + + strncpy(dimm_name, (char *)&spd_params[0x80], 18); + dimm_name[18] = '\0'; + + return 0; +} diff --git a/board/ti/ks2_evm/ddr3_cfg.h b/board/ti/ks2_evm/ddr3_cfg.h new file mode 100644 index 0000000000..15fcf52ef1 --- /dev/null +++ b/board/ti/ks2_evm/ddr3_cfg.h @@ -0,0 +1,24 @@ +/* + * Keystone2: DDR3 configuration + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __DDR3_CFG_H +#define __DDR3_CFG_H + +extern struct ddr3_phy_config ddr3phy_1600_8g; +extern struct ddr3_emif_config ddr3_1600_8g; + +extern struct ddr3_phy_config ddr3phy_1333_2g; +extern struct ddr3_emif_config ddr3_1333_2g; + +extern struct ddr3_phy_config ddr3phy_1600_4g; +extern struct ddr3_emif_config ddr3_1600_4g; + +int ddr3_get_dimm_params(char *dimm_name); + +#endif /* __DDR3_CFG_H */ diff --git a/board/ti/ks2_evm/ddr3_k2e.c b/board/ti/ks2_evm/ddr3_k2e.c new file mode 100644 index 0000000000..40fd96607d --- /dev/null +++ b/board/ti/ks2_evm/ddr3_k2e.c @@ -0,0 +1,55 @@ +/* + * Keystone2: DDR3 initialization + * + * (C) Copyright 2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include "ddr3_cfg.h" +#include <asm/arch/ddr3.h> + +static int ddr3_size; +static struct pll_init_data ddr3_400 = DDR3_PLL_400; + +void ddr3_init(void) +{ + char dimm_name[32]; + + if (~(readl(KS2_PLL_CNTRL_BASE + KS2_RSTCTRL_RSTYPE) & 0x1)) + init_pll(&ddr3_400); + + ddr3_get_dimm_params(dimm_name); + + printf("Detected SO-DIMM [%s]\n", dimm_name); + + /* Reset DDR3 PHY after PLL enabled */ + ddr3_reset_ddrphy(); + + if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) { + /* 8G SO-DIMM */ + ddr3_size = 8; + printf("DRAM: 8 GiB\n"); + ddr3phy_1600_8g.zq0cr1 |= 0x10000; + ddr3phy_1600_8g.zq1cr1 |= 0x10000; + ddr3phy_1600_8g.zq2cr1 |= 0x10000; + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g); + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_8g); + } else if (!strcmp(dimm_name, "18KSF51272HZ-1G6K2")) { + /* 4G SO-DIMM */ + ddr3_size = 4; + printf("DRAM: 4 GiB\n"); + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_4g); + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, &ddr3_1600_4g); + } +} + +/** + * ddr3_get_size - return ddr3 size in GiB + */ +int ddr3_get_size(void) +{ + return ddr3_size; +} diff --git a/board/ti/ks2_evm/ddr3_k2hk.c b/board/ti/ks2_evm/ddr3_k2hk.c new file mode 100644 index 0000000000..21a5a0a252 --- /dev/null +++ b/board/ti/ks2_evm/ddr3_k2hk.c @@ -0,0 +1,84 @@ +/* + * Keystone2: DDR3 initialization + * + * (C) Copyright 2012-2014 + * Texas Instruments Incorporated, <www.ti.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include "ddr3_cfg.h" +#include <asm/arch/ddr3.h> +#include <asm/arch/hardware.h> + +struct pll_init_data ddr3a_333 = DDR3_PLL_333(A); +struct pll_init_data ddr3a_400 = DDR3_PLL_400(A); + +void ddr3_init(void) +{ + char dimm_name[32]; + + ddr3_get_dimm_params(dimm_name); + + printf("Detected SO-DIMM [%s]\n", dimm_name); + + if (!strcmp(dimm_name, "18KSF1G72HZ-1G6E2 ")) { + init_pll(&ddr3a_400); + if (cpu_revision() > 0) { + if (cpu_revision() > 1) { + /* PG 2.0 */ + /* Reset DDR3A PHY after PLL enabled */ + ddr3_reset_ddrphy(); + ddr3phy_1600_8g.zq0cr1 |= 0x10000; + ddr3phy_1600_8g.zq1cr1 |= 0x10000; + ddr3phy_1600_8g.zq2cr1 |= 0x10000; + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, + &ddr3phy_1600_8g); + } else { + /* PG 1.1 */ + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, + &ddr3phy_1600_8g); + } + + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, + &ddr3_1600_8g); + printf("DRAM: Capacity 8 GiB (includes reported below)\n"); + } else { + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1600_8g); + ddr3_1600_8g.sdcfg |= 0x1000; + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, + &ddr3_1600_8g); + printf("DRAM: Capacity 4 GiB (includes reported below)\n"); + } + } else if (!strcmp(dimm_name, "SQR-SD3T-2G1333SED")) { + init_pll(&ddr3a_333); + if (cpu_revision() > 0) { + if (cpu_revision() > 1) { + /* PG 2.0 */ + /* Reset DDR3A PHY after PLL enabled */ + ddr3_reset_ddrphy(); + ddr3phy_1333_2g.zq0cr1 |= 0x10000; + ddr3phy_1333_2g.zq1cr1 |= 0x10000; + ddr3phy_1333_2g.zq2cr1 |= 0x10000; + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, + &ddr3phy_1333_2g); + } else { + /* PG 1.1 */ + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, + &ddr3phy_1333_2g); + } + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, + &ddr3_1333_2g); + } else { + ddr3_init_ddrphy(KS2_DDR3A_DDRPHYC, &ddr3phy_1333_2g); + ddr3_1333_2g.sdcfg |= 0x1000; + ddr3_init_ddremif(KS2_DDR3A_EMIF_CTRL_BASE, + &ddr3_1333_2g); + } + } else { + printf("Unknown SO-DIMM. Cannot configure DDR3\n"); + while (1) + ; + } +} |
