diff options
Diffstat (limited to 'board/mcc200/mcc200.c')
| -rw-r--r-- | board/mcc200/mcc200.c | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c index 167dc0f846..5d74bdeb42 100644 --- a/board/mcc200/mcc200.c +++ b/board/mcc200/mcc200.c @@ -27,6 +27,7 @@ #include <common.h> #include <mpc5xxx.h> #include <pci.h> +#include <asm/processor.h> /* Two MT48LC8M32B2 for 32 MB */ /* #include "mt48lc8m32b2-6-7.h" */ @@ -98,6 +99,7 @@ long int initdram (int board_type) { ulong dramsize = 0; ulong dramsize2 = 0; + uint svr, pvr; #ifndef CFG_RAMBOOT ulong test1, test2; @@ -192,17 +194,39 @@ long int initdram (int board_type) #endif /* CFG_RAMBOOT */ + /* + * On MPC5200B we need to set the special configuration delay in the + * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM + * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: + * + * "The SDelay should be written to a value of 0x00000004. It is + * required to account for changes caused by normal wafer processing + * parameters." + */ + svr = get_svr(); + pvr = get_pvr(); + if ((SVR_MJREV(svr) >= 2) && (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { + *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04; + __asm__ volatile ("sync"); + } + return dramsize + dramsize2; } int checkboard (void) { +#if defined(CONFIG_PRS200) + puts ("Board: PRS200\n"); +#else puts ("Board: MCC200\n"); +#endif return 0; } int misc_init_r (void) { + ulong flash_sup_end, snum; + /* * Adjust flash start and offset to detected values */ @@ -257,6 +281,12 @@ int misc_init_r (void) (flash_info[0].start[0] - 1) + flash_info[0].size, &flash_info[0]); *(volatile int*)MPC5XXX_CS0_CFG &= ~(1 << 6); + printf ("Warning: Only 32 of 64 MB of Flash are accessible from U-Boot\n"); + flash_info[0].size = 32 << 20; + for (snum = 0, flash_sup_end = gd->bd->bi_flashstart + (32<<20); + flash_info[0].start[snum] < flash_sup_end; + snum++); + flash_info[0].sector_count = snum; } return (0); |
