diff options
Diffstat (limited to 'board/exbitgen/init.S')
| -rw-r--r-- | board/exbitgen/init.S | 296 |
1 files changed, 148 insertions, 148 deletions
diff --git a/board/exbitgen/init.S b/board/exbitgen/init.S index 96b0abae1b..0e6cd04ba8 100644 --- a/board/exbitgen/init.S +++ b/board/exbitgen/init.S @@ -34,7 +34,7 @@ #include <asm/mmu.h> #include "exbitgen.h" - + /* IIC declarations (This is an extract from 405gp_i2c.h, which also contains some */ /* c-code declarations and consequently can't be included here). */ /* (Possibly to be solved somehow else). */ @@ -100,25 +100,25 @@ #define TIMEBASE_10PS (1000000000 / CONFIG_SYS_CLK_FREQ) * 100 #define FLASH_8bit_AP 0x9B015480 -#define FLASH_8bit_CR 0xFFF18000 /* 1MB(min), 8bit, R/W */ +#define FLASH_8bit_CR 0xFFF18000 /* 1MB(min), 8bit, R/W */ #define FLASH_32bit_AP 0x9B015480 #define FLASH_32bit_CR 0xFFE3C000 /* 2MB, 32bit, R/W */ #define WDCR_EBC(reg,val) addi r4,0,reg;\ - mtdcr ebccfga,r4;\ - addis r4,0,val@h;\ - ori r4,r4,val@l;\ - mtdcr ebccfgd,r4 + mtdcr ebccfga,r4;\ + addis r4,0,val@h;\ + ori r4,r4,val@l;\ + mtdcr ebccfgd,r4 /*--------------------------------------------------------------------- * Function: ext_bus_cntlr_init - * Description: Initializes the External Bus Controller for the external - * peripherals. IMPORTANT: For pass1 this code must run from + * Description: Initializes the External Bus Controller for the external + * peripherals. IMPORTANT: For pass1 this code must run from * cache since you can not reliably change a peripheral banks * timing register (pbxap) while running code from that bank. - * For ex., since we are running from ROM on bank 0, we can NOT + * For ex., since we are running from ROM on bank 0, we can NOT * execute the code that modifies bank 0 timings from ROM, so * we run it from cache. * Bank 0 - Boot flash @@ -126,63 +126,63 @@ * Bank 5 - CPLD * Bank 6 - not used * Bank 7 - Heathrow chip - *--------------------------------------------------------------------- + *--------------------------------------------------------------------- */ - .globl ext_bus_cntlr_init + .globl ext_bus_cntlr_init ext_bus_cntlr_init: - mflr r4 /* save link register */ - bl ..getAddr + mflr r4 /* save link register */ + bl ..getAddr ..getAddr: - mflr r3 /* get address of ..getAddr */ - mtlr r4 /* restore link register */ - addi r4,0,14 /* set ctr to 10; used to prefetch */ - mtctr r4 /* 10 cache lines to fit this function */ - /* in cache (gives us 8x10=80 instrctns) */ + mflr r3 /* get address of ..getAddr */ + mtlr r4 /* restore link register */ + addi r4,0,14 /* set ctr to 10; used to prefetch */ + mtctr r4 /* 10 cache lines to fit this function */ + /* in cache (gives us 8x10=80 instrctns) */ ..ebcloop: - icbt r0,r3 /* prefetch cache line for addr in r3 */ - addi r3,r3,32 /* move to next cache line */ - bdnz ..ebcloop /* continue for 10 cache lines */ + icbt r0,r3 /* prefetch cache line for addr in r3 */ + addi r3,r3,32 /* move to next cache line */ + bdnz ..ebcloop /* continue for 10 cache lines */ mflr r31 /* save link register */ - - /*----------------------------------------------------------- - * Delay to ensure all accesses to ROM are complete before changing + + /*----------------------------------------------------------- + * Delay to ensure all accesses to ROM are complete before changing * bank 0 timings. 200usec should be enough. - * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles - *----------------------------------------------------------- + * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles + *----------------------------------------------------------- */ addis r3,0,0x0 - ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ - mtctr r3 + ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ + mtctr r3 ..spinlp: - bdnz ..spinlp /* spin loop */ + bdnz ..spinlp /* spin loop */ - /*--------------------------------------------------------------- - * Memory Bank 0 (Boot Flash) initialization - *--------------------------------------------------------------- + /*--------------------------------------------------------------- + * Memory Bank 0 (Boot Flash) initialization + *--------------------------------------------------------------- */ WDCR_EBC(pb0ap, FLASH_32bit_AP) WDCR_EBC(pb0cr, 0xffe38000) /*pnc WDCR_EBC(pb0cr, FLASH_32bit_CR) */ - - /*--------------------------------------------------------------- - * Memory Bank 5 (CPLD) initialization - *--------------------------------------------------------------- + + /*--------------------------------------------------------------- + * Memory Bank 5 (CPLD) initialization + *--------------------------------------------------------------- */ WDCR_EBC(pb5ap, 0x01010040) /*jsa recommendation: WDCR_EBC(pb5ap, 0x00010040) */ WDCR_EBC(pb5cr, 0x10038000) - /*--------------------------------------------------------------- */ - /* Memory Bank 6 (not used) initialization */ - /*--------------------------------------------------------------- */ + /*--------------------------------------------------------------- */ + /* Memory Bank 6 (not used) initialization */ + /*--------------------------------------------------------------- */ WDCR_EBC(pb6cr, 0x00000000) /* Read HW ID to determine whether old H2 board or new generic CPU board */ addis r3, 0, HW_ID_ADDR@h ori r3, r3, HW_ID_ADDR@l - lbz r3,0x0000(r3) + lbz r3,0x0000(r3) cmpi 0, r3, 1 /* if (HW_ID==1) */ beq setup_h2evalboard /* then jump */ cmpi 0, r3, 2 /* if (HW_ID==2) */ @@ -191,9 +191,9 @@ ext_bus_cntlr_init: beq setup_genieboard /* then jump */ setup_genieboard: - /*--------------------------------------------------------------- */ - /* Memory Bank 1 (Application Flash) initialization for generic CPU board */ - /*--------------------------------------------------------------- */ + /*--------------------------------------------------------------- */ + /* Memory Bank 1 (Application Flash) initialization for generic CPU board */ + /*--------------------------------------------------------------- */ /* WDCR_EBC(pb1ap, 0x7b015480) /###* T.B.M. */ /* WDCR_EBC(pb1ap, 0x7F8FFE80) /###* T.B.M. */ WDCR_EBC(pb1ap, 0x9b015480) /* hlb-20020207: burst 8 bit 6 cycles */ @@ -201,68 +201,68 @@ setup_genieboard: /* WDCR_EBC(pb1cr, 0x20098000) /###* 16 MB */ WDCR_EBC(pb1cr, 0x200B8000) /* 32 MB */ - /*--------------------------------------------------------------- */ - /* Memory Bank 4 (Onboard FPGA) initialization for generic CPU board */ - /*--------------------------------------------------------------- */ + /*--------------------------------------------------------------- */ + /* Memory Bank 4 (Onboard FPGA) initialization for generic CPU board */ + /*--------------------------------------------------------------- */ WDCR_EBC(pb4ap, 0x01010000) /* */ WDCR_EBC(pb4cr, 0x1021c000) /* */ - /*--------------------------------------------------------------- */ - /* Memory Bank 7 (Heathrow chip on Reference board) initialization */ - /*--------------------------------------------------------------- */ + /*--------------------------------------------------------------- */ + /* Memory Bank 7 (Heathrow chip on Reference board) initialization */ + /*--------------------------------------------------------------- */ WDCR_EBC(pb7ap, 0x200ffe80) /* No Ready, many wait states (let reflections die out) */ WDCR_EBC(pb7cr, 0X4001A000) bl setup_continue - + setup_h2evalboard: - /*--------------------------------------------------------------- */ - /* Memory Bank 1 (Application Flash) initialization */ - /*--------------------------------------------------------------- */ + /*--------------------------------------------------------------- */ + /* Memory Bank 1 (Application Flash) initialization */ + /*--------------------------------------------------------------- */ WDCR_EBC(pb1ap, 0x7b015480) /* T.B.M. */ /*3010 WDCR_EBC(pb1ap, 0x7F8FFE80) /###* T.B.M. */ - WDCR_EBC(pb1cr, 0x20058000) + WDCR_EBC(pb1cr, 0x20058000) - /*--------------------------------------------------------------- */ - /* Memory Bank 2 (Application Flash) initialization */ - /*--------------------------------------------------------------- */ + /*--------------------------------------------------------------- */ + /* Memory Bank 2 (Application Flash) initialization */ + /*--------------------------------------------------------------- */ WDCR_EBC(pb2ap, 0x7b015480) /* T.B.M. */ /*3010 WDCR_EBC(pb2ap, 0x7F8FFE80) /###* T.B.M. */ - WDCR_EBC(pb2cr, 0x20458000) + WDCR_EBC(pb2cr, 0x20458000) /*--------------------------------------------------------------- */ - /* Memory Bank 3 (Application Flash) initialization */ - /*--------------------------------------------------------------- */ + /* Memory Bank 3 (Application Flash) initialization */ + /*--------------------------------------------------------------- */ WDCR_EBC(pb3ap, 0x7b015480) /* T.B.M. */ /*3010 WDCR_EBC(pb3ap, 0x7F8FFE80) /###* T.B.M. */ - WDCR_EBC(pb3cr, 0x20858000) + WDCR_EBC(pb3cr, 0x20858000) - /*--------------------------------------------------------------- */ - /* Memory Bank 4 (Application Flash) initialization */ - /*--------------------------------------------------------------- */ + /*--------------------------------------------------------------- */ + /* Memory Bank 4 (Application Flash) initialization */ + /*--------------------------------------------------------------- */ WDCR_EBC(pb4ap, 0x7b015480) /* T.B.M. */ /*3010 WDCR_EBC(pb4ap, 0x7F8FFE80) /###* T.B.M. */ WDCR_EBC(pb4cr, 0x20C58000) - /*--------------------------------------------------------------- */ - /* Memory Bank 7 (Heathrow chip) initialization */ - /*--------------------------------------------------------------- */ + /*--------------------------------------------------------------- */ + /* Memory Bank 7 (Heathrow chip) initialization */ + /*--------------------------------------------------------------- */ WDCR_EBC(pb7ap, 0x02000280) /* No Ready, 4 wait states */ WDCR_EBC(pb7cr, 0X4001A000) setup_continue: - - mtlr r31 /* restore lr */ + + mtlr r31 /* restore lr */ nop /* pass2 DCR errata #8 */ - blr + blr /*--------------------------------------------------------------------- */ /* Function: sdram_init */ /* Description: Configures SDRAM memory banks. */ /*--------------------------------------------------------------------- */ - .globl sdram_init + .globl sdram_init sdram_init: #if CFG_MONITOR_BASE < CFG_FLASH_BASE @@ -377,12 +377,12 @@ sdram_init: subf r5, r6, r17 or r4, r4, r5 - /*----------------------------------------------------------- */ - /* Set SDTR1 */ - /*----------------------------------------------------------- */ - addi r5,0,mem_sdtr1 - mtdcr memcfga,r5 - mtdcr memcfgd,r4 + /*----------------------------------------------------------- */ + /* Set SDTR1 */ + /*----------------------------------------------------------- */ + addi r5,0,mem_sdtr1 + mtdcr memcfga,r5 + mtdcr memcfgd,r4 /*----------------------------------------------------------- */ /* */ @@ -444,36 +444,36 @@ b1skip: addi r7,0,mem_mb2cf addi r7,0,mem_mb3cf mtdcr memcfga,r7 mtdcr memcfgd,r6 -b3skip: +b3skip: - /*----------------------------------------------------------- */ - /* Set RTR */ - /*----------------------------------------------------------- */ + /*----------------------------------------------------------- */ + /* Set RTR */ + /*----------------------------------------------------------- */ cmpi 0, r30, 1600 bge rtr_1 - addis r7, 0, 0x05F0 /* RTR value for 100Mhz */ + addis r7, 0, 0x05F0 /* RTR value for 100Mhz */ bl rtr_2 rtr_1: addis r7, 0, 0x03F8 rtr_2: addi r4,0,mem_rtr mtdcr memcfga,r4 mtdcr memcfgd,r7 - /*----------------------------------------------------------- */ - /* Delay to ensure 200usec have elapsed since reset. Assume worst */ - /* case that the core is running 200Mhz: */ - /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */ - /*----------------------------------------------------------- */ - addis r3,0,0x0000 - ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ - mtctr r3 + /*----------------------------------------------------------- */ + /* Delay to ensure 200usec have elapsed since reset. Assume worst */ + /* case that the core is running 200Mhz: */ + /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */ + /*----------------------------------------------------------- */ + addis r3,0,0x0000 + ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ + mtctr r3 ..spinlp2: - bdnz ..spinlp2 /* spin loop */ + bdnz ..spinlp2 /* spin loop */ - /*----------------------------------------------------------- */ - /* Set memory controller options reg, MCOPT1. */ + /*----------------------------------------------------------- */ + /* Set memory controller options reg, MCOPT1. */ /* Set DC_EN to '1' and BRD_PRF to '01' for 16 byte PLB Burst */ /* read/prefetch. */ - /*----------------------------------------------------------- */ + /*----------------------------------------------------------- */ addi r4,0,mem_mcopt1 mtdcr memcfga,r4 addis r4,0,0x80C0 /* set DC_EN=1 */ @@ -481,13 +481,13 @@ rtr_2: addi r4,0,mem_rtr mtdcr memcfgd,r4 - /*----------------------------------------------------------- */ - /* Delay to ensure 10msec have elapsed since reset. This is */ - /* required for the MPC952 to stabalize. Assume worst */ - /* case that the core is running 200Mhz: */ - /* 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles */ - /* This delay should occur before accessing SDRAM. */ - /*----------------------------------------------------------- */ + /*----------------------------------------------------------- */ + /* Delay to ensure 10msec have elapsed since reset. This is */ + /* required for the MPC952 to stabalize. Assume worst */ + /* case that the core is running 200Mhz: */ + /* 200,000,000 (cycles/sec) X .010 (sec) = 0x1E8480 cycles */ + /* This delay should occur before accessing SDRAM. */ + /*----------------------------------------------------------- */ addis r3,0,0x001E ori r3,r3,0x8480 /* ensure 10msec have passed since reset */ mtctr r3 @@ -501,8 +501,8 @@ rtr_2: addi r4,0,mem_rtr stb r4,0(r5) eieio - mtlr r31 /* restore lr */ - blr + mtlr r31 /* restore lr */ + blr /*--------------------------------------------------------------------- */ /* Function: read_spd */ @@ -512,21 +512,21 @@ rtr_2: addi r4,0,mem_rtr #define WRITE_I2C(reg,val) \ addi r3,0,val;\ - addis r4, 0, 0xef60;\ - ori r4, r4, 0x0500 + reg;\ - stb r3, 0(r4);\ - eieio + addis r4, 0, 0xef60;\ + ori r4, r4, 0x0500 + reg;\ + stb r3, 0(r4);\ + eieio #define READ_I2C(reg) \ - addis r3, 0, 0xef60;\ - ori r3, r3, 0x0500 + reg;\ - lbz r3, 0x0000(r3);\ - eieio + addis r3, 0, 0xef60;\ + ori r3, r3, 0x0500 + reg;\ + lbz r3, 0x0000(r3);\ + eieio read_spd: mflr r5 - + /* Initialize i2c */ /*--------------- */ WRITE_I2C(IICLMADR, 0x00) /* clear lo master address */ @@ -558,9 +558,9 @@ read_spd: /* Wait a little */ /*-------------- */ - addis r3,0,0x0000 - ori r3,r3,0xA000 - mtctr r3 + addis r3,0,0x0000 + ori r3,r3,0xA000 + mtctr r3 in02: bdnz in02 /* Issue write command */ @@ -572,12 +572,12 @@ in02: bdnz in02 /*--------------- */ addi r7, 0, 0 /* byte counter in r7 */ addi r8, 0, 0 /* checksum in r8 */ -rdlp: +rdlp: /* issue read command */ /*------------------- */ cmpi 0, r7, 127 blt rd01 - WRITE_I2C(IICCNTL, IIC_CNTL_READ | IIC_CNTL_PT) + WRITE_I2C(IICCNTL, IIC_CNTL_READ | IIC_CNTL_PT) bl rd02 rd01: WRITE_I2C(IICCNTL, IIC_CNTL_READ | IIC_CNTL_CHT | IIC_CNTL_PT) rd02: bl wait_i2c_transfer_done @@ -585,46 +585,46 @@ rd02: bl wait_i2c_transfer_done /* Fetch byte from buffer */ /*----------------------- */ READ_I2C(IICMDBUF) - + /* Retrieve parameters that are going to be used during configuration. */ /* Save them in dedicated registers. */ /*------------------------------------------------------------ */ cmpi 0, r7, 3 /* Save byte 3 in r10 */ bne rd10 - addi r10, r3, 0 + addi r10, r3, 0 rd10: cmpi 0, r7, 4 /* Save byte 4 in r11 */ bne rd11 - addi r11, r3, 0 + addi r11, r3, 0 rd11: cmpi 0, r7, 5 /* Save byte 5 in r12 */ bne rd12 - addi r12, r3, 0 + addi r12, r3, 0 rd12: cmpi 0, r7, 17 /* Save byte 17 in r13 */ bne rd13 - addi r13, r3, 0 + addi r13, r3, 0 rd13: cmpi 0, r7, 18 /* Save byte 18 in r14 */ bne rd14 - addi r14, r3, 0 + addi r14, r3, 0 rd14: cmpi 0, r7, 31 /* Save byte 31 in r15 */ bne rd15 - addi r15, r3, 0 + addi r15, r3, 0 rd15: cmpi 0, r7, 27 /* Save byte 27 in r16 */ bne rd16 - addi r16, r3, 0 + addi r16, r3, 0 rd16: cmpi 0, r7, 29 /* Save byte 29 in r17 */ bne rd17 - addi r17, r3, 0 + addi r17, r3, 0 rd17: cmpi 0, r7, 30 /* Save byte 30 in r18 */ bne rd18 - addi r18, r3, 0 + addi r18, r3, 0 rd18: cmpi 0, r7, 9 /* Save byte 9 in r19 */ bne rd19 - addi r19, r3, 0 + addi r19, r3, 0 rd19: cmpi 0, r7, 23 /* Save byte 23 in r20 */ bne rd20 - addi r20, r3, 0 + addi r20, r3, 0 rd20: cmpi 0, r7, 25 /* Save byte 25 in r21 */ bne rd21 - addi r21, r3, 0 + addi r21, r3, 0 rd21: /* Calculate checksum of the first 63 bytes */ @@ -647,16 +647,16 @@ rd30: andi. r8, r8, 0xff /* use only 8 bits */ eieio rderr: bl rderr -rd31: - +rd31: + /* Increment byte counter and check whether all bytes have been read. */ /*------------------------------------------------------------------- */ addi r7, r7, 1 cmpi 0, r7, 127 bgt rd05 bl rdlp -rd05: - mtlr r5 /* restore lr */ +rd05: + mtlr r5 /* restore lr */ blr wait_i2c_transfer_done: @@ -664,8 +664,8 @@ wait_i2c_transfer_done: wt01: READ_I2C(IICSTS) andi. r4, r3, IIC_STS_PT cmpi 0, r4, IIC_STS_PT - beq wt01 - mtlr r6 /* restore lr */ + beq wt01 + mtlr r6 /* restore lr */ blr /*--------------------------------------------------------------------- */ @@ -696,7 +696,7 @@ fm01: cmpi 0, r10, 11 cmpi 0, r13, 2 bne fm02 addi r3, 0, 1 - bl fmfound + bl fmfound fm02: cmpi 0, r10, 12 bne fm03 @@ -815,7 +815,7 @@ fm14: cmpi 0, r10, 13 addi r3, 0, 7 bl fmfound -fm15: +fm15: /* not found, error code to be issued on LEDs */ addi r7, 0, LED_SDRAM_CODE_2 addis r6, 0, 0x1000 @@ -827,7 +827,7 @@ fmerr: bl fmerr fmfound:addi r6, 0, 1 subf r3, r6, r3 - mtlr r5 /* restore lr */ + mtlr r5 /* restore lr */ blr /*--------------------------------------------------------------------- */ @@ -838,13 +838,13 @@ fmfound:addi r6, 0, 1 find_size_code: mflr r5 - + addi r3, r15, 0 /* density */ addi r7, 0, 0 fs01: andi. r6, r3, 0x01 cmpi 0, r6, 1 beq fs04 - + addi r7, r7, 1 cmpi 0, r7, 7 bge fs02 @@ -866,7 +866,7 @@ fs04: addi r3, r7, 0 addi r6, 0, 1 subf r3, r6, r3 fs05: - mtlr r5 /* restore lr */ + mtlr r5 /* restore lr */ blr /*--------------------------------------------------------------------- */ @@ -895,9 +895,9 @@ fc01: srw r6, r14, r4 /* */ addi r7, r19, 0 /* SDRAM cycle time for highest CAS latenty */ bl fc03 -fc02: +fc02: addi r7, r20, 0 /* SDRAM cycle time for next-highest CAS latenty */ -fc03: +fc03: addi r8, r7, 0 addi r9, 0, 4 srw r7, r7, r9 @@ -910,7 +910,7 @@ fc03: bgt fc05 addi r3, r2, 0 bl fc05 -fc04: +fc04: addi r7, r21, 0 /* SDRAM cycle time for third-highest CAS latenty */ addi r8, r7, 0 addi r9, 0, 2 @@ -933,9 +933,9 @@ fc06: addi r6, 0, 1 cmpi 0, r4, 0 bne fc01 -fc07: +fc07: - mtlr r5 /* restore lr */ + mtlr r5 /* restore lr */ blr #endif @@ -1000,7 +1000,7 @@ fc07: /* Size: 2 MB */ /* Usage: read/write */ /* Width: 32 bit */ - + /* Walnut fpga pb7ap */ /* 0 1 8 1 5 2 8 0 */ /* 0 + 00000 + 011 + 000 + 00 + 01 + 01 + 01 + 001 + 0 + 1 + 0 + 0 + 00000 */ |
