diff options
Diffstat (limited to 'board/altera/cyclone5-socdk/qts/sequencer_defines.h')
| -rw-r--r-- | board/altera/cyclone5-socdk/qts/sequencer_defines.h | 35 |
1 files changed, 0 insertions, 35 deletions
diff --git a/board/altera/cyclone5-socdk/qts/sequencer_defines.h b/board/altera/cyclone5-socdk/qts/sequencer_defines.h index bfe5b2719f..27ace02d55 100644 --- a/board/altera/cyclone5-socdk/qts/sequencer_defines.h +++ b/board/altera/cyclone5-socdk/qts/sequencer_defines.h @@ -12,39 +12,20 @@ #define AC_ROM_MR2_MIRR 0000000010000 #define AC_ROM_MR3_MIRR 0000000000000 #define AC_ROM_MR0_CALIB -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define AC_ROM_MR0_DLL_RESET_MIRR 0100011001000 -#define AC_ROM_MR0_DLL_RESET 0100100110000 -#define AC_ROM_MR0_MIRR 0100001001001 -#define AC_ROM_MR0 0100000110001 -#else #define AC_ROM_MR0_DLL_RESET_MIRR 0010011001000 #define AC_ROM_MR0_DLL_RESET 0010100110000 #define AC_ROM_MR0_MIRR 0010001001001 #define AC_ROM_MR0 0010000110001 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ #define AC_ROM_MR1 0000000000100 #define AC_ROM_MR2 0000000001000 #define AC_ROM_MR3 0000000000000 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define AFI_CLK_FREQ 534 -#else #define AFI_CLK_FREQ 401 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ #define AFI_RATE_RATIO 1 #define AVL_CLK_FREQ 67 #define BFM_MODE 0 #define BURST2 0 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define CALIB_LFIFO_OFFSET 8 -#define CALIB_VFIFO_OFFSET 6 -#else #define CALIB_LFIFO_OFFSET 7 #define CALIB_VFIFO_OFFSET 5 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ #define ENABLE_EXPORT_SEQ_DEBUG_BRIDGE 0 #define ENABLE_SUPER_QUICK_CALIBRATION 0 #define GUARANTEED_READ_BRINGUP_TEST 0 @@ -54,23 +35,12 @@ #define HR_DDIO_OUT_HAS_THREE_REGS 0 #define IO_DELAY_PER_DCHAIN_TAP 25 #define IO_DELAY_PER_DQS_EN_DCHAIN_TAP 25 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define IO_DELAY_PER_OPA_TAP 234 -#else #define IO_DELAY_PER_OPA_TAP 312 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ #define IO_DLL_CHAIN_LENGTH 8 #define IO_DM_OUT_RESERVE 0 #define IO_DQDQS_OUT_PHASE_MAX 0 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define IO_DQS_EN_DELAY_MAX 15 -#define IO_DQS_EN_DELAY_OFFSET 16 -#else #define IO_DQS_EN_DELAY_MAX 31 #define IO_DQS_EN_DELAY_OFFSET 0 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ #define IO_DQS_EN_PHASE_MAX 7 #define IO_DQS_IN_DELAY_MAX 31 #define IO_DQS_IN_RESERVE 4 @@ -84,12 +54,7 @@ #define MAX_LATENCY_COUNT_WIDTH 5 #define MEM_ADDR_WIDTH 13 #define READ_VALID_FIFO_SIZE 16 -#ifdef CONFIG_SOCFPGA_ARRIA5 -/* The if..else... is not required if generated by tools */ -#define REG_FILE_INIT_SEQ_SIGNATURE 0x5555048c -#else #define REG_FILE_INIT_SEQ_SIGNATURE 0x55550483 -#endif /* CONFIG_SOCFPGA_ARRIA5 */ #define RW_MGR_MEM_ADDRESS_MIRRORING 0 #define RW_MGR_MEM_ADDRESS_WIDTH 15 #define RW_MGR_MEM_BANK_WIDTH 3 |
