diff options
Diffstat (limited to 'board/RPXlite')
| -rw-r--r-- | board/RPXlite/Makefile | 8 | ||||
| -rw-r--r-- | board/RPXlite/README | 877 | ||||
| -rw-r--r-- | board/RPXlite/README.PlanetCore | 163 | ||||
| -rw-r--r-- | board/RPXlite/RPXlite.c | 149 | ||||
| -rw-r--r-- | board/RPXlite/flash.c | 508 | ||||
| -rw-r--r-- | board/RPXlite/u-boot.lds | 82 | ||||
| -rw-r--r-- | board/RPXlite/u-boot.lds.debug | 121 |
7 files changed, 0 insertions, 1908 deletions
diff --git a/board/RPXlite/Makefile b/board/RPXlite/Makefile deleted file mode 100644 index c17cbacf32..0000000000 --- a/board/RPXlite/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2000-2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = RPXlite.o flash.o diff --git a/board/RPXlite/README b/board/RPXlite/README deleted file mode 100644 index 3ca671126d..0000000000 --- a/board/RPXlite/README +++ /dev/null @@ -1,877 +0,0 @@ -# Porting U-Boot onto RPXlite board -# Written by Yoo. Jonghoon -# E-Mail : yooth@ipone.co.kr -# IP ONE Inc. - -# Since 2001. 1. 29 - -# Shell : bash -# Cross-compile tools : Montavista Hardhat -# Debugging tools : Windriver VisionProbe (PowerPC BDM) -# ppcboot ver. : ppcboot-0.8.1 - -############################################################### -# 1. Hardware setting -############################################################### - -1.1. Board, BDM settings - Install board, BDM, connect each other - -1.2. Save Register value - Boot with board-on monitor program and save the - register values with BDM. - -1.3. Configure flash programmer - Check flash memory area in the memory map. - 0xFFC00000 - 0xFFFFFFFF - - Boot monitor program is at - 0xFFF00000 - - You can program on-board flash memory with VisionClick - flash programmer. Set the target flash device as: - - 29DL800B - - (?) The flash memory device in the board *is* 29LV800B, - but I cannot program it with '29LV800B' option. - (in VisionClick flash programming tools) - I don't know why... - -1.4. Save boot monitor program *IMPORTANT* - Upload boot monitor program from board to file. - boot monitor program starts at 0xFFF00000 - -1.5. Test flash memory programming - Try to erase boot program in the flash memory, - and re-write them. - *WARNING* YOU MUST SAVE BOOT PROGRAM TO FILE - BEFORE ERASING FLASH - -############################################################### -# 2. U-Boot setting -############################################################### - -2.1. Download U-Boot tarball at - ftp://ftp.denx.de - (The latest version is ppcboot-0.8.1.tar.bz2) - - To extract the archive use the following syntax : - > bzip2 -cd ppcboot-0.8.1.tar.bz2 | tar xf - - -2.2. Add the following lines in '.profile' - export PATH=$PATH:/opt/hardhat/devkit/ppc/8xx/bin - -2.3. Make board specific config, for example: - > cd ppcboot-0.8.1 - > make TQM860L_config - - Now we can build ppcboot bin files. - After make all, you must see these files in your - ppcboot root directory. - - ppcboot - ppcboot.bin - ppcboot.srec - ppcboot.map - -2.4. Make your own board directory into the - ppcboot-0.8.1/board - and make your board-specific files here. - - For exmanple, tqm8xx files are composed of - .depend : Nothing - Makefile : To make config file - config.mk : Sets base address - flash.c : Flash memory control files - ppcboot.lds : linker(ld) script? (I don't know this yet) - tqm8xx.c : DRAM control and board check routines - - And, add your board config lines in the - ppcboot-0.8.1/Makefile - - Finally, add config_(your board).h file in the - ppcboot-0.8.1/include/ - - I've made board/rpxlite directory, and just copied - tqm8xx settings for now. - - Rebuild ppcboot for rpxlite board: - > make rpxlite_config - > make - -############################################################### -# 3. U-Boot porting -############################################################### - -3.1. My RPXlite files are based on tqm8xx board files. - > cd board - > cp -r tqm8xx RPXLITE - > cd RPXLITE - > mv tqm8xx.c RPXLITE.c - > cd ../../include - > cp config_tqm8xx.h config_RPXLITE.h - -3.2. Modified files are: - board/RPXLITE/RPXLITE.c /* DRAM-related routines */ - board/RPXLITE/flash.c /* flash-related routines */ - board/RPXLITE/config.mk /* set text base address */ - arch/powerpc/cpu/mpc8xx/serial.c /* board specific register setting */ - include/config_RPXLITE.h /* board specific registers */ - - See 'reg_config.txt' for register values in detail. - -############################################################### -# 4. Running Linux -############################################################### - - -############################################################### -# Misc Information -############################################################### - -mem_config.txt: -=============== - -Flash memory device : AM29LV800BB (1Mx8Bit) x 4 device -manufacturer id : 01 (AMD) -device id : 5B (AM29LV800B) -size : 4Mbyte -sector # : 19 - -Sector information : - -number start addr. size -00 FFC0_0000 64 -01 FFC1_0000 32 -02 FFC1_8000 32 -03 FFC2_0000 128 -04 FFC4_0000 256 -05 FFC8_0000 256 -06 FFCC_0000 256 -07 FFD0_0000 256 -08 FFD4_0000 256 -09 FFD8_0000 256 -10 FFDC_0000 256 -11 FFE0_0000 256 -12 FFE4_0000 256 -13 FFE8_0000 256 -14 FFEC_0000 256 -15 FFF0_0000 256 -16 FFF4_0000 256 -17 FFF8_0000 256 -18 FFFC_0000 256 - - -reg_config.txt: -=============== - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* SIU (System Interface Unit) */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ - - -/*### IMMR */ -/*### Internal Memory Map Register */ -/*### Chap. 11.4.1 */ - - ISB = 0xFA20 /* Set the Immap base = 0xFA20 0000 */ - PARTNUM = 0x21 - MASKNUM = 0x00 - - => 0xFA20 2100 - ---------------------------------------------------------------------- - -/*### SIUMCR */ -/*### SIU Module Configuration Register */ -/*### Chap. 11.4.2 */ -/*### Offset : 0x0000 0000 */ - - EARB = 0 - EARP = 0 - DSHW = 0 - DBGC = 0 - DBPC = 0 - FRC = 0 - DLK = 0 - OPAR = 0 - PNCS = 0 - DPC = 0 - MPRE = 0 - MLRC = 10 /* ~KR/~RETRY/~IRQ4/SPKROUT functions as ~KR/~TRTRY */ - AEME = 0 - SEME = 0 - BSC = 0 - GB5E = 0 - B2DD = 0 - B3DD = 0 - - => 0x0000 0800 - ---------------------------------------------------------------------- - -/*### SYPCR */ -/*### System Protection Control Register */ -/*### Chap. 11.4.3 */ -/*### Offset : 0x0000 0004 */ - - SWTC = 0xFFFF /* SW watchdog timer count = 0xFFFF */ - BMT = 0x06 /* BUS monitoring timing */ - BME = 1 /* BUS monitor enable */ - SWF = 1 - SWE = 0 /* SW watchdog disable */ - SWRI = 0 - SWP = 1 - - => 0xFFFF 0689 - ---------------------------------------------------------------------- - -/*### TESR */ -/*### Transfer Error Status Register */ -/*### Chap. 11.4.4 */ -/*### Offset : 0x0000 0020 */ - - IEXT = 0 - ITMT = 0 - IPB = 0000 - DEXT = 0 - DTMT = 0 - DPB = 0000 - - => 0x0000 0000 - ---------------------------------------------------------------------- - -/*### SIPEND */ -/*### SIU Interrupt Pending Register */ -/*### Chap. 11.5.4.1 */ -/*### Offset : 0x0000 0010 */ - - IRQ0~IRQ7 = 0 - LVL0~LVL7 = 0 - - => 0x0000 0000 - ---------------------------------------------------------------------- - -/*### SIMASK */ -/*### SIU Interrupt Mask Register */ -/*### Chap. 11.5.4.2 */ -/*### Offset : 0x0000 0014 */ - - IRM0~IRM7 = 0 /* Mask all interrupts */ - LVL0~LVL7 = 0 - - => 0x0000 0000 - ---------------------------------------------------------------------- - -/*### SIEL */ -/*### SIU Interrupt Edge/Level Register */ -/*### Chap. 11.5.4.3 */ -/*### Offset : 0x0000 0018 */ - - ED0~ED7 = 0 /* Low level triggered */ - WMn0~WMn7 = 0 /* Not allowed to exit from low-power mode */ - - => 0x0000 0000 - ---------------------------------------------------------------------- - -/*### SIVEC */ -/*### SIU Interrupt Vector Register */ -/*### Chap. 11.5.4.4 */ -/*### Offset : 0x0000 001C */ - - INTC = 3C /* The lowest interrupt is pending..(?) */ - - => 0x3C00 0000 - ---------------------------------------------------------------------- - -/*### SWSR */ -/*### Software Service Register */ -/*### Chap. 11.7.1 */ -/*### Offset : 0x0000 001E */ - - SEQ = 0 - - => 0x0000 - ---------------------------------------------------------------------- - -/*### SDCR */ -/*### SDMA Configuration Register */ -/*### Chap. 20.2.1 */ -/*### Offset : 0x0000 0032 */ - - FRZ = 0 - RAID = 01 /* Priority level 5 (BR5) (normal operation) */ - - => 0x0000 0001 - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* UPMA (User Programmable Machine A) */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ - -/*### Chap. 16.6.4.1 */ -/*### Offset = 0x0000 017c */ - - T0 = CFFF CC24 /* Single Read */ - T1 = 0FFF CC04 - T2 = 0CAF CC04 - T3 = 03AF CC08 - T4 = 3FBF CC27 /* last */ - T5 = FFFF CC25 - T6 = FFFF CC25 - T7 = FFFF CC25 - T8 = CFFF CC24 /* Burst Read */ - T9 = 0FFF CC04 - T10 = 0CAF CC84 - T11 = 03AF CC88 - T12 = 3FBF CC27 /* last */ - T13 = FFFF CC25 - T14 = FFFF CC25 - T15 = FFFF CC25 - T16 = FFFF CC25 - T17 = FFFF CC25 - T18 = FFFF CC25 - T19 = FFFF CC25 - T20 = FFFF CC25 - T21 = FFFF CC25 - T22 = FFFF CC25 - T23 = FFFF CC25 - T24 = CFFF CC24 /* Single Write */ - T25 = 0FFF CC04 - T26 = 0CFF CC04 - T27 = 03FF CC00 - T28 = 3FFF CC27 /* last */ - T29 = FFFF CC25 - T30 = FFFF CC25 - T31 = FFFF CC25 - T32 = CFFF CC24 /* Burst Write */ - T33 = 0FFF CC04 - T34 = 0CFF CC80 - T35 = 03FF CC8C - T36 = 0CFF CC00 - T37 = 33FF CC27 /* last */ - T38 = FFFF CC25 - T39 = FFFF CC25 - T40 = FFFF CC25 - T41 = FFFF CC25 - T42 = FFFF CC25 - T43 = FFFF CC25 - T44 = FFFF CC25 - T45 = FFFF CC25 - T46 = FFFF CC25 - T47 = FFFF CC25 - T48 = C0FF CC24 /* Refresh */ - T49 = 03FF CC24 - T50 = 0FFF CC24 - T51 = 0FFF CC24 - T52 = 3FFF CC27 /* last */ - T53 = FFFF CC25 - T54 = FFFF CC25 - T55 = FFFF CC25 - T56 = FFFF CC25 - T57 = FFFF CC25 - T58 = FFFF CC25 - T59 = FFFF CC25 - T60 = FFFF CC25 /* Exception */ - T61 = FFFF CC25 - T62 = FFFF CC25 - T63 = FFFF CC25 - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* UPMB */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ ---------------------------------------------------------------------- - -/*### Chap. 16.6.4.1 */ - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* MEMC */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ ---------------------------------------------------------------------- - -/*### BR0 & OR0 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR0(0x0000 0100) & OR0(0x0000 0104) */ -/*### Flash memory */ - - BA = 1111 1110 0000 0000 0 /* Base addr = 0xFE00 0000 */ - AT = 000 - PS = 00 - PARE = 0 - WP = 0 - MS = 0 /* GPCM */ - V = 1 /* Valid */ - - => 0xFE00 0001 - - AM = 1111 1110 0000 0000 0 /* 32MBytes */ - ATM = 000 - CSNT/SAM = 0 - ACS/G5LA,G5LS = 00 - BIH = 1 /* Burst inhibited */ - SCY = 0100 /* cycle length = 4 */ - SETA = 0 - TRLX = 0 - EHTR = 0 - - => 0xFE00 0140 - -/*### BR1 & OR1 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR1(0x0000 0108) & OR1(0x0000 010C) */ -/*### SDRAM */ - - BA = 0000 0000 0000 0000 0 /* Base addr = 0x0000 0000 */ - AT = 000 - PS = 00 - PARE = 0 - WP = 0 - MS = 1 /* UPMA */ - V = 1 /* Valid */ - - => 0x0000 0081 - - AM = 1111 1110 0000 0000 /* 32MBytes */ - ATM = 000 - CSNT/SAM = 1 - ACS/G5LA,G5LS = 11 - BIH = 0 - SCY = 0000 /* cycle length = 0 */ - SETA = 0 - TRLX = 0 - EHTR = 0 - - => 0xFE00 0E00 - -/*### BR2 & OR2 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR2(0x0000 0110) & OR2(0x0000 0114) */ - - BR2 & OR2 = 0x0000 0000 /* Not used */ - -/*### BR3 & OR3 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR3(0x0000 0118) & OR3(0x0000 011C) */ -/*### BCSR */ - - BA = 1111 1010 0100 0000 0 /* Base addr = 0xFA40 0000 */ - AT = 000 - PS = 00 - PARE = 0 - WP = 0 - MS = 0 /* GPCM */ - V = 1 /* Valid */ - - => 0xFA40 0001 - - AM = 1111 1111 0111 1111 1 /* (?) */ - ATM = 000 - CSNT/SAM = 1 - ACS/G5LA,G5LS = 00 - BIH = 1 /* Burst inhibited */ - SCY = 0001 /* cycle length = 1 */ - SETA = 0 - TRLX = 0 - - => 0xFF7F 8910 - -/*### BR4 & OR4 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR4(0x0000 0120) & OR4(0x0000 0124) */ -/*### NVRAM & SRAM */ - - BA = 1111 1010 0000 0000 0 /* Base addr = 0xFA00 0000 */ - AT = 000 - PS = 01 - PARE = 0 - WP = 0 - MS = 0 /* GPCM */ - V = 1 /* Valid */ - - => 0xFA00 0401 - - AM = 1111 1111 1111 1000 0 /* 8MByte */ - ATM = 000 - CSNT/SAM = 1 - ACS/G5LA,G5LS = 00 - BIH = 1 /* Burst inhibited */ - SCY = 0111 /* cycle length = 7 */ - SETA = 0 - TRLX = 0 - - => 0xFFF8 0970 - -/*### BR5 & OR5 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR2(0x0000 0128) & OR2(0x0000 012C) */ - - BR5 & OR5 = 0x0000 0000 /* Not used */ - -/*### BR6 & OR6 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR2(0x0000 0130) & OR2(0x0000 0134) */ - - BR6 & OR6 = 0x0000 0000 /* Not used */ - -/*### BR7 & OR7 */ -/*### Base Registers & Option Registers */ -/*### Chap. 16.4.1 & 16.4.2 */ -/*### Offset : BR7(0x0000 0138) & OR7(0x0000 013C) */ - - BR7 & OR7 = 0x0000 0000 /* Not used */ - -/*### MAR */ -/*### Memory Address Register */ -/*### Chap. 16.4.7 */ -/*### Offset : 0x0000 0164 */ - - MA = External memory address - -/*### MCR */ -/*### Memory Command Register */ -/*### Chap. 16.4.5 */ -/*### Offset : 0x0000 0168 */ - - OP = xx /* Command op code */ - UM = 1 /* Select UPMA */ - MB = 001 /* Select CS1 */ - MCLF = xxxx /* Loop times */ - MAD = xx xxxx /* Memory array index */ - -/*### MAMR */ -/*### Machine A Mode Register */ -/*### Chap. 16.4.4 */ -/*### Offset : 0x0000 0170 */ - - PTA = 0101 1000 - PTAE = 1 /* Periodic timer A enabled */ - AMA = 010 - DSA = 00 - G0CLA = 000 - GPLA4DIS = 1 - RLFA = 0100 - WLFA = 0011 - TLFA = 0000 - - => 0x58A0 1430 - -/*### MBMR */ -/*### Machine B Mode Register */ -/*### Chap. 16.4.4 */ -/*### Offset : 0x0000 0174 */ - - PTA = 0100 1110 - PTAE = 0 /* Periodic timer B disabled */ - AMA = 000 - DSA = 00 - G0CLA = 000 - GPLA4DIS = 1 - RLFA = 0000 - WLFA = 0000 - TLFA = 0000 - - => 0x4E00 1000 - -/*### MSTAT */ -/*### Memory Status Register */ -/*### Chap. 16.4.3 */ -/*### Offset : 0x0000 0178 */ - - PER0~PER7 = Parity error - WPER = Write protection error - - => 0x0000 - -/*### MPTPR */ -/*### Memory Periodic Timer Prescaler Register */ -/*### Chap. 16.4.8 */ -/*### Offset : 0x0000 017A */ - - PTP = 0000 1000 /* Divide by 8 */ - - => 0x0800 - -/*### MDR */ -/*### Memory Data Register */ -/*### Chap. 16.4.6 */ -/*### Offset : 0x0000 017C */ - - MD = Memory data contains the RAM array word - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* TIMERS */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ ---------------------------------------------------------------------- - -/*### TBREFx */ -/*### Timebase Reference Registers */ -/*### Chap. 11.9.2 */ -/*### Offset : TBREFF0(0x0000 0204)/TBREFF1(0x0000 0208) */ -/*### (Locked) */ - - TBREFF0 = 0xFFFF FFFF - TBREFF1 = 0xFFFF FFFF - ---------------------------------------------------------------------- - -/*### TBSCR */ -/*### Timebase Status and Control Registers */ -/*### Chap. 11.9.3 */ -/*### Offset : 0x0000 0200 */ -/*### (Locked) */ - - TBIRQ = 00000000 - REF0 = 0 - REF1 = 0 - REFE0 = 0 /* Reference interrupt disable */ - REFE1 = 0 - TBF = 1 - TBE = 1 /* Timebase enable */ - - => 0x0003 - ---------------------------------------------------------------------- - -/*### RTCSC */ -/*### Real-Time Clock Status and Control Registers */ -/*### Chap. 11.10.1 */ -/*### Offset : 0x0000 0220 */ -/*### (Locked) */ - - RTCIRQ = 00000000 - SEC = 1 - ALR = 0 - 38K = 0 /* PITRTCLK is driven by 32.768KHz */ - SIE = 0 - ALE = 0 - RTF = 0 - RTE = 1 /* Real-Time clock enabled */ - - => 0x0081 - ---------------------------------------------------------------------- - -/*### RTC */ -/*### Real-Time Clock Registers */ -/*### Chap. 11.10.2 */ -/*### Offset : 0x0000 0224 */ -/*### (Locked) */ - - RTC = Real time clock measured in second - ---------------------------------------------------------------------- - -/*### RTCAL */ -/*### Real-Time Clock Alarm Registers */ -/*### Chap. 11.10.3 */ -/*### Offset : 0x0000 022C */ -/*### (Locked) */ - - ALARM = 0xFFFF FFFF - ---------------------------------------------------------------------- - -/*### RTSEC */ -/*### Real-Time Clock Alarm Second Registers */ -/*### Chap. 11.10.4 */ -/*### Offset : 0x0000 0228 */ -/*### (Locked) */ - - COUNTER = Counter bits(fraction of a second) - ---------------------------------------------------------------------- - -/*### PISCR */ -/*### Periodic Interrupt Status and Control Register */ -/*### Chap. 11.11.1 */ -/*### Offset : 0x0000 0240 */ -/*### (Locked) */ - - PIRQ = 0 - PS = 0 /* Write 1 to clear */ - PIE = 0 - PITF = 1 - PTE = 0 /* PIT disabled */ - ---------------------------------------------------------------------- - -/*### PITC */ -/*### PIT Count Register */ -/*### Chap. 11.11.2 */ -/*### Offset : 0x0000 0244 */ -/*### (Locked) */ - - PITC = PIT count - ---------------------------------------------------------------------- - -/*### PITR */ -/*### PIT Register */ -/*### Chap. 11.11.3 */ -/*### Offset : 0x0000 0248 */ -/*### (Locked) */ - - PIT = PIT count /* Read only */ - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* CLOCKS */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ ---------------------------------------------------------------------- - - ---------------------------------------------------------------------- - -/*### SCCR */ -/*### System Clock and Reset Control Register */ -/*### Chap. 15.6.1 */ -/*### Offset : 0x0000 0280 */ -/*### (Locked) */ - - COM = 11 /* Clock output disabled */ - TBS = 1 /* Timebase frequency source is GCLK2 divided by 16 */ - RTDIV = 0 /* The clock is divided by 4 */ - RTSEL = 0 /* OSCM(Crystal oscillator) is selected */ - CRQEN = 0 - PRQEN = 0 - EBDF = 00 /* CLKOUT is GCLK2 divided by 1 */ - DFSYNC = 00 /* Divided by 1 (normal operation) */ - DFBRG = 00 /* Divided by 1 (normal operation) */ - DFNL = 000 - DFNH = 000 - - => 0x6200 0000 - ---------------------------------------------------------------------- - -/*### PLPRCR */ -/*### PLL, Low-Power, and Reset Control Register */ -/*### Chap. 15.6.2 */ -/*### Offset : 0x0000 0284 */ -/*### (Locked) */ - - MF = 0x005 /* 48MHz (?) ( = 8MHz * (MF+1) ) */ - SPLSS = 0 - TEXPS = 0 - TMIST = 0 - CSRC = 0 /* The general system clock is generated by the DFNH field */ - LPM = 00 /* Normal high/normal low mode */ - CSR = 0 - LOLRE = 0 - FIOPD = 0 - - => 0x0050 0000 - ---------------------------------------------------------------------- - -/*### RSR */ -/*### Reset Status Register */ -/*### Chap. 12.2 */ -/*### Offset : 0x0000 0288 */ -/*### (Locked) */ - - EHRS = External hard reset - ESRS = External soft reset - LLRS = Loss-of-lock reset - SWRS = Software watchdog reset - CSRS = Check stop reset - DBHRS = Debug port hard reset - DBSRS = Debug port soft reset - JTRS = JTAG reset - - -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ -/* DMA */ -/* */ -/*------------------------------------------------------------------- */ -/*------------------------------------------------------------------- */ ---------------------------------------------------------------------- - -/*### SDSR */ -/*### SDMA Status Register */ -/*### Chap. 20.2.2 */ -/*### Offset : 0x0000 0908 */ - - SBER = 0 /* SDMA channel bus error */ - DSP2 = 0 /* DSP chain2 (Tx) interrupt */ - DSP1 = 0 /* DSP chain1 (Rx) interrupt */ - - => 0x00 - -/*### SDMR */ -/*### SDMA Mask Register */ -/*### Chap. 20.2.3 */ -/*### Offset : 0x0000 090C */ - - SBER = 0 - DSP2 = 0 - DSP1 = 0 /* All interrupts are masked */ - - => 0x00 - -/*### SDAR */ -/*### SDMA Address Register */ -/*### Chap. 20.2.4 */ -/*### Offset : 0x0000 0904 */ - - AR = 0xxxxx xxxx /* current system address */ - - => 0xFA20 23AC - -/*### IDSRx */ -/*### IDMA Status Register */ -/*### Chap. 20.3.3.2 */ -/*### Offset : IDSR1(0x0000 0910) & IDSR2(0x0000 0918) */ - - AD = 0 - DONE = 0 - OB = 0 - - => 0x00 - -/*### IDMRx */ -/*### IDMA Mask Register */ -/*### Chap. 20.3.3.3 */ -/*### Offset : IDMR1(0x0000 0914) & IDMR2(0x0000 091C) */ - - AD = 0 - DONE = 0 - OB = 0 diff --git a/board/RPXlite/README.PlanetCore b/board/RPXlite/README.PlanetCore deleted file mode 100644 index b73c5f5a87..0000000000 --- a/board/RPXlite/README.PlanetCore +++ /dev/null @@ -1,163 +0,0 @@ -After several heart-struck failure, I got one workable way to program -each other in FLASH between PlanetCore and U-Boot. - -Hardware Platform : RPXlite DW(EP 823 H1 DW) - -1. From U-Boot to PlanetCore - -Utilities : PlanetCore Boot Loader - PCL200.mot - -[root@sam tftpboot]# ppc_8xx-objcopy -O ppcboot -PCL200.mot pcl200.bin - -[Target Operation] -u-boot>t 100000 pcl200.bin -u-boot>go 0x100000 -## Starting application at 0x00100000 ... - -MPC8xx PlanetCore Flash Burner v2.00 -Copyright 2001 Embedded Planet. All rights reserved. - -Construct Flash Device.....done. - - -Program MPC8xx PlanetCore Boot Loader v2.00 -Built Sep 19, 2001 at 14:34:42 -Image located from FC000000 to FC01B5D1. -(Skipping an image, only loading low boot image) - -Low boot board detected, skipping high boot image. -Erasing, programming and verifying will start in 20 -seconds -Press P to start immediately or ESC to cancel -Press Space or Enter for more options. -.............. - -Erasing -Programming -FLASH programmed successfully! -Press R to induce a hard reset - -MPC8xx PlanetCore Boot Loader v2.00 -Copyright 2001 Embedded Planet. All rights reserved. -DRAM available size = 64 MB -wvCV -DRAM OK -> - -2. From PlanetCore to U-Boot - -Utilities : PlanetCore FLASH Burner - PCB200.mot - -Use Flash Burner to finish the work: - -First, TFTP the U-Boot image file to RAM; For example, -RPXlite_DW.bin to 0x400000 -Second, TFTP FLASH Burner to RAM; For example, -0x100000 -Third, run the FLASH Burner and Program the U-Boot -image into the correct location in FLASH. - -[Target Operation] -MPC8xx PlanetCore Boot Loader v2.00 -Copyright 2001 Embedded Planet. All rights reserved. -DRAM available size = 64 MB -wvCV -DRAM OK ->t -Load using tftp via Ethernet -Enter server IP address <172.16.115.6> : -Enter server filename <PCL200.mot> : RPXlite_DW.bin -Enter (B)inary or (S)record input mode <S> : B -Enter address offset : <00400000 hex> : - -Total bytes = 120096 in 232184 uSecs -Loaded addresses 00400000 through 0041D51F. -Start address = 00400000 ->t -Load using tftp via Ethernet -Enter server IP address <172.16.115.6> : -Enter server filename <RPXlite_DW.bin> : PCB200.mot -Enter (B)inary or (S)record input mode <B> : S -Enter address offset : <00000000 hex> : -.512.1024..2048....4096..... -Total bytes = 326280 in 2570249 uSecs -Loaded addresses 00100000 through 0011BB51. -Start address = 00100000 ->go -[Go 00100000] - -MPC8xx PlanetCore Flash Burner v2.00 -Copyright 2001 Embedded Planet. All rights reserved. - -Construct Flash Device.....done. - -Bad start address -Start = 0xFFFFFFFF, target = 0xFFFFFFFF, length = -0xFFFFFFFF -Forcing Menu Interface - -h[elp] Show commands. -c[ode] Show information on code to be loaded. -di[splay] Display all flash sections. -du[mp] Dump memory. d ? for more info. -e[rase] Erase flash sections. -f[ill] Fill flash sections. -im[age] Toggle load high, low, or both flash -images. -in[fo] Show flash information. -ma[p] Show memory map. -mo[dify] Modify memory. m ? for more info. -p[rogram] Erase, program, and verify now. -reset Restart the loader. -s[how] Show flash sections to erase and program. -t[est] Test flash sections. -q[uit] Quit without programming. -#program 400000 ff000000 1D51F -doProgram( 400000 ff000000 1D51F ) - -Start = 0x00400000, target = 0xFF000000, length = -0x0001D51F -Erasing sector 0xFF000000, length 0x008000. -Erasing sector 0xFF008000, length 0x008000. -Erasing sector 0xFF010000, length 0x008000. -Erasing sector 0xFF018000, length 0x008000. -Programming FF000000 through FF01D51E -FLASH programmed successfully! -Press R to induce a hard reset - -Forcing Hard Reset by MachineCheck and -ResetOnCheckstop... - -U-Boot 1.1.2 (Aug 29 2004 - 15:11:27) - -CPU: PPC823EZTnnB2 at 48 MHz: 16 kB I-Cache 8 kB -D-Cache -Board: RPXlite_DW -DRAM: 64 MB -FLASH: 16 MB -*** Warning - bad CRC, using default environment - -In: serial -Out: serial -Err: serial -Net: SCC ETHERNET -u-boot> - -------------------------------------------------- - -Well, sometimes network function of PlanetCore couldn't work when -switching from U-Boot to PlanetCore. For example, you couldn't -download a file from HOST PC via TFTP. Don't worry, just restart your -HOST PC and everything would work as smooth as clockwork. I don't -know the reason WHY:-) - -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -Merry Christmas and Happy New Year! - -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -===== -Best regards, - -Sam diff --git a/board/RPXlite/RPXlite.c b/board/RPXlite/RPXlite.c deleted file mode 100644 index 08575a4930..0000000000 --- a/board/RPXlite/RPXlite.c +++ /dev/null @@ -1,149 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * U-Boot port on RPXlite board - * - * DRAM related UPMA register values are modified. - * See RPXLite engineering note : 50MHz/60ns - UPM RAM WORDS - */ - -#include <common.h> -#include <mpc8xx.h> - -/* ------------------------------------------------------------------------- */ - -static long int dram_size (long int, long int *, long int); - -/* ------------------------------------------------------------------------- */ - -#define _NOT_USED_ 0xFFFFCC25 - -const uint sdram_table[] = { - /* - * Single Read. (Offset 00h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0X0CAFCC04, 0X03AFCC08, - 0x3FBFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Read. (Offset 08h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0x0CAFCC84, 0x03AFCC88, - 0x3FBFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Single Write. (Offset 18h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC04, 0x03FFCC00, - 0x3FFFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Burst Write. (Offset 20h in UPMA RAM) - */ - 0xCFFFCC24, 0x0FFFCC04, 0x0CFFCC80, 0x03FFCC8C, - 0x0CFFCC00, 0x33FFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, - - /* - * Refresh. (Offset 30h in UPMA RAM) - */ - 0xC0FFCC24, 0x03FFCC24, 0x0FFFCC24, 0x0FFFCC24, - 0x3FFFCC27, /* last */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_, - _NOT_USED_, _NOT_USED_, _NOT_USED_, - - /* - * Exception. (Offset 3Ch in UPMA RAM) - */ - _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_ -}; - -/* ------------------------------------------------------------------------- */ - - -/* - * Check Board Identity: - */ - -int checkboard (void) -{ - puts ("Board: RPXlite\n"); - return (0); -} - -/* ------------------------------------------------------------------------- */ - -phys_size_t initdram (int board_type) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - long int size10; - - upmconfig (UPMA, (uint *) sdram_table, - sizeof (sdram_table) / sizeof (uint)); - - /* Refresh clock prescalar */ - memctl->memc_mptpr = CONFIG_SYS_MPTPR; - - memctl->memc_mar = 0x00000000; - - /* Map controller banks 1 to the SDRAM bank */ - memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM; - memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; - - memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE)); /* no refresh yet */ - - udelay (200); - - /* perform SDRAM initializsation sequence */ - - memctl->memc_mcr = 0x80002230; /* SDRAM bank 0 - refresh twice */ - udelay (1); - - memctl->memc_mamr |= MAMR_PTAE; /* enable refresh */ - - udelay (1000); - - /* Check Bank 0 Memory Size - * try 10 column mode - */ - - size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM, - SDRAM_MAX_SIZE); - - return (size10); -} - -/* ------------------------------------------------------------------------- */ - -/* - * Check memory range for valid RAM. A simple memory test determines - * the actually available RAM size between addresses `base' and - * `base + maxsize'. Some (not all) hardware errors are detected: - * - short between address lines - * - short between data lines - */ - -static long int dram_size (long int mamr_value, long int *base, - long int maxsize) -{ - volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR; - volatile memctl8xx_t *memctl = &immap->im_memctl; - - memctl->memc_mamr = mamr_value; - - return (get_ram_size (base, maxsize)); -} diff --git a/board/RPXlite/flash.c b/board/RPXlite/flash.c deleted file mode 100644 index 21b11d4e90..0000000000 --- a/board/RPXlite/flash.c +++ /dev/null @@ -1,508 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -/* - * Yoo. Jonghoon, IPone, yooth@ipone.co.kr - * U-Boot port on RPXlite board - * - * Some of flash control words are modified. (from 2x16bit device - * to 4x8bit device) - * RPXLite board I tested has only 4 AM29LV800BB devices. Other devices - * are not tested. - * - * (?) Does an RPXLite board which - * does not use AM29LV800 flash memory exist ? - * I don't know... - */ - -#include <common.h> -#include <mpc8xx.h> - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ - -/*----------------------------------------------------------------------- - * Functions - */ -static ulong flash_get_size (vu_long *addr, flash_info_t *info); -static int write_word (flash_info_t *info, ulong dest, ulong data); -static void flash_get_offsets (ulong base, flash_info_t *info); - -/*----------------------------------------------------------------------- - */ - -unsigned long flash_init (void) -{ -/* volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; */ -/* volatile memctl8xx_t *memctl = &immap->im_memctl; */ - unsigned long size_b0 ; - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) { - flash_info[i].flash_id = FLASH_UNKNOWN; - } - - /* Static FLASH Bank configuration here - FIXME XXX */ -/* - size_b0 = flash_get_size((vu_long *)FLASH_BASE_DEBUG, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) { - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size_b0, size_b0<<20); - } -*/ - /* Remap FLASH according to real size */ -/*%%% - memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000); - memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; -%%%*/ - /* Re-do sizing to get full correct info */ - - size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]); - flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]); - -#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE - /* monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, - CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1, - &flash_info[0]); -#endif - - flash_info[0].size = size_b0; - - return (size_b0); -} - -/*----------------------------------------------------------------------- - */ -static void flash_get_offsets (ulong base, flash_info_t *info) -{ - int i; - - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00010000; - info->start[2] = base + 0x00018000; - info->start[3] = base + 0x00020000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + ((i-3) * 0x00040000) ; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00010000; - info->start[i--] = base + info->size - 0x00018000; - info->start[i--] = base + info->size - 0x00020000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00040000; - } - } - -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t *info) -{ - int i; - - if (info->flash_id == FLASH_UNKNOWN) { - printf ("missing or unknown FLASH type\n"); - return; - } - - switch (info->flash_id & FLASH_VENDMASK) { - case FLASH_MAN_AMD: printf ("AMD "); break; - case FLASH_MAN_FUJ: printf ("FUJITSU "); break; - default: printf ("Unknown Vendor "); break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case FLASH_AM400B: printf ("AM29LV400B (4 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM400T: printf ("AM29LV400T (4 Mbit, top boot sector)\n"); - break; - case FLASH_AM800B: printf ("AM29LV800B (8 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM800T: printf ("AM29LV800T (8 Mbit, top boot sector)\n"); - break; - case FLASH_AM160B: printf ("AM29LV160B (16 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM160T: printf ("AM29LV160T (16 Mbit, top boot sector)\n"); - break; - case FLASH_AM320B: printf ("AM29LV320B (32 Mbit, bottom boot sect)\n"); - break; - case FLASH_AM320T: printf ("AM29LV320T (32 Mbit, top boot sector)\n"); - break; - default: printf ("Unknown Chip Type\n"); - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - printf (" Sector Start Addresses:"); - for (i=0; i<info->sector_count; ++i) { - if ((i % 5) == 0) - printf ("\n "); - printf (" %08lX%s", - info->start[i], - info->protect[i] ? " (RO)" : " " - ); - } - printf ("\n"); - return; -} - -/*----------------------------------------------------------------------- - */ - - -/*----------------------------------------------------------------------- - */ - -/* - * The following code cannot be run from FLASH! - */ - -static ulong flash_get_size (vu_long *addr, flash_info_t *info) -{ - short i; - ulong value; - ulong base = (ulong)addr; - - /* Write auto select command: read Manufacturer ID */ - addr[0xAAA] = 0x00AA00AA ; - addr[0x555] = 0x00550055 ; - addr[0xAAA] = 0x00900090 ; - - value = addr[0] ; - - switch (value & 0x00FF00FF) { - case AMD_MANUFACT: - info->flash_id = FLASH_MAN_AMD; - break; - case FUJ_MANUFACT: - info->flash_id = FLASH_MAN_FUJ; - break; - default: - info->flash_id = FLASH_UNKNOWN; - info->sector_count = 0; - info->size = 0; - return (0); /* no or unknown flash */ - } - - value = addr[2] ; /* device ID */ - - switch (value & 0x00FF00FF) { - case (AMD_ID_LV400T & 0x00FF00FF): - info->flash_id += FLASH_AM400T; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV400B & 0x00FF00FF): - info->flash_id += FLASH_AM400B; - info->sector_count = 11; - info->size = 0x00100000; - break; /* => 1 MB */ - - case (AMD_ID_LV800T & 0x00FF00FF): - info->flash_id += FLASH_AM800T; - info->sector_count = 19; - info->size = 0x00200000; - break; /* => 2 MB */ - - case (AMD_ID_LV800B & 0x00FF00FF): - info->flash_id += FLASH_AM800B; - info->sector_count = 19; - info->size = 0x00400000; /*%%% Size doubled by yooth */ - break; /* => 4 MB */ - - case (AMD_ID_LV160T & 0x00FF00FF): - info->flash_id += FLASH_AM160T; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ - - case (AMD_ID_LV160B & 0x00FF00FF): - info->flash_id += FLASH_AM160B; - info->sector_count = 35; - info->size = 0x00400000; - break; /* => 4 MB */ -#if 0 /* enable when device IDs are available */ - case AMD_ID_LV320T: - info->flash_id += FLASH_AM320T; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ - - case AMD_ID_LV320B: - info->flash_id += FLASH_AM320B; - info->sector_count = 67; - info->size = 0x00800000; - break; /* => 8 MB */ -#endif - default: - info->flash_id = FLASH_UNKNOWN; - return (0); /* => no or unknown flash */ - - } - /*%%% sector start address modified */ - /* set up sector start address table */ - if (info->flash_id & FLASH_BTYPE) { - /* set sector offsets for bottom boot block type */ - info->start[0] = base + 0x00000000; - info->start[1] = base + 0x00010000; - info->start[2] = base + 0x00018000; - info->start[3] = base + 0x00020000; - for (i = 4; i < info->sector_count; i++) { - info->start[i] = base + ((i-3) * 0x00040000) ; - } - } else { - /* set sector offsets for top boot block type */ - i = info->sector_count - 1; - info->start[i--] = base + info->size - 0x00010000; - info->start[i--] = base + info->size - 0x00018000; - info->start[i--] = base + info->size - 0x00020000; - for (; i >= 0; i--) { - info->start[i] = base + i * 0x00040000; - } - } - - /* check for protected sectors */ - for (i = 0; i < info->sector_count; i++) { - /* read sector protection at sector address, (A7 .. A0) = 0x02 */ - /* D0 = 1 if protected */ - addr = (volatile unsigned long *)(info->start[i]); - info->protect[i] = addr[4] & 1 ; - } - - /* - * Prevent writes to uninitialized FLASH. - */ - if (info->flash_id != FLASH_UNKNOWN) { - addr = (volatile unsigned long *)info->start[0]; - - *addr = 0xF0F0F0F0; /* reset bank */ - } - - return (info->size); -} - - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t *info, int s_first, int s_last) -{ - vu_long *addr = (vu_long*)(info->start[0]); - int flag, prot, sect, l_sect; - ulong start, now, last; - - if ((s_first < 0) || (s_first > s_last)) { - if (info->flash_id == FLASH_UNKNOWN) { - printf ("- missing\n"); - } else { - printf ("- no sectors to erase\n"); - } - return 1; - } - - if ((info->flash_id == FLASH_UNKNOWN) || - (info->flash_id > FLASH_AMD_COMP)) { - printf ("Can't erase unknown flash type %08lx - aborted\n", - info->flash_id); - return 1; - } - - prot = 0; - for (sect=s_first; sect<=s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - - if (prot) { - printf ("- Warning: %d protected sectors will not be erased!\n", - prot); - } else { - printf ("\n"); - } - - l_sect = -1; - - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - addr[0xAAA] = 0x80808080; - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect<=s_last; sect++) { - if (info->protect[sect] == 0) { /* not protected */ - addr = (vu_long *)(info->start[sect]) ; - addr[0] = 0x30303030 ; - l_sect = sect; - } - } - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* wait at least 80us - let's wait 1 ms */ - udelay (1000); - - /* - * We wait for the last triggered sector - */ - if (l_sect < 0) - goto DONE; - - start = get_timer (0); - last = start; - addr = (vu_long *)(info->start[l_sect]); - while ((addr[0] & 0x80808080) != 0x80808080) { - if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) { - printf ("Timeout\n"); - return 1; - } - /* show that we're waiting */ - if ((now - last) > 1000) { /* every second */ - putc ('.'); - last = now; - } - } - -DONE: - /* reset to read mode */ - addr = (vu_long *)info->start[0]; - addr[0] = 0xF0F0F0F0; /* reset bank */ - - printf (" done\n"); - return 0; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ - -int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt) -{ - ulong cp, wp, data; - int i, l, rc; - - wp = (addr & ~3); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i=0, cp=wp; i<l; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - for (; i<4 && cnt>0; ++i) { - data = (data << 8) | *src++; - --cnt; - ++cp; - } - for (; cnt==0 && i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - } - - /* - * handle word aligned part - */ - while (cnt >= 4) { - data = 0; - for (i=0; i<4; ++i) { - data = (data << 8) | *src++; - } - if ((rc = write_word(info, wp, data)) != 0) { - return (rc); - } - wp += 4; - cnt -= 4; - } - - if (cnt == 0) { - return (0); - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i=0, cp=wp; i<4 && cnt>0; ++i, ++cp) { - data = (data << 8) | *src++; - --cnt; - } - for (; i<4; ++i, ++cp) { - data = (data << 8) | (*(uchar *)cp); - } - - return (write_word(info, wp, data)); -} - -/*----------------------------------------------------------------------- - * Write a word to Flash, returns: - * 0 - OK - * 1 - write timeout - * 2 - Flash not erased - */ -static int write_word (flash_info_t *info, ulong dest, ulong data) -{ - vu_long *addr = (vu_long *)(info->start[0]); - ulong start; - int flag; - - /* Check if Flash is (sufficiently) erased */ - if ((*((vu_long *)dest) & data) != data) { - return (2); - } - /* Disable interrupts which might cause a timeout here */ - flag = disable_interrupts(); - - addr[0xAAA] = 0xAAAAAAAA; - addr[0x555] = 0x55555555; - addr[0xAAA] = 0xA0A0A0A0; - - *((vu_long *)dest) = data; - - /* re-enable interrupts if necessary */ - if (flag) - enable_interrupts(); - - /* data polling for D7 */ - start = get_timer (0); - while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) { - if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) { - return (1); - } - } - return (0); -} - -/*----------------------------------------------------------------------- - */ diff --git a/board/RPXlite/u-boot.lds b/board/RPXlite/u-boot.lds deleted file mode 100644 index 0eb2fba00c..0000000000 --- a/board/RPXlite/u-boot.lds +++ /dev/null @@ -1,82 +0,0 @@ -/* - * (C) Copyright 2000-2010 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) - -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .text : - { - arch/powerpc/cpu/mpc8xx/start.o (.text*) - arch/powerpc/cpu/mpc8xx/traps.o (.text*) - - *(.text*) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) - } - - /* Read-write section, merged into data segment: */ - . = (. + 0x00FF) & 0xFFFFFF00; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - _GOT2_TABLE_ = .; - KEEP(*(.got2)) - KEEP(*(.got)) - PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4); - _FIXUP_TABLE_ = .; - KEEP(*(.fixup)) - } - __got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data*) - *(.sdata*) - } - _edata = .; - PROVIDE (edata = .); - - . = .; - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - . = .; - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(256); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(256); - __init_end = .; - - __bss_start = .; - .bss (NOLOAD) : - { - *(.bss*) - *(.sbss*) - *(COMMON) - . = ALIGN(4); - } - __bss_end = . ; - PROVIDE (end = .); -} diff --git a/board/RPXlite/u-boot.lds.debug b/board/RPXlite/u-boot.lds.debug deleted file mode 100644 index b9c84c77d6..0000000000 --- a/board/RPXlite/u-boot.lds.debug +++ /dev/null @@ -1,121 +0,0 @@ -/* - * (C) Copyright 2000 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -OUTPUT_ARCH(powerpc) -/* Do we need any of these for elf? - __DYNAMIC = 0; */ -SECTIONS -{ - /* Read-only sections, merged into text segment: */ - . = + SIZEOF_HEADERS; - .interp : { *(.interp) } - .hash : { *(.hash) } - .dynsym : { *(.dynsym) } - .dynstr : { *(.dynstr) } - .rel.text : { *(.rel.text) } - .rela.text : { *(.rela.text) } - .rel.data : { *(.rel.data) } - .rela.data : { *(.rela.data) } - .rel.rodata : { *(.rel.rodata) } - .rela.rodata : { *(.rela.rodata) } - .rel.got : { *(.rel.got) } - .rela.got : { *(.rela.got) } - .rel.ctors : { *(.rel.ctors) } - .rela.ctors : { *(.rela.ctors) } - .rel.dtors : { *(.rel.dtors) } - .rela.dtors : { *(.rela.dtors) } - .rel.bss : { *(.rel.bss) } - .rela.bss : { *(.rela.bss) } - .rel.plt : { *(.rel.plt) } - .rela.plt : { *(.rela.plt) } - .init : { *(.init) } - .plt : { *(.plt) } - .text : - { - /* WARNING - the following is hand-optimized to fit within */ - /* the sector layout of our flash chips! XXX FIXME XXX */ - - arch/powerpc/cpu/mpc8xx/start.o (.text) - common/dlmalloc.o (.text) - lib/vsprintf.o (.text) - lib/crc32.o (.text) - - . = env_offset; - common/env_embedded.o(.text) - - *(.text) - *(.got1) - } - _etext = .; - PROVIDE (etext = .); - .rodata : - { - *(.rodata) - *(.rodata1) - *(.rodata.str1.4) - *(.eh_frame) - } - .fini : { *(.fini) } =0 - .ctors : { *(.ctors) } - .dtors : { *(.dtors) } - - /* Read-write section, merged into data segment: */ - . = (. + 0x0FFF) & 0xFFFFF000; - _erotext = .; - PROVIDE (erotext = .); - .reloc : - { - *(.got) - _GOT2_TABLE_ = .; - *(.got2) - _FIXUP_TABLE_ = .; - *(.fixup) - } - __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; - __fixup_entries = (. - _FIXUP_TABLE_)>>2; - - .data : - { - *(.data) - *(.data1) - *(.sdata) - *(.sdata2) - *(.dynamic) - CONSTRUCTORS - } - _edata = .; - PROVIDE (edata = .); - - - . = ALIGN(4); - .u_boot_list : { - KEEP(*(SORT(.u_boot_list*))); - } - - - __start___ex_table = .; - __ex_table : { *(__ex_table) } - __stop___ex_table = .; - - . = ALIGN(4096); - __init_begin = .; - .text.init : { *(.text.init) } - .data.init : { *(.data.init) } - . = ALIGN(4096); - __init_end = .; - - __bss_start = .; - .bss : - { - *(.sbss) *(.scommon) - *(.dynbss) - *(.bss) - *(COMMON) - } - __bss_end = . ; - PROVIDE (end = .); -} |
