diff options
Diffstat (limited to 'board/MAI/bios_emulator/scitech/src/pm/common')
6 files changed, 874 insertions, 876 deletions
diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/agp.c b/board/MAI/bios_emulator/scitech/src/pm/common/agp.c index 23f7e1e145..d53bc88e14 100644 --- a/board/MAI/bios_emulator/scitech/src/pm/common/agp.c +++ b/board/MAI/bios_emulator/scitech/src/pm/common/agp.c @@ -54,22 +54,22 @@ size of the available AGP aperture in megabytes. ulong PMAPI PM_agpInit(void) { if ((agp = AGP_loadDriver(0)) == NULL) - return 0; + return 0; driver.dwSize = sizeof(driver); if (!agp->QueryFunctions(AGP_GET_DRIVERFUNCS,&driver)) - return 0; + return 0; switch (driver.GetApertureSize()) { - case agpSize4MB: return 4; - case agpSize8MB: return 8; - case agpSize16MB: return 16; - case agpSize32MB: return 32; - case agpSize64MB: return 64; - case agpSize128MB: return 128; - case agpSize256MB: return 256; - case agpSize512MB: return 512; - case agpSize1GB: return 1024; - case agpSize2GB: return 2048; - } + case agpSize4MB: return 4; + case agpSize8MB: return 8; + case agpSize16MB: return 16; + case agpSize32MB: return 32; + case agpSize64MB: return 64; + case agpSize128MB: return 128; + case agpSize256MB: return 256; + case agpSize512MB: return 512; + case agpSize1GB: return 1024; + case agpSize2GB: return 2048; + } return 0; } @@ -106,18 +106,18 @@ ibool PMAPI PM_agpReservePhysical( PM_physAddr *physAddr) { switch (type) { - case PM_agpUncached: - type = agpUncached; - break; - case PM_agpWriteCombine: - type = agpWriteCombine; - break; - case PM_agpIntelDCACHE: - type = agpIntelDCACHE; - break; - default: - return false; - } + case PM_agpUncached: + type = agpUncached; + break; + case PM_agpWriteCombine: + type = agpWriteCombine; + break; + case PM_agpIntelDCACHE: + type = agpIntelDCACHE; + break; + default: + return false; + } return driver.ReservePhysical(numPages,type,physContext,physAddr) == nOK; } @@ -187,4 +187,3 @@ ibool PMAPI PM_agpFreePhysical( } #endif /* !REALMODE */ - diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/keyboard.c b/board/MAI/bios_emulator/scitech/src/pm/common/keyboard.c index 79b4040ac1..36867bdba7 100644 --- a/board/MAI/bios_emulator/scitech/src/pm/common/keyboard.c +++ b/board/MAI/bios_emulator/scitech/src/pm/common/keyboard.c @@ -52,18 +52,18 @@ static uchar translateScan( int n,pivot,val; for (n = count; n > 0; ) { - pivot = n >> 1; - test = table + pivot; - val = scanCode - test->scanCode; - if (val < 0) - n = pivot; - else if (val == 0) - return test->asciiCode; - else { - table = test + 1; - n -= pivot + 1; - } - } + pivot = n >> 1; + test = table + pivot; + val = scanCode - test->scanCode; + if (val < 0) + n = pivot; + else if (val == 0) + return test->asciiCode; + else { + table = test + 1; + n -= pivot + 1; + } + } return 0; } @@ -84,35 +84,35 @@ void _EVT_maskKeyCode( evt->message &= ~0xFF; if (evt->modifiers & EVT_NUMLOCK) { - if ((ascii = translateScan(scan,EVT.codePage->numPad,EVT.codePage->numPadLen)) != 0) { - evt->message |= ascii; - return; - } - } + if ((ascii = translateScan(scan,EVT.codePage->numPad,EVT.codePage->numPadLen)) != 0) { + evt->message |= ascii; + return; + } + } if (evt->modifiers & EVT_CTRLSTATE) { - evt->message |= translateScan(scan,EVT.codePage->ctrl,EVT.codePage->ctrlLen); - return; - } + evt->message |= translateScan(scan,EVT.codePage->ctrl,EVT.codePage->ctrlLen); + return; + } if (evt->modifiers & EVT_CAPSLOCK) { - if (evt->modifiers & EVT_SHIFTKEY) { - if ((ascii = translateScan(scan,EVT.codePage->shiftCaps,EVT.codePage->shiftCapsLen)) != 0) { - evt->message |= ascii; - return; - } - } - else { - if ((ascii = translateScan(scan,EVT.codePage->caps,EVT.codePage->capsLen)) != 0) { - evt->message |= ascii; - return; - } - } - } + if (evt->modifiers & EVT_SHIFTKEY) { + if ((ascii = translateScan(scan,EVT.codePage->shiftCaps,EVT.codePage->shiftCapsLen)) != 0) { + evt->message |= ascii; + return; + } + } + else { + if ((ascii = translateScan(scan,EVT.codePage->caps,EVT.codePage->capsLen)) != 0) { + evt->message |= ascii; + return; + } + } + } if (evt->modifiers & EVT_SHIFTKEY) { - if ((ascii = translateScan(scan,EVT.codePage->shift,EVT.codePage->shiftLen)) != 0) { - evt->message |= ascii; - return; - } - } + if ((ascii = translateScan(scan,EVT.codePage->shift,EVT.codePage->shiftLen)) != 0) { + evt->message |= ascii; + return; + } + } evt->message |= translateScan(scan,EVT.codePage->normal,EVT.codePage->normalLen); } @@ -124,9 +124,9 @@ static ibool _EVT_isKeyDown( uchar scanCode) { if (scanCode > 0x7F) - return false; + return false; else - return EVT.keyTable[scanCode] != 0; + return EVT.keyTable[scanCode] != 0; } /**************************************************************************** @@ -139,7 +139,7 @@ Adds a new keyboard event to the event queue. This routine is called from within the keyboard interrupt subroutine! NOTE: Interrupts are OFF when this routine is called by the keyboard ISR, - and we leave them OFF the entire time. + and we leave them OFF the entire time. ****************************************************************************/ static void addKeyEvent( uint what, @@ -148,31 +148,31 @@ static void addKeyEvent( event_t evt; if (EVT.count < EVENTQSIZE) { - /* Save information in event record */ - evt.when = _EVT_getTicks(); - evt.what = what; - evt.message = message | 0x10000UL; - evt.where_x = 0; - evt.where_y = 0; - evt.relative_x = 0; - evt.relative_y = 0; - evt.modifiers = EVT.keyModifiers; - if (evt.what == EVT_KEYREPEAT) { - if (EVT.oldKey != -1) - EVT.evtq[EVT.oldKey].message += 0x10000UL; - else { - EVT.oldKey = EVT.freeHead; - addEvent(&evt); /* Add to tail of event queue */ - } - } - else { + /* Save information in event record */ + evt.when = _EVT_getTicks(); + evt.what = what; + evt.message = message | 0x10000UL; + evt.where_x = 0; + evt.where_y = 0; + evt.relative_x = 0; + evt.relative_y = 0; + evt.modifiers = EVT.keyModifiers; + if (evt.what == EVT_KEYREPEAT) { + if (EVT.oldKey != -1) + EVT.evtq[EVT.oldKey].message += 0x10000UL; + else { + EVT.oldKey = EVT.freeHead; + addEvent(&evt); /* Add to tail of event queue */ + } + } + else { #ifdef __QNX__ - _EVT_maskKeyCode(&evt); + _EVT_maskKeyCode(&evt); #endif - addEvent(&evt); /* Add to tail of event queue */ - } - EVT.oldMove = -1; - } + addEvent(&evt); /* Add to tail of event queue */ + } + EVT.oldMove = -1; + } } /**************************************************************************** @@ -184,7 +184,7 @@ static int kbWaitForWriteReady(void) { int timeout = 8192; while ((timeout > 0) && (PM_inpb(0x64) & 0x02)) - timeout--; + timeout--; return (timeout > 0); } @@ -197,7 +197,7 @@ static int kbWaitForReadReady(void) { int timeout = 8192; while ((timeout > 0) && (!(PM_inpb(0x64) & 0x01))) - timeout--; + timeout--; return (timeout > 0); } @@ -215,20 +215,20 @@ static int kbSendData( int timeout, temp; do { - if (!kbWaitForWriteReady()) - return 0; - PM_outpb(0x60,data); - timeout = 8192; - while (--timeout > 0) { - if (!kbWaitForReadReady()) - return 0; - temp = PM_inpb(0x60); - if (temp == 0xFA) - return 1; - if (temp == 0xFE) - break; - } - } while ((resends-- > 0) && (timeout > 0)); + if (!kbWaitForWriteReady()) + return 0; + PM_outpb(0x60,data); + timeout = 8192; + while (--timeout > 0) { + if (!kbWaitForReadReady()) + return 0; + temp = PM_inpb(0x60); + if (temp == 0xFA) + return 1; + if (temp == 0xFE) + break; + } + } while ((resends-- > 0) && (timeout > 0)); return 0; } @@ -245,10 +245,10 @@ static void setLEDS( uint modifiers) { if (EVT.allowLEDS) { - if (!kbSendData(0xED) || !kbSendData((modifiers>>9) & 7)) { - kbSendData(0xF4); - } - } + if (!kbSendData(0xED) || !kbSendData((modifiers>>9) & 7)) { + kbSendData(0xF4); + } + } } /**************************************************************************** @@ -256,7 +256,7 @@ REMARKS: Function to process raw scan codes read from the keyboard controller. NOTE: Interrupts are OFF when this routine is called by the keyboard ISR, - and we leave them OFF the entire time. + and we leave them OFF the entire time. {secret} ****************************************************************************/ void processRawScanCode( @@ -267,156 +267,156 @@ void processRawScanCode( int what; if (pauseLoop) { - /* Skip scan codes until the pause key sequence has been read */ - pauseLoop--; - } + /* Skip scan codes until the pause key sequence has been read */ + pauseLoop--; + } else if (scan == 0xE0) { - /* This signals the start of an extended scan code sequence */ - extended = 1; - } + /* This signals the start of an extended scan code sequence */ + extended = 1; + } else if (scan == 0xE1) { - /* The Pause key sends a strange scan code sequence, which is: - * - * E1 1D 52 E1 9D D2 - * - * However there is never any release code nor any auto-repeat for - * this key. For this reason we simply ignore the key and skip the - * next 5 scan codes read from the keyboard. - */ - pauseLoop = 5; - } + /* The Pause key sends a strange scan code sequence, which is: + * + * E1 1D 52 E1 9D D2 + * + * However there is never any release code nor any auto-repeat for + * this key. For this reason we simply ignore the key and skip the + * next 5 scan codes read from the keyboard. + */ + pauseLoop = 5; + } else { - /* Process the scan code normally (it may be an extended code - * however!). Bit 7 means key was released, and bits 0-6 are the - * scan code. - */ - what = (scan & 0x80) ? EVT_KEYUP : EVT_KEYDOWN; - scan &= 0x7F; - if (extended) { - extended = 0; - if (scan == 0x2A || scan == 0x36) { - /* Ignore these extended scan code sequences. These are - * used by the keyboard controller to wrap around certain - * key sequences for the keypad (and when NUMLOCK is down - * internally). - */ - return; - } + /* Process the scan code normally (it may be an extended code + * however!). Bit 7 means key was released, and bits 0-6 are the + * scan code. + */ + what = (scan & 0x80) ? EVT_KEYUP : EVT_KEYDOWN; + scan &= 0x7F; + if (extended) { + extended = 0; + if (scan == 0x2A || scan == 0x36) { + /* Ignore these extended scan code sequences. These are + * used by the keyboard controller to wrap around certain + * key sequences for the keypad (and when NUMLOCK is down + * internally). + */ + return; + } - /* Convert extended codes for key sequences that we map to - * virtual scan codes so the user can detect them in their - * code. - */ - switch (scan) { - case KB_leftCtrl: scan = KB_rightCtrl; break; - case KB_leftAlt: scan = KB_rightAlt; break; - case KB_divide: scan = KB_padDivide; break; - case KB_enter: scan = KB_padEnter; break; - case KB_padTimes: scan = KB_sysReq; break; - } - } - else { - /* Convert regular scan codes for key sequences that we map to - * virtual scan codes so the user can detect them in their - * code. - */ - switch (scan) { - case KB_left: scan = KB_padLeft; break; - case KB_right: scan = KB_padRight; break; - case KB_up: scan = KB_padUp; break; - case KB_down: scan = KB_padDown; break; - case KB_insert: scan = KB_padInsert; break; - case KB_delete: scan = KB_padDelete; break; - case KB_home: scan = KB_padHome; break; - case KB_end: scan = KB_padEnd; break; - case KB_pageUp: scan = KB_padPageUp; break; - case KB_pageDown: scan = KB_padPageDown; break; - } - } + /* Convert extended codes for key sequences that we map to + * virtual scan codes so the user can detect them in their + * code. + */ + switch (scan) { + case KB_leftCtrl: scan = KB_rightCtrl; break; + case KB_leftAlt: scan = KB_rightAlt; break; + case KB_divide: scan = KB_padDivide; break; + case KB_enter: scan = KB_padEnter; break; + case KB_padTimes: scan = KB_sysReq; break; + } + } + else { + /* Convert regular scan codes for key sequences that we map to + * virtual scan codes so the user can detect them in their + * code. + */ + switch (scan) { + case KB_left: scan = KB_padLeft; break; + case KB_right: scan = KB_padRight; break; + case KB_up: scan = KB_padUp; break; + case KB_down: scan = KB_padDown; break; + case KB_insert: scan = KB_padInsert; break; + case KB_delete: scan = KB_padDelete; break; + case KB_home: scan = KB_padHome; break; + case KB_end: scan = KB_padEnd; break; + case KB_pageUp: scan = KB_padPageUp; break; + case KB_pageDown: scan = KB_padPageDown; break; + } + } - /* Determine if the key is an UP, DOWN or REPEAT and maintain the - * up/down status of all keys in our global key array. - */ - if (what == EVT_KEYDOWN) { - if (EVT.keyTable[scan]) - what = EVT_KEYREPEAT; - else - EVT.keyTable[scan] = scan; - } - else { - EVT.keyTable[scan] = 0; - } + /* Determine if the key is an UP, DOWN or REPEAT and maintain the + * up/down status of all keys in our global key array. + */ + if (what == EVT_KEYDOWN) { + if (EVT.keyTable[scan]) + what = EVT_KEYREPEAT; + else + EVT.keyTable[scan] = scan; + } + else { + EVT.keyTable[scan] = 0; + } - /* Handle shift key modifiers */ - if (what != EVT_KEYREPEAT) { - switch (scan) { - case KB_capsLock: - if (what == EVT_KEYDOWN) - EVT.keyModifiers ^= EVT_CAPSLOCK; - setLEDS(EVT.keyModifiers); - break; - case KB_numLock: - if (what == EVT_KEYDOWN) - EVT.keyModifiers ^= EVT_NUMLOCK; - setLEDS(EVT.keyModifiers); - break; - case KB_scrollLock: - if (what == EVT_KEYDOWN) - EVT.keyModifiers ^= EVT_SCROLLLOCK; - setLEDS(EVT.keyModifiers); - break; - case KB_leftShift: - if (what == EVT_KEYUP) - EVT.keyModifiers &= ~EVT_LEFTSHIFT; - else - EVT.keyModifiers |= EVT_LEFTSHIFT; - break; - case KB_rightShift: - if (what == EVT_KEYUP) - EVT.keyModifiers &= ~EVT_RIGHTSHIFT; - else - EVT.keyModifiers |= EVT_RIGHTSHIFT; - break; - case KB_leftCtrl: - if (what == EVT_KEYUP) - EVT.keyModifiers &= ~EVT_LEFTCTRL; - else - EVT.keyModifiers |= EVT_LEFTCTRL; - break; - case KB_rightCtrl: - if (what == EVT_KEYUP) - EVT.keyModifiers &= ~EVT_RIGHTCTRL; - else - EVT.keyModifiers |= EVT_RIGHTCTRL; - break; - case KB_leftAlt: - if (what == EVT_KEYUP) - EVT.keyModifiers &= ~EVT_LEFTALT; - else - EVT.keyModifiers |= EVT_LEFTALT; - break; - case KB_rightAlt: - if (what == EVT_KEYUP) - EVT.keyModifiers &= ~EVT_RIGHTALT; - else - EVT.keyModifiers |= EVT_RIGHTALT; - break; + /* Handle shift key modifiers */ + if (what != EVT_KEYREPEAT) { + switch (scan) { + case KB_capsLock: + if (what == EVT_KEYDOWN) + EVT.keyModifiers ^= EVT_CAPSLOCK; + setLEDS(EVT.keyModifiers); + break; + case KB_numLock: + if (what == EVT_KEYDOWN) + EVT.keyModifiers ^= EVT_NUMLOCK; + setLEDS(EVT.keyModifiers); + break; + case KB_scrollLock: + if (what == EVT_KEYDOWN) + EVT.keyModifiers ^= EVT_SCROLLLOCK; + setLEDS(EVT.keyModifiers); + break; + case KB_leftShift: + if (what == EVT_KEYUP) + EVT.keyModifiers &= ~EVT_LEFTSHIFT; + else + EVT.keyModifiers |= EVT_LEFTSHIFT; + break; + case KB_rightShift: + if (what == EVT_KEYUP) + EVT.keyModifiers &= ~EVT_RIGHTSHIFT; + else + EVT.keyModifiers |= EVT_RIGHTSHIFT; + break; + case KB_leftCtrl: + if (what == EVT_KEYUP) + EVT.keyModifiers &= ~EVT_LEFTCTRL; + else + EVT.keyModifiers |= EVT_LEFTCTRL; + break; + case KB_rightCtrl: + if (what == EVT_KEYUP) + EVT.keyModifiers &= ~EVT_RIGHTCTRL; + else + EVT.keyModifiers |= EVT_RIGHTCTRL; + break; + case KB_leftAlt: + if (what == EVT_KEYUP) + EVT.keyModifiers &= ~EVT_LEFTALT; + else + EVT.keyModifiers |= EVT_LEFTALT; + break; + case KB_rightAlt: + if (what == EVT_KEYUP) + EVT.keyModifiers &= ~EVT_RIGHTALT; + else + EVT.keyModifiers |= EVT_RIGHTALT; + break; #ifdef SUPPORT_CTRL_ALT_DEL - case KB_delete: - if ((EVT.keyModifiers & EVT_CTRLSTATE) && (EVT.keyModifiers & EVT_ALTSTATE)) - Reboot(); - break; + case KB_delete: + if ((EVT.keyModifiers & EVT_CTRLSTATE) && (EVT.keyModifiers & EVT_ALTSTATE)) + Reboot(); + break; #endif - } - } + } + } - /* Add the untranslated key code to the event queue. All - * translation to ASCII from the key codes occurs when the key - * is extracted from the queue, saving time in the low level - * interrupt handler. - */ - addKeyEvent(what,scan << 8); - } + /* Add the untranslated key code to the event queue. All + * translation to ASCII from the key codes occurs when the key + * is extracted from the queue, saving time in the low level + * interrupt handler. + */ + addKeyEvent(what,scan << 8); + } } /**************************************************************************** @@ -442,9 +442,8 @@ void EVTAPI EVT_allowLEDS( { EVT.allowLEDS = true; if (enable) - setLEDS(EVT.keyModifiers); + setLEDS(EVT.keyModifiers); else - setLEDS(0); + setLEDS(0); EVT.allowLEDS = enable; } - diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/mtrr.c b/board/MAI/bios_emulator/scitech/src/pm/common/mtrr.c index d6ced6eadc..eed5f45c9e 100644 --- a/board/MAI/bios_emulator/scitech/src/pm/common/mtrr.c +++ b/board/MAI/bios_emulator/scitech/src/pm/common/mtrr.c @@ -106,26 +106,26 @@ static int MTRR_haveWriteCombine(void) ulong config,dummy; switch (cpuFamily) { - case CPU_AMD: - if (cpuType < CPU_AMDAthlon) { - /* AMD K6-2 stepping 8 and later support the MTRR registers. - * The earlier K6-2 steppings (300Mhz models) do not - * support MTRR's. - */ - if ((cpuType < CPU_AMDK6_2) || (cpuType == CPU_AMDK6_2 && cpuStepping < 8)) - return 0; - return 1; - } - /* Fall through for AMD Athlon which uses P6 style MTRR's */ - case CPU_Intel: - _MTRR_readMSR(INTEL_cap_MSR,&config,&dummy); - return (config & (1 << 10)); - case CPU_Cyrix: - /* Cyrix 6x86 and later support the MTRR registers */ - if (cpuType < CPU_Cyrix6x86) - return 0; - return 1; - } + case CPU_AMD: + if (cpuType < CPU_AMDAthlon) { + /* AMD K6-2 stepping 8 and later support the MTRR registers. + * The earlier K6-2 steppings (300Mhz models) do not + * support MTRR's. + */ + if ((cpuType < CPU_AMDK6_2) || (cpuType == CPU_AMDK6_2 && cpuStepping < 8)) + return 0; + return 1; + } + /* Fall through for AMD Athlon which uses P6 style MTRR's */ + case CPU_Intel: + _MTRR_readMSR(INTEL_cap_MSR,&config,&dummy); + return (config & (1 << 10)); + case CPU_Cyrix: + /* Cyrix 6x86 and later support the MTRR registers */ + if (cpuType < CPU_Cyrix6x86) + return 0; + return 1; + } return 0; } @@ -149,10 +149,10 @@ static int GENERIC_getFreeRegion( ulong lbase,lsize; for (i = 0; i < numMTRR; i++) { - getMTRR(i,&lbase,&lsize,<ype); - if (lsize < 1) - return i; - } + getMTRR(i,&lbase,&lsize,<ype); + if (lsize < 1) + return i; + } (void)base; (void)size; return -1; @@ -178,10 +178,10 @@ static int AMDK6_getFreeRegion( ulong lbase,lsize; for (i = 0; i < numMTRR; i++) { - getMTRR(i,&lbase,&lsize,<ype); - if (lsize < 1) - return i; - } + getMTRR(i,&lbase,&lsize,<ype); + if (lsize < 1) + return i; + } (void)base; (void)size; return -1; @@ -207,23 +207,23 @@ static int CYRIX_getFreeRegion( ulong lbase, lsize; if (size > 0x2000000UL) { - /* If we are to set up a region >32M then look at ARR7 immediately */ - getMTRR(7,&lbase,&lsize,<ype); - if (lsize < 1) - return 7; - } + /* If we are to set up a region >32M then look at ARR7 immediately */ + getMTRR(7,&lbase,&lsize,<ype); + if (lsize < 1) + return 7; + } else { - /* Check ARR0-6 registers */ - for (i = 0; i < 7; i++) { - getMTRR(i,&lbase,&lsize,<ype); - if (lsize < 1) - return i; - } - /* Try ARR7 but its size must be at least 256K */ - getMTRR(7,&lbase,&lsize,<ype); - if ((lsize < 1) && (size >= 0x40000)) - return i; - } + /* Check ARR0-6 registers */ + for (i = 0; i < 7; i++) { + getMTRR(i,&lbase,&lsize,<ype); + if (lsize < 1) + return i; + } + /* Try ARR7 but its size must be at least 256K */ + getMTRR(7,&lbase,&lsize,<ype); + if ((lsize < 1) && (size >= 0x40000)) + return i; + } (void)base; return -1; } @@ -240,20 +240,20 @@ static void MTRR_beginUpdate( { c->flags = _MTRR_disableInt(); if (cpuFamily != CPU_AMD || (cpuFamily == CPU_AMD && cpuType >= CPU_AMDAthlon)) { - switch (cpuFamily) { - case CPU_Intel: - case CPU_AMD: - /* Disable MTRRs, and set the default type to uncached */ - c->cr4Val = _MTRR_saveCR4(); - _MTRR_readMSR(INTEL_defType_MSR,&c->defTypeLo,&c->defTypeHi); - _MTRR_writeMSR(INTEL_defType_MSR,c->defTypeLo & 0xF300UL,c->defTypeHi); - break; - case CPU_Cyrix: - c->ccr3 = _MTRR_getCx86(CX86_CCR3); - _MTRR_setCx86(CX86_CCR3, (uchar)((c->ccr3 & 0x0F) | 0x10)); - break; - } - } + switch (cpuFamily) { + case CPU_Intel: + case CPU_AMD: + /* Disable MTRRs, and set the default type to uncached */ + c->cr4Val = _MTRR_saveCR4(); + _MTRR_readMSR(INTEL_defType_MSR,&c->defTypeLo,&c->defTypeHi); + _MTRR_writeMSR(INTEL_defType_MSR,c->defTypeLo & 0xF300UL,c->defTypeHi); + break; + case CPU_Cyrix: + c->ccr3 = _MTRR_getCx86(CX86_CCR3); + _MTRR_setCx86(CX86_CCR3, (uchar)((c->ccr3 & 0x0F) | 0x10)); + break; + } + } } /**************************************************************************** @@ -267,18 +267,18 @@ static void MTRR_endUpdate( MTRRContext *c) { if (cpuFamily != CPU_AMD || (cpuFamily == CPU_AMD && cpuType >= CPU_AMDAthlon)) { - PM_flushTLB(); - switch (cpuFamily) { - case CPU_Intel: - case CPU_AMD: - _MTRR_writeMSR(INTEL_defType_MSR,c->defTypeLo,c->defTypeHi); - _MTRR_restoreCR4(c->cr4Val); - break; - case CPU_Cyrix: - _MTRR_setCx86(CX86_CCR3,(uchar)c->ccr3); - break; - } - } + PM_flushTLB(); + switch (cpuFamily) { + case CPU_Intel: + case CPU_AMD: + _MTRR_writeMSR(INTEL_defType_MSR,c->defTypeLo,c->defTypeHi); + _MTRR_restoreCR4(c->cr4Val); + break; + case CPU_Cyrix: + _MTRR_setCx86(CX86_CCR3,(uchar)c->ccr3); + break; + } + } /* Re-enable interrupts (if enabled previously) */ _MTRR_restoreInt(c->flags); @@ -304,12 +304,12 @@ static void INTEL_getMTRR( _MTRR_readMSR(INTEL_physMask_MSR(reg),&maskLo,&hi); if ((maskLo & 0x800) == 0) { - /* MTRR is disabled, so it is free */ - *base = 0; - *size = 0; - *type = 0; - return; - } + /* MTRR is disabled, so it is free */ + *base = 0; + *size = 0; + *type = 0; + return; + } _MTRR_readMSR(INTEL_physBase_MSR(reg),&baseLo,&hi); maskLo = (maskLo & 0xFFFFF000UL); *size = ~(maskLo - 1); @@ -338,15 +338,15 @@ static void INTEL_setMTRR( MTRR_beginUpdate(&c); if (size == 0) { - /* The invalid bit is kept in the mask, so we simply clear the - * relevant mask register to disable a range. - */ - _MTRR_writeMSR(INTEL_physMask_MSR(reg),0,0); - } + /* The invalid bit is kept in the mask, so we simply clear the + * relevant mask register to disable a range. + */ + _MTRR_writeMSR(INTEL_physMask_MSR(reg),0,0); + } else { - _MTRR_writeMSR(INTEL_physBase_MSR(reg),base | type,0); - _MTRR_writeMSR(INTEL_physMask_MSR(reg),~(size - 1) | 0x800,0); - } + _MTRR_writeMSR(INTEL_physBase_MSR(reg),base | type,0); + _MTRR_writeMSR(INTEL_physMask_MSR(reg),~(size - 1) | 0x800,0); + } MTRR_endUpdate(&c); } @@ -386,19 +386,19 @@ static void AMD_getMTRR( /* Upper dword is region 1, lower is region 0 */ _MTRR_readMSR(0xC0000085, &low, &high); if (reg == 1) - low = high; + low = high; /* Find the base and type for the region */ *base = low & 0xFFFE0000; *type = 0; if (low & 1) - *type = PM_MTRR_UNCACHABLE; + *type = PM_MTRR_UNCACHABLE; if (low & 2) - *type = PM_MTRR_WRCOMB; + *type = PM_MTRR_WRCOMB; if ((low & 3) == 0) { - *size = 0; - return; - } + *size = 0; + return; + } /* This needs a little explaining. The size is stored as an * inverted mask of bits of 128K granularity 15 bits long offset @@ -441,26 +441,26 @@ static void AMD_setMTRR( MTRR_beginUpdate(&c); _MTRR_readMSR(0xC0000085, &low, &high); if (size == 0) { - /* Clear register to disable */ - if (reg) - high = 0; - else - low = 0; - } + /* Clear register to disable */ + if (reg) + high = 0; + else + low = 0; + } else { - /* Set the register to the base (already shifted for us), the - * type (off by one) and an inverted bitmask of the size - * The size is the only odd bit. We are fed say 512K - * We invert this and we get 111 1111 1111 1011 but - * if you subtract one and invert you get the desired - * 111 1111 1111 1100 mask - */ - newVal = (((~(size-1)) >> 15) & 0x0001FFFC) | base | (type+1); - if (reg) - high = newVal; - else - low = newVal; - } + /* Set the register to the base (already shifted for us), the + * type (off by one) and an inverted bitmask of the size + * The size is the only odd bit. We are fed say 512K + * We invert this and we get 111 1111 1111 1011 but + * if you subtract one and invert you get the desired + * 111 1111 1111 1100 mask + */ + newVal = (((~(size-1)) >> 15) & 0x0001FFFC) | base | (type+1); + if (reg) + high = newVal; + else + low = newVal; + } /* The writeback rule is quite specific. See the manual. Its * disable local interrupts, write back the cache, set the MTRR @@ -507,29 +507,29 @@ static void CYRIX_getMTRR( * Note: shift==0xF means 4G, this is unsupported. */ if (shift) - *size = (reg < 7 ? 0x800UL : 0x20000UL) << shift; + *size = (reg < 7 ? 0x800UL : 0x20000UL) << shift; else - *size = 0; + *size = 0; /* Bit 0 is Cache Enable on ARR7, Cache Disable on ARR0-ARR6 */ if (reg < 7) { - switch (rcr) { - case 1: *type = PM_MTRR_UNCACHABLE; break; - case 8: *type = PM_MTRR_WRBACK; break; - case 9: *type = PM_MTRR_WRCOMB; break; - case 24: - default: *type = PM_MTRR_WRTHROUGH; break; - } - } + switch (rcr) { + case 1: *type = PM_MTRR_UNCACHABLE; break; + case 8: *type = PM_MTRR_WRBACK; break; + case 9: *type = PM_MTRR_WRCOMB; break; + case 24: + default: *type = PM_MTRR_WRTHROUGH; break; + } + } else { - switch (rcr) { - case 0: *type = PM_MTRR_UNCACHABLE; break; - case 8: *type = PM_MTRR_WRCOMB; break; - case 9: *type = PM_MTRR_WRBACK; break; - case 25: - default: *type = PM_MTRR_WRTHROUGH; break; - } - } + switch (rcr) { + case 0: *type = PM_MTRR_UNCACHABLE; break; + case 8: *type = PM_MTRR_WRCOMB; break; + case 9: *type = PM_MTRR_WRBACK; break; + case 25: + default: *type = PM_MTRR_WRTHROUGH; break; + } + } } /**************************************************************************** @@ -557,23 +557,23 @@ static void CYRIX_setMTRR( size >>= (reg < 7 ? 12 : 18); size &= 0x7FFF; /* Make sure arr_size <= 14 */ for (arr_size = 0; size; arr_size++, size >>= 1) - ; + ; if (reg < 7) { - switch (type) { - case PM_MTRR_UNCACHABLE: arr_type = 1; break; - case PM_MTRR_WRCOMB: arr_type = 9; break; - case PM_MTRR_WRTHROUGH: arr_type = 24; break; - default: arr_type = 8; break; - } - } + switch (type) { + case PM_MTRR_UNCACHABLE: arr_type = 1; break; + case PM_MTRR_WRCOMB: arr_type = 9; break; + case PM_MTRR_WRTHROUGH: arr_type = 24; break; + default: arr_type = 8; break; + } + } else { - switch (type) { - case PM_MTRR_UNCACHABLE: arr_type = 0; break; - case PM_MTRR_WRCOMB: arr_type = 8; break; - case PM_MTRR_WRTHROUGH: arr_type = 25; break; - default: arr_type = 9; break; - } - } + switch (type) { + case PM_MTRR_UNCACHABLE: arr_type = 0; break; + case PM_MTRR_WRCOMB: arr_type = 8; break; + case PM_MTRR_WRTHROUGH: arr_type = 25; break; + default: arr_type = 9; break; + } + } MTRR_beginUpdate(&c); _MTRR_setCx86((uchar)arr, ((uchar*)&base)[3]); _MTRR_setCx86((uchar)(arr+1), ((uchar*)&base)[2]); @@ -615,28 +615,28 @@ static void CYRIX_initARR(void) ccr[5] = _MTRR_getCx86(CX86_CCR5); ccr[6] = _MTRR_getCx86(CX86_CCR6); if (ccr[3] & 1) - ccrc[3] = 1; + ccrc[3] = 1; else { - /* Disable SMM mode (bit 1), access to SMM memory (bit 2) and - * access to SMM memory through ARR3 (bit 7). - */ - if (ccr[6] & 0x02) { - ccr[6] &= 0xFD; - ccrc[6] = 1; /* Disable write protection of ARR3. */ - _MTRR_setCx86(CX86_CCR6,ccr[6]); - } - } + /* Disable SMM mode (bit 1), access to SMM memory (bit 2) and + * access to SMM memory through ARR3 (bit 7). + */ + if (ccr[6] & 0x02) { + ccr[6] &= 0xFD; + ccrc[6] = 1; /* Disable write protection of ARR3. */ + _MTRR_setCx86(CX86_CCR6,ccr[6]); + } + } /* If we changed CCR1 in memory, change it in the processor, too. */ if (ccrc[1]) - _MTRR_setCx86(CX86_CCR1,ccr[1]); + _MTRR_setCx86(CX86_CCR1,ccr[1]); /* Enable ARR usage by the processor */ if (!(ccr[5] & 0x20)) { - ccr[5] |= 0x20; - ccrc[5] = 1; - _MTRR_setCx86(CX86_CCR5,ccr[5]); - } + ccr[5] |= 0x20; + ccrc[5] = 1; + _MTRR_setCx86(CX86_CCR5,ccr[5]); + } /* We are finished updating */ MTRR_endUpdate(&c); @@ -654,72 +654,72 @@ void MTRR_init(void) /* Check that we have a compatible CPU */ if (numMTRR == -1) { - numMTRR = 0; - if (!_MTRR_isRing0()) - return; - cpu = CPU_getProcessorType(); - cpuFamily = cpu & CPU_familyMask; - cpuType = cpu & CPU_mask; - cpuStepping = (cpu & CPU_steppingMask) >> CPU_steppingShift; - switch (cpuFamily) { - case CPU_Intel: - /* Intel Pentium Pro and later support the MTRR registers */ - if (cpuType < CPU_PentiumPro) - return; - _MTRR_readMSR(INTEL_cap_MSR,&eax,&edx); - numMTRR = eax & 0xFF; - getMTRR = INTEL_getMTRR; - setMTRR = INTEL_setMTRR; - getFreeRegion = GENERIC_getFreeRegion; - INTEL_disableBankedWriteCombine(); - break; - case CPU_AMD: - /* AMD K6-2 and later support the MTRR registers */ - if ((cpuType < CPU_AMDK6_2) || (cpuType == CPU_AMDK6_2 && cpuStepping < 8)) - return; - if (cpuType < CPU_AMDAthlon) { - numMTRR = 2; /* AMD CPU's have 2 MTRR's */ - getMTRR = AMD_getMTRR; - setMTRR = AMD_setMTRR; - getFreeRegion = AMDK6_getFreeRegion; - - /* For some reason some IBM systems with K6-2 processors - * have write combined enabled for the system BIOS - * region from 0xE0000 to 0xFFFFFF. We need *both* MTRR's - * for our own graphics drivers, so if we detect any - * regions below the 1Meg boundary, we remove them - * so we can use this MTRR register ourselves. - */ - for (i = 0; i < numMTRR; i++) { - getMTRR(i,&lbase,&lsize,<ype); - if (lbase < 0x100000) - setMTRR(i,0,0,0); - } - } - else { - /* AMD Athlon uses P6 style MTRR's */ - _MTRR_readMSR(INTEL_cap_MSR,&eax,&edx); - numMTRR = eax & 0xFF; - getMTRR = INTEL_getMTRR; - setMTRR = INTEL_setMTRR; - getFreeRegion = GENERIC_getFreeRegion; - INTEL_disableBankedWriteCombine(); - } - break; - case CPU_Cyrix: - /* Cyrix 6x86 and later support the MTRR registers */ - if (cpuType < CPU_Cyrix6x86 || cpuType >= CPU_CyrixMediaGX) - return; - numMTRR = 8; /* Cyrix CPU's have 8 ARR's */ - getMTRR = CYRIX_getMTRR; - setMTRR = CYRIX_setMTRR; - getFreeRegion = CYRIX_getFreeRegion; - CYRIX_initARR(); - break; - default: - return; - } - } + numMTRR = 0; + if (!_MTRR_isRing0()) + return; + cpu = CPU_getProcessorType(); + cpuFamily = cpu & CPU_familyMask; + cpuType = cpu & CPU_mask; + cpuStepping = (cpu & CPU_steppingMask) >> CPU_steppingShift; + switch (cpuFamily) { + case CPU_Intel: + /* Intel Pentium Pro and later support the MTRR registers */ + if (cpuType < CPU_PentiumPro) + return; + _MTRR_readMSR(INTEL_cap_MSR,&eax,&edx); + numMTRR = eax & 0xFF; + getMTRR = INTEL_getMTRR; + setMTRR = INTEL_setMTRR; + getFreeRegion = GENERIC_getFreeRegion; + INTEL_disableBankedWriteCombine(); + break; + case CPU_AMD: + /* AMD K6-2 and later support the MTRR registers */ + if ((cpuType < CPU_AMDK6_2) || (cpuType == CPU_AMDK6_2 && cpuStepping < 8)) + return; + if (cpuType < CPU_AMDAthlon) { + numMTRR = 2; /* AMD CPU's have 2 MTRR's */ + getMTRR = AMD_getMTRR; + setMTRR = AMD_setMTRR; + getFreeRegion = AMDK6_getFreeRegion; + + /* For some reason some IBM systems with K6-2 processors + * have write combined enabled for the system BIOS + * region from 0xE0000 to 0xFFFFFF. We need *both* MTRR's + * for our own graphics drivers, so if we detect any + * regions below the 1Meg boundary, we remove them + * so we can use this MTRR register ourselves. + */ + for (i = 0; i < numMTRR; i++) { + getMTRR(i,&lbase,&lsize,<ype); + if (lbase < 0x100000) + setMTRR(i,0,0,0); + } + } + else { + /* AMD Athlon uses P6 style MTRR's */ + _MTRR_readMSR(INTEL_cap_MSR,&eax,&edx); + numMTRR = eax & 0xFF; + getMTRR = INTEL_getMTRR; + setMTRR = INTEL_setMTRR; + getFreeRegion = GENERIC_getFreeRegion; + INTEL_disableBankedWriteCombine(); + } + break; + case CPU_Cyrix: + /* Cyrix 6x86 and later support the MTRR registers */ + if (cpuType < CPU_Cyrix6x86 || cpuType >= CPU_CyrixMediaGX) + return; + numMTRR = 8; /* Cyrix CPU's have 8 ARR's */ + getMTRR = CYRIX_getMTRR; + setMTRR = CYRIX_setMTRR; + getFreeRegion = CYRIX_getFreeRegion; + CYRIX_initARR(); + break; + default: + return; + } + } } /**************************************************************************** @@ -745,93 +745,93 @@ int MTRR_enableWriteCombine( /* Check that we have a CPU that supports MTRR's and type is valid */ if (numMTRR <= 0) { - if (!_MTRR_isRing0()) - return PM_MTRR_ERR_NO_OS_SUPPORT; - return PM_MTRR_NOT_SUPPORTED; - } + if (!_MTRR_isRing0()) + return PM_MTRR_ERR_NO_OS_SUPPORT; + return PM_MTRR_NOT_SUPPORTED; + } if (type >= PM_MTRR_MAX) - return PM_MTRR_ERR_PARAMS; + return PM_MTRR_ERR_PARAMS; /* If the type is WC, check that this processor supports it */ if (!MTRR_haveWriteCombine()) - return PM_MTRR_ERR_NOWRCOMB; + return PM_MTRR_ERR_NOWRCOMB; /* Adjust the boundaries depending on the CPU type */ switch (cpuFamily) { - case CPU_AMD: - if (cpuType < CPU_AMDAthlon) { - /* Apply the K6 block alignment and size rules. In order: - * o Uncached or gathering only - * o 128K or bigger block - * o Power of 2 block - * o base suitably aligned to the power - */ - if (type > PM_MTRR_WRCOMB && (size < (1 << 17) || (size & ~(size-1))-size || (base & (size-1)))) - return PM_MTRR_ERR_NOT_ALIGNED; - break; - } - /* Fall through for AMD Athlon which uses P6 style MTRR's */ - case CPU_Intel: - case CPU_Cyrix: - if ((base & 0xFFF) || (size & 0xFFF)) { - /* Base and size must be multiples of 4Kb */ - return PM_MTRR_ERR_NOT_4KB_ALIGNED; - } - if (base < 0x100000) { - /* Base must be >= 1Mb */ - return PM_MTRR_ERR_BELOW_1MB; - } - - /* Check upper bits of base and last are equal and lower bits - * are 0 for base and 1 for last - */ - last = base + size - 1; - for (lbase = base; !(lbase & 1) && (last & 1); lbase = lbase >> 1, last = last >> 1) - ; - if (lbase != last) { - /* Base is not aligned on the correct boundary */ - return PM_MTRR_ERR_NOT_ALIGNED; - } - break; - default: - return PM_MTRR_NOT_SUPPORTED; - } + case CPU_AMD: + if (cpuType < CPU_AMDAthlon) { + /* Apply the K6 block alignment and size rules. In order: + * o Uncached or gathering only + * o 128K or bigger block + * o Power of 2 block + * o base suitably aligned to the power + */ + if (type > PM_MTRR_WRCOMB && (size < (1 << 17) || (size & ~(size-1))-size || (base & (size-1)))) + return PM_MTRR_ERR_NOT_ALIGNED; + break; + } + /* Fall through for AMD Athlon which uses P6 style MTRR's */ + case CPU_Intel: + case CPU_Cyrix: + if ((base & 0xFFF) || (size & 0xFFF)) { + /* Base and size must be multiples of 4Kb */ + return PM_MTRR_ERR_NOT_4KB_ALIGNED; + } + if (base < 0x100000) { + /* Base must be >= 1Mb */ + return PM_MTRR_ERR_BELOW_1MB; + } + + /* Check upper bits of base and last are equal and lower bits + * are 0 for base and 1 for last + */ + last = base + size - 1; + for (lbase = base; !(lbase & 1) && (last & 1); lbase = lbase >> 1, last = last >> 1) + ; + if (lbase != last) { + /* Base is not aligned on the correct boundary */ + return PM_MTRR_ERR_NOT_ALIGNED; + } + break; + default: + return PM_MTRR_NOT_SUPPORTED; + } /* Search for existing MTRR */ for (i = 0; i < numMTRR; ++i) { - getMTRR(i,&lbase,&lsize,<ype); - if (lbase == 0 && lsize == 0) - continue; - if (base > lbase + (lsize-1)) - continue; - if ((base < lbase) && (base+size-1 < lbase)) - continue; - - /* Check that we don't overlap an existing region */ - if (type != PM_MTRR_UNCACHABLE) { - if ((base < lbase) || (base+size-1 > lbase+lsize-1)) - return PM_MTRR_ERR_OVERLAP; - } - else if (base == lbase && size == lsize) { - /* The region already exists so leave it alone */ - return PM_MTRR_ERR_OK; - } - - /* New region is enclosed by an existing region, so only allow - * a new type to be created if we are setting a region to be - * uncacheable (such as MMIO registers within a framebuffer). - */ - if (ltype != (int)type) { - if (type == PM_MTRR_UNCACHABLE) - continue; - return PM_MTRR_ERR_TYPE_MISMATCH; - } - return PM_MTRR_ERR_OK; - } + getMTRR(i,&lbase,&lsize,<ype); + if (lbase == 0 && lsize == 0) + continue; + if (base > lbase + (lsize-1)) + continue; + if ((base < lbase) && (base+size-1 < lbase)) + continue; + + /* Check that we don't overlap an existing region */ + if (type != PM_MTRR_UNCACHABLE) { + if ((base < lbase) || (base+size-1 > lbase+lsize-1)) + return PM_MTRR_ERR_OVERLAP; + } + else if (base == lbase && size == lsize) { + /* The region already exists so leave it alone */ + return PM_MTRR_ERR_OK; + } + + /* New region is enclosed by an existing region, so only allow + * a new type to be created if we are setting a region to be + * uncacheable (such as MMIO registers within a framebuffer). + */ + if (ltype != (int)type) { + if (type == PM_MTRR_UNCACHABLE) + continue; + return PM_MTRR_ERR_TYPE_MISMATCH; + } + return PM_MTRR_ERR_OK; + } /* Search for an empty MTRR */ if ((i = getFreeRegion(base,size)) < 0) - return PM_MTRR_ERR_NONE_FREE; + return PM_MTRR_ERR_NONE_FREE; setMTRR(i,base,size,type); return PM_MTRR_ERR_OK; } @@ -852,16 +852,16 @@ int PMAPI PM_enumWriteCombine( /* Check that we have a CPU that supports MTRR's and type is valid */ if (numMTRR <= 0) { - if (!_MTRR_isRing0()) - return PM_MTRR_ERR_NO_OS_SUPPORT; - return PM_MTRR_NOT_SUPPORTED; - } + if (!_MTRR_isRing0()) + return PM_MTRR_ERR_NO_OS_SUPPORT; + return PM_MTRR_NOT_SUPPORTED; + } /* Enumerate all existing MTRR's */ for (i = 0; i < numMTRR; ++i) { - getMTRR(i,&lbase,&lsize,<ype); - callback(lbase,lsize,ltype); - } + getMTRR(i,&lbase,&lsize,<ype); + callback(lbase,lsize,ltype); + } return PM_MTRR_ERR_OK; } #endif diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/pcilib.c b/board/MAI/bios_emulator/scitech/src/pm/common/pcilib.c index 8dd6dd13e3..1d542fc5df 100644 --- a/board/MAI/bios_emulator/scitech/src/pm/common/pcilib.c +++ b/board/MAI/bios_emulator/scitech/src/pm/common/pcilib.c @@ -67,13 +67,13 @@ typedef union { struct { - ulong signature; /* _32_ */ - ulong entry; /* 32 bit physical address */ - uchar revision; /* Revision level, 0 */ - uchar length; /* Length in paragraphs should be 01 */ - uchar checksum; /* All bytes must add up to zero */ - uchar reserved[5]; /* Must be zero */ - } fields; + ulong signature; /* _32_ */ + ulong entry; /* 32 bit physical address */ + uchar revision; /* Revision level, 0 */ + uchar length; /* Length in paragraphs should be 01 */ + uchar checksum; /* All bytes must add up to zero */ + uchar reserved[5]; /* Must be zero */ + } fields; char chars[16]; } PCI_bios32; @@ -143,54 +143,54 @@ static int PCIBIOS_detect( /* Bail if we have already detected no BIOS is present */ if (PCIBIOSVersion == 0) - return 0; + return 0; /* First scan the memory from 0xE0000 to 0xFFFFF looking for the * BIOS32 service directory, so we can determine if we can call it * from 32-bit protected mode. */ if (PCIBIOSVersion == -1) { - PCIBIOSVersion = 0; - BIOSImage = PM_mapPhysicalAddr(0xE0000,BIOS_LIMIT,false); - if (!BIOSImage) - return 0; - BIOSEnd = BIOSImage + 0x20000; - for (BIOSDir = (PCI_bios32*)BIOSImage; BIOSDir < (PCI_bios32*)BIOSEnd; BIOSDir++) { - uchar sum; - int i,length; - - if (BIOSDir->fields.signature != BIOS32_SIGNATURE) - continue; - length = BIOSDir->fields.length * 16; - if (!length) - continue; - for (sum = i = 0; i < length ; i++) - sum += BIOSDir->chars[i]; - if (sum != 0) - continue; - BIOSEntry.address = (ulong)BIOSImage + (BIOSDir->fields.entry - 0xE0000); - BIOSEntry.segment = _PCI_getCS(); - break; - } - - /* If we found the BIOS32 directory, call it to get the address of the - * PCI services. - */ - if (BIOSEntry.address == 0) - return 0; - if (_BIOS32_service(PCI_SERVICE,0,&physBase,&length,&offset,BIOSEntry) != 0) - return 0; - PCIPhysEntry = physBase + offset; - PCIEntry.address = (ulong)BIOSImage + (PCIPhysEntry - 0xE0000); - PCIEntry.segment = _PCI_getCS(); - } + PCIBIOSVersion = 0; + BIOSImage = PM_mapPhysicalAddr(0xE0000,BIOS_LIMIT,false); + if (!BIOSImage) + return 0; + BIOSEnd = BIOSImage + 0x20000; + for (BIOSDir = (PCI_bios32*)BIOSImage; BIOSDir < (PCI_bios32*)BIOSEnd; BIOSDir++) { + uchar sum; + int i,length; + + if (BIOSDir->fields.signature != BIOS32_SIGNATURE) + continue; + length = BIOSDir->fields.length * 16; + if (!length) + continue; + for (sum = i = 0; i < length ; i++) + sum += BIOSDir->chars[i]; + if (sum != 0) + continue; + BIOSEntry.address = (ulong)BIOSImage + (BIOSDir->fields.entry - 0xE0000); + BIOSEntry.segment = _PCI_getCS(); + break; + } + + /* If we found the BIOS32 directory, call it to get the address of the + * PCI services. + */ + if (BIOSEntry.address == 0) + return 0; + if (_BIOS32_service(PCI_SERVICE,0,&physBase,&length,&offset,BIOSEntry) != 0) + return 0; + PCIPhysEntry = physBase + offset; + PCIEntry.address = (ulong)BIOSImage + (PCIPhysEntry - 0xE0000); + PCIEntry.segment = _PCI_getCS(); + } #endif /* We found the BIOS entry, so now do the version check */ version = _PCIBIOS_isPresent(PCI_BIOS_PRESENT,&signature,&stat,lastBus,PCIEntry); if (version > 0 && ((stat >> 8) == 0) && signature == PCI_SIGNATURE) { - *hwType = stat & 0xFF; - return PCIBIOSVersion = version; - } + *hwType = stat & 0xFF; + return PCIBIOSVersion = version; + } return 0; } @@ -215,16 +215,16 @@ static ibool CheckDuplicate( { /* Ignore devices with a vendor ID of 0 */ if (info->VendorID == 0) - return true; + return true; /* NOTE: We only check against the current device on * the bus to ensure that we do not exclude * multiple controllers of the same device ID. */ if (info->slot.p.Bus == prev->slot.p.Bus && - info->slot.p.Device == prev->slot.p.Device && - info->DeviceID == prev->DeviceID) - return true; + info->slot.p.Device == prev->slot.p.Device && + info->DeviceID == prev->DeviceID) + return true; return false; } @@ -253,41 +253,41 @@ static int PCI_enumerateMech1( tmp = PM_inpd(0xCF8); PM_outpd(0xCF8,slot.i); if ((PM_inpd(0xCF8) == slot.i) && (PM_inpd(0xCFC) != 0xFFFFFFFFUL)) { - /* PCI access mechanism 1 - the preferred mechanism */ - for (bus = 0; bus < 8; bus++) { - slot.p.Bus = bus; - for (device = 0; device < 32; device++) { - slot.p.Device = device; - for (function = 0; function < 8; function++) { - slot.p.Function = function; - slot.p.Register = 0; - PM_outpd(0xCF8,slot.i); - if (PM_inpd(0xCFC) != 0xFFFFFFFFUL) { - memset(&pci,0,sizeof(pci)); - pci.dwSize = sizeof(pci); - pci.mech1 = 1; - pci.slot = slot; - lp = (ulong*)&(pci.VendorID); - for (i = 0; i < NUM_PCI_REG; i++, lp++) { - slot.p.Register = i; - PM_outpd(0xCF8,slot.i); - *lp = PM_inpd(0xCFC); - } - if (!CheckDuplicate(&pci,&prev)) { - if (info) - COPY_STRUCTURE(&info[numFound],&pci); - ++numFound; - } - prev = pci; - } - } - } - } - - /* Disable PCI config cycle on exit */ - PM_outpd(0xCF8,0); - return numFound; - } + /* PCI access mechanism 1 - the preferred mechanism */ + for (bus = 0; bus < 8; bus++) { + slot.p.Bus = bus; + for (device = 0; device < 32; device++) { + slot.p.Device = device; + for (function = 0; function < 8; function++) { + slot.p.Function = function; + slot.p.Register = 0; + PM_outpd(0xCF8,slot.i); + if (PM_inpd(0xCFC) != 0xFFFFFFFFUL) { + memset(&pci,0,sizeof(pci)); + pci.dwSize = sizeof(pci); + pci.mech1 = 1; + pci.slot = slot; + lp = (ulong*)&(pci.VendorID); + for (i = 0; i < NUM_PCI_REG; i++, lp++) { + slot.p.Register = i; + PM_outpd(0xCF8,slot.i); + *lp = PM_inpd(0xCFC); + } + if (!CheckDuplicate(&pci,&prev)) { + if (info) + COPY_STRUCTURE(&info[numFound],&pci); + ++numFound; + } + prev = pci; + } + } + } + } + + /* Disable PCI config cycle on exit */ + PM_outpd(0xCF8,0); + return numFound; + } PM_outpd(0xCF8,tmp); /* No hardware access mechanism 1 found */ @@ -320,42 +320,42 @@ static int PCI_enumerateMech2( PM_outpb(0xCF8,0x00); PM_outpb(0xCFA,0x00); if (PM_inpb(0xCF8) == 0x00 && PM_inpb(0xCFB) == 0x00) { - /* PCI access mechanism 2 - the older mechanism for legacy busses */ - for (bus = 0; bus < 2; bus++) { - slot.p.Bus = bus; - PM_outpb(0xCFA,(uchar)bus); - for (device = 0; device < 16; device++) { - slot.p.Device = device; - deviceIO = 0xC000 + (device << 8); - for (function = 0; function < 8; function++) { - slot.p.Function = function; - slot.p.Register = 0; - PM_outpb(0xCF8,(uchar)((function << 1) | 0x10)); - if (PM_inpd(deviceIO) != 0xFFFFFFFFUL) { - memset(&pci,0,sizeof(pci)); - pci.dwSize = sizeof(pci); - pci.mech1 = 0; - pci.slot = slot; - lp = (ulong*)&(pci.VendorID); - for (i = 0; i < NUM_PCI_REG; i++, lp++) { - slot.p.Register = i; - *lp = PM_inpd(deviceIO + (i << 2)); - } - if (!CheckDuplicate(&pci,&prev)) { - if (info) - COPY_STRUCTURE(&info[numFound],&pci); - ++numFound; - } - prev = pci; - } - } - } - } - - /* Disable PCI config cycle on exit */ - PM_outpb(0xCF8,0); - return numFound; - } + /* PCI access mechanism 2 - the older mechanism for legacy busses */ + for (bus = 0; bus < 2; bus++) { + slot.p.Bus = bus; + PM_outpb(0xCFA,(uchar)bus); + for (device = 0; device < 16; device++) { + slot.p.Device = device; + deviceIO = 0xC000 + (device << 8); + for (function = 0; function < 8; function++) { + slot.p.Function = function; + slot.p.Register = 0; + PM_outpb(0xCF8,(uchar)((function << 1) | 0x10)); + if (PM_inpd(deviceIO) != 0xFFFFFFFFUL) { + memset(&pci,0,sizeof(pci)); + pci.dwSize = sizeof(pci); + pci.mech1 = 0; + pci.slot = slot; + lp = (ulong*)&(pci.VendorID); + for (i = 0; i < NUM_PCI_REG; i++, lp++) { + slot.p.Register = i; + *lp = PM_inpd(deviceIO + (i << 2)); + } + if (!CheckDuplicate(&pci,&prev)) { + if (info) + COPY_STRUCTURE(&info[numFound],&pci); + ++numFound; + } + prev = pci; + } + } + } + } + + /* Disable PCI config cycle on exit */ + PM_outpb(0xCF8,0); + return numFound; + } /* No hardware access mechanism 2 found */ return 0; @@ -394,32 +394,32 @@ static int PCI_enumerateBIOS( PCIDeviceInfo pci,prev = {0}; if (PCIBIOS_detect(&hwType,&lastBus)) { - /* PCI BIOS access - the ultimate fallback */ - for (bus = 0; bus <= lastBus; bus++) { - slot.p.Bus = bus; - for (device = 0; device < 32; device++) { - slot.p.Device = device; - for (function = 0; function < 8; function++) { - slot.p.Function = function; - if (PCIBIOS_readDWORD(0,slot.i) != 0xFFFFFFFFUL) { - memset(&pci,0,sizeof(pci)); - pci.dwSize = sizeof(pci); - pci.mech1 = 2; - pci.slot = slot; - lp = (ulong*)&(pci.VendorID); - for (i = 0; i < NUM_PCI_REG; i++, lp++) - *lp = PCIBIOS_readDWORD(i << 2,slot.i); - if (!CheckDuplicate(&pci,&prev)) { - if (info) - COPY_STRUCTURE(&info[numFound],&pci); - ++numFound; - } - prev = pci; - } - } - } - } - } + /* PCI BIOS access - the ultimate fallback */ + for (bus = 0; bus <= lastBus; bus++) { + slot.p.Bus = bus; + for (device = 0; device < 32; device++) { + slot.p.Device = device; + for (function = 0; function < 8; function++) { + slot.p.Function = function; + if (PCIBIOS_readDWORD(0,slot.i) != 0xFFFFFFFFUL) { + memset(&pci,0,sizeof(pci)); + pci.dwSize = sizeof(pci); + pci.mech1 = 2; + pci.slot = slot; + lp = (ulong*)&(pci.VendorID); + for (i = 0; i < NUM_PCI_REG; i++, lp++) + *lp = PCIBIOS_readDWORD(i << 2,slot.i); + if (!CheckDuplicate(&pci,&prev)) { + if (info) + COPY_STRUCTURE(&info[numFound],&pci); + ++numFound; + } + prev = pci; + } + } + } + } + } /* Return number of devices found */ return numFound; @@ -447,11 +447,11 @@ int _ASMAPI PCI_enumerate( * stuff we can't do directly. */ if ((numFound = PCI_enumerateMech1(info)) == 0) { - if ((numFound = PCI_enumerateMech2(info)) == 0) { - if ((numFound = PCI_enumerateBIOS(info)) == 0) - return 0; - } - } + if ((numFound = PCI_enumerateMech2(info)) == 0) { + if ((numFound = PCI_enumerateBIOS(info)) == 0) + return 0; + } + } return numFound; } @@ -493,22 +493,22 @@ ulong _ASMAPI PCI_findBARSize( base = PCI_accessReg(bar,0,PCI_READ_DWORD,pci); if (base && !(base & 0x1)) { - /* For some strange reason some devices don't properly decode - * their base address registers (Intel PCI/PCI bridges!), and - * we read completely bogus values. We check for that here - * and clear out those BAR's. - * - * We check for that here because at least the low 12 bits - * of the address range must be zeros, since the page size - * on IA32 processors is always 4Kb. - */ - if ((base & 0xFFF) == 0) { - PCI_accessReg(bar,0xFFFFFFFF,PCI_WRITE_DWORD,pci); - size = PCI_accessReg(bar,0,PCI_READ_DWORD,pci) & ~0xFF; - size = ~size+1; - PCI_accessReg(bar,base,PCI_WRITE_DWORD,pci); - } - } + /* For some strange reason some devices don't properly decode + * their base address registers (Intel PCI/PCI bridges!), and + * we read completely bogus values. We check for that here + * and clear out those BAR's. + * + * We check for that here because at least the low 12 bits + * of the address range must be zeros, since the page size + * on IA32 processors is always 4Kb. + */ + if ((base & 0xFFF) == 0) { + PCI_accessReg(bar,0xFFFFFFFF,PCI_WRITE_DWORD,pci); + size = PCI_accessReg(bar,0,PCI_READ_DWORD,pci) & ~0xFF; + size = ~size+1; + PCI_accessReg(bar,base,PCI_WRITE_DWORD,pci); + } + } pci->slot.p.Register = 0; return size; } @@ -542,49 +542,49 @@ ulong _ASMAPI PCI_accessReg( int iobase; if (info->mech1 == 2) { - /* Use PCI BIOS access since we dont have direct hardware access */ - switch (func) { - case PCI_READ_BYTE: - return (uchar)_PCIBIOS_service(READ_CONFIG_BYTE,info->slot.i >> 8,index,0,PCIEntry); - case PCI_READ_WORD: - return (ushort)_PCIBIOS_service(READ_CONFIG_WORD,info->slot.i >> 8,index,0,PCIEntry); - case PCI_READ_DWORD: - return (ulong)_PCIBIOS_service(READ_CONFIG_DWORD,info->slot.i >> 8,index,0,PCIEntry); - case PCI_WRITE_BYTE: - _PCIBIOS_service(WRITE_CONFIG_BYTE,info->slot.i >> 8,index,value,PCIEntry); - break; - case PCI_WRITE_WORD: - _PCIBIOS_service(WRITE_CONFIG_WORD,info->slot.i >> 8,index,value,PCIEntry); - break; - case PCI_WRITE_DWORD: - _PCIBIOS_service(WRITE_CONFIG_DWORD,info->slot.i >> 8,index,value,PCIEntry); - break; - } - } + /* Use PCI BIOS access since we dont have direct hardware access */ + switch (func) { + case PCI_READ_BYTE: + return (uchar)_PCIBIOS_service(READ_CONFIG_BYTE,info->slot.i >> 8,index,0,PCIEntry); + case PCI_READ_WORD: + return (ushort)_PCIBIOS_service(READ_CONFIG_WORD,info->slot.i >> 8,index,0,PCIEntry); + case PCI_READ_DWORD: + return (ulong)_PCIBIOS_service(READ_CONFIG_DWORD,info->slot.i >> 8,index,0,PCIEntry); + case PCI_WRITE_BYTE: + _PCIBIOS_service(WRITE_CONFIG_BYTE,info->slot.i >> 8,index,value,PCIEntry); + break; + case PCI_WRITE_WORD: + _PCIBIOS_service(WRITE_CONFIG_WORD,info->slot.i >> 8,index,value,PCIEntry); + break; + case PCI_WRITE_DWORD: + _PCIBIOS_service(WRITE_CONFIG_DWORD,info->slot.i >> 8,index,value,PCIEntry); + break; + } + } else { - /* Use direct hardware access mechanisms */ - if (info->mech1) { - /* PCI access mechanism 1 */ - iobase = 0xCFC + (index & 3); - info->slot.p.Register = index >> 2; - PM_outpd(0xCF8,info->slot.i); - } - else { - /* PCI access mechanism 2 */ - PM_outpb(0xCF8,(uchar)((info->slot.p.Function << 1) | 0x10)); - PM_outpb(0xCFA,(uchar)info->slot.p.Bus); - iobase = 0xC000 + (info->slot.p.Device << 8) + index; - } - switch (func) { - case PCI_READ_BYTE: - case PCI_READ_WORD: - case PCI_READ_DWORD: value = PM_inpd(iobase); break; - case PCI_WRITE_BYTE: PM_outpb(iobase,(uchar)value); break; - case PCI_WRITE_WORD: PM_outpw(iobase,(ushort)value); break; - case PCI_WRITE_DWORD: PM_outpd(iobase,(ulong)value); break; - } - PM_outpd(0xCF8,0); - } + /* Use direct hardware access mechanisms */ + if (info->mech1) { + /* PCI access mechanism 1 */ + iobase = 0xCFC + (index & 3); + info->slot.p.Register = index >> 2; + PM_outpd(0xCF8,info->slot.i); + } + else { + /* PCI access mechanism 2 */ + PM_outpb(0xCF8,(uchar)((info->slot.p.Function << 1) | 0x10)); + PM_outpb(0xCFA,(uchar)info->slot.p.Bus); + iobase = 0xC000 + (info->slot.p.Device << 8) + index; + } + switch (func) { + case PCI_READ_BYTE: + case PCI_READ_WORD: + case PCI_READ_DWORD: value = PM_inpd(iobase); break; + case PCI_WRITE_BYTE: PM_outpb(iobase,(uchar)value); break; + case PCI_WRITE_WORD: PM_outpw(iobase,(ushort)value); break; + case PCI_WRITE_DWORD: PM_outpd(iobase,(ulong)value); break; + } + PM_outpd(0xCF8,0); + } return value; } @@ -608,14 +608,14 @@ ibool _ASMAPI PCI_getIRQRoutingOptions( int ret; if (PCIPhysEntry) { - buf.BufferSize = numDevices * sizeof(PCIRouteInfo); - buf.DataBuffer = buffer; - if ((ret = _PCIBIOS_getRouting(&buf,PCIEntry)) == 0x89) - return buf.BufferSize / sizeof(PCIRouteInfo); - if (ret != 0) - return -1; - return 0; - } + buf.BufferSize = numDevices * sizeof(PCIRouteInfo); + buf.DataBuffer = buffer; + if ((ret = _PCIBIOS_getRouting(&buf,PCIEntry)) == 0x89) + return buf.BufferSize / sizeof(PCIRouteInfo); + if (ret != 0) + return -1; + return 0; + } /* We currently only support this via the PCI BIOS functions */ return -1; @@ -642,13 +642,13 @@ ibool _ASMAPI PCI_setHardwareIRQ( uint IRQ) { if (PCIPhysEntry) { - if (_PCIBIOS_setIRQ(info->slot.i >> 8,intPin,IRQ,PCIEntry)) { - info->u.type0.InterruptPin = intPin; - info->u.type0.InterruptLine = IRQ; - return true; - } - return false; - } + if (_PCIBIOS_setIRQ(info->slot.i >> 8,intPin,IRQ,PCIEntry)) { + info->u.type0.InterruptPin = intPin; + info->u.type0.InterruptLine = IRQ; + return true; + } + return false; + } /* We currently only support this via the PCI BIOS functions */ return false; @@ -668,7 +668,7 @@ void _ASMAPI PCI_generateSpecialCyle( ulong specialCycleData) { if (PCIPhysEntry) - _PCIBIOS_specialCycle(bus,specialCycleData,PCIEntry); + _PCIBIOS_specialCycle(bus,specialCycleData,PCIEntry); /* We currently only support this via the PCI BIOS functions */ } @@ -699,14 +699,14 @@ void _ASMAPI PCI_readRegBlock( int endCount = count - middleCount * 4 - startCount; for (i = 0,pb = dst; i < startCount; i++, index++) { - *pb++ = (uchar)PCI_accessReg(index,0,PCI_READ_BYTE,info); - } + *pb++ = (uchar)PCI_accessReg(index,0,PCI_READ_BYTE,info); + } for (i = 0,pd = (ulong*)pb; i < middleCount; i++, index += 4) { - *pd++ = (ulong)PCI_accessReg(index,0,PCI_READ_DWORD,info); - } + *pd++ = (ulong)PCI_accessReg(index,0,PCI_READ_DWORD,info); + } for (i = 0,pb = (uchar*)pd; i < endCount; i++, index++) { - *pb++ = (uchar)PCI_accessReg(index,0,PCI_READ_BYTE,info); - } + *pb++ = (uchar)PCI_accessReg(index,0,PCI_READ_BYTE,info); + } } /**************************************************************************** @@ -736,12 +736,12 @@ void _ASMAPI PCI_writeRegBlock( int endCount = count - middleCount * 4 - startCount; for (i = 0,pb = src; i < startCount; i++, index++) { - PCI_accessReg(index,*pb++,PCI_WRITE_BYTE,info); - } + PCI_accessReg(index,*pb++,PCI_WRITE_BYTE,info); + } for (i = 0,pd = (ulong*)pb; i < middleCount; i++, index += 4) { - PCI_accessReg(index,*pd++,PCI_WRITE_DWORD,info); - } + PCI_accessReg(index,*pd++,PCI_WRITE_DWORD,info); + } for (i = 0,pb = (uchar*)pd; i < endCount; i++, index++) { - PCI_accessReg(index,*pb++,PCI_WRITE_BYTE,info); - } + PCI_accessReg(index,*pb++,PCI_WRITE_BYTE,info); + } } diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/unixio.c b/board/MAI/bios_emulator/scitech/src/pm/common/unixio.c index 04aa47002b..c3a66a7c14 100644 --- a/board/MAI/bios_emulator/scitech/src/pm/common/unixio.c +++ b/board/MAI/bios_emulator/scitech/src/pm/common/unixio.c @@ -65,9 +65,9 @@ static void convertFindData( strcat(filename,blk->d_name); stat(filename,&st); if (!(st.st_mode & S_IWRITE)) - findData->attrib |= PM_FILE_READONLY; + findData->attrib |= PM_FILE_READONLY; if (st.st_mode & S_IFDIR) - findData->attrib |= PM_FILE_DIRECTORY; + findData->attrib |= PM_FILE_DIRECTORY; findData->sizeLo = st.st_size; findData->sizeHi = 0; strncpy(findData->name,blk->d_name,PM_MAX_PATH); @@ -91,24 +91,24 @@ static ibool filematch( PM_backslash(fullpath); strcat(fullpath, dire->d_name); if (stat(fullpath, &st) != 0) - return false; + return false; for (; i < (int)strlen(dire->d_name) && j < (int)strlen(pattern); i++, j++) { - if (pattern[j] == '*' && lastchar != '\\') { - if (pattern[j+1] == '\0') - return true; - while (dire->d_name[i++] != pattern[j+1]) { - if (dire->d_name[i] == '\0') - return false; - } - i -= 2; - } - else if (dire->d_name[i] != pattern[j] && - !(pattern[j] == '?' && lastchar != '\\')) - return false; - lastchar = pattern[i]; - } + if (pattern[j] == '*' && lastchar != '\\') { + if (pattern[j+1] == '\0') + return true; + while (dire->d_name[i++] != pattern[j+1]) { + if (dire->d_name[i] == '\0') + return false; + } + i -= 2; + } + else if (dire->d_name[i] != pattern[j] && + !(pattern[j] == '?' && lastchar != '\\')) + return false; + lastchar = pattern[i]; + } if (j == (int)strlen(pattern) && i == (int)strlen(dire->d_name)) - return true; + return true; return false; } @@ -126,23 +126,23 @@ void * PMAPI PM_findFirstFile( char ext[PM_MAX_PATH]; if ((d = PM_malloc(sizeof(*d))) == NULL) - return PM_FILE_INVALID; + return PM_FILE_INVALID; PM_splitpath(filename,NULL,d->path,name,ext); strcpy(d->mask,name); strcat(d->mask,ext); if (strlen(d->path) == 0) - strcpy(d->path, "."); + strcpy(d->path, "."); if (d->path[strlen(d->path)-1] == '/') - d->path[strlen(d->path)-1] = 0; + d->path[strlen(d->path)-1] = 0; if ((d->d = opendir(d->path)) != NULL) { - while ((dire = readdir(d->d)) != NULL) { - if (filematch(d->mask,d->path,dire)) { - convertFindData(findData,dire,d->path); - return d; - } - } - closedir(d->d); - } + while ((dire = readdir(d->d)) != NULL) { + if (filematch(d->mask,d->path,dire)) { + convertFindData(findData,dire,d->path); + return d; + } + } + closedir(d->d); + } PM_free(d); return PM_FILE_INVALID; } @@ -159,11 +159,11 @@ ibool PMAPI PM_findNextFile( struct dirent *dire; while ((dire = readdir(d->d)) != NULL) { - if (filematch(d->mask,d->path,dire)) { - convertFindData(findData,dire,d->path); - return true; - } - } + if (filematch(d->mask,d->path,dire)) { + convertFindData(findData,dire,d->path); + return true; + } + } return false; } @@ -197,7 +197,7 @@ ibool PMAPI PM_driveValid( char drive) { if (drive == 3) - return true; + return true; return false; } @@ -230,9 +230,9 @@ void PMAPI PM_setFileAttr( stat(filename,&st); mode = st.st_mode; if (attrib & PM_FILE_READONLY) - mode &= ~S_IWRITE; + mode &= ~S_IWRITE; else - mode |= S_IWRITE; + mode |= S_IWRITE; chmod(filename,mode); } @@ -247,7 +247,7 @@ uint PMAPI PM_getFileAttr( stat(filename,&st); if (st.st_mode & S_IWRITE) - return 0; + return 0; return PM_FILE_READONLY; } @@ -280,7 +280,7 @@ ibool PMAPI PM_getFileTime( ibool gmTime, PM_time *time) { - // TODO: Implement this! + /* TODO: Implement this! */ (void)filename; (void)gmTime; (void)time; @@ -297,7 +297,7 @@ ibool PMAPI PM_setFileTime( ibool gmTime, PM_time *time) { - // TODO: Implement this! + /* TODO: Implement this! */ (void)filename; (void)gmTime; (void)time; diff --git a/board/MAI/bios_emulator/scitech/src/pm/common/vgastate.c b/board/MAI/bios_emulator/scitech/src/pm/common/vgastate.c index 3be14e81eb..8056e9a33f 100644 --- a/board/MAI/bios_emulator/scitech/src/pm/common/vgastate.c +++ b/board/MAI/bios_emulator/scitech/src/pm/common/vgastate.c @@ -104,7 +104,7 @@ static void vga_delay(void) * what we need. */ for (i = 0; i <= 10; i++) - PM_outpb(0x80, 0); + PM_outpb(0x80, 0); } /**************************************************************************** @@ -152,9 +152,9 @@ static void vga_savepalette( _port_out(0, PEL_IR); for (i = 0; i < 768; i++) { - vga_delay(); - *pal++ = _port_in(PEL_D); - } + vga_delay(); + *pal++ = _port_in(PEL_D); + } } /**************************************************************************** @@ -169,9 +169,9 @@ static void vga_restorepalette( /* restore saved palette */ _port_out(0, PEL_IW); for (i = 0; i < 768; i++) { - vga_delay(); - _port_out(*pal++, PEL_D); - } + vga_delay(); + _port_out(*pal++, PEL_D); + } } /**************************************************************************** @@ -247,25 +247,25 @@ void PMAPI PM_saveVGAState( /* Save state of VGA registers */ for (i = 0; i < CRT_C; i++) { - _port_out(i, CRT_I); - regs[CRT + i] = _port_in(CRT_D); - } + _port_out(i, CRT_I); + regs[CRT + i] = _port_in(CRT_D); + } for (i = 0; i < ATT_C; i++) { - _port_in(IS1_R); - vga_delay(); - _port_out(i, ATT_IW); - vga_delay(); - regs[ATT + i] = _port_in(ATT_R); - vga_delay(); - } + _port_in(IS1_R); + vga_delay(); + _port_out(i, ATT_IW); + vga_delay(); + regs[ATT + i] = _port_in(ATT_R); + vga_delay(); + } for (i = 0; i < GRA_C; i++) { - _port_out(i, GRA_I); - regs[GRA + i] = _port_in(GRA_D); - } + _port_out(i, GRA_I); + regs[GRA + i] = _port_in(GRA_D); + } for (i = 0; i < SEQ_C; i++) { - _port_out(i, SEQ_I); - regs[SEQ + i] = _port_in(SEQ_D); - } + _port_out(i, SEQ_I); + regs[SEQ + i] = _port_in(SEQ_D); + } regs[MIS] = _port_in(MIS_R); /* Save the VGA palette values */ @@ -302,7 +302,7 @@ void PMAPI PM_restoreVGAState( /* Delay to allow clock change to settle */ for (i = 0; i < 10; i++) - vga_delay(); + vga_delay(); /* Synchronous reset on */ _port_out(0x00,SEQ_I); @@ -312,9 +312,9 @@ void PMAPI PM_restoreVGAState( _port_out(1, SEQ_I); _port_out(regs[SEQ + 1] | 0x20, SEQ_D); for (i = 2; i < SEQ_C; i++) { - _port_out(i, SEQ_I); - _port_out(regs[SEQ + i], SEQ_D); - } + _port_out(i, SEQ_I); + _port_out(regs[SEQ + i], SEQ_D); + } /* Synchronous reset off */ _port_out(0x00,SEQ_I); @@ -324,21 +324,21 @@ void PMAPI PM_restoreVGAState( _port_out(0x11, CRT_I); _port_out(_port_in(CRT_D) & 0x7F, CRT_D); for (i = 0; i < CRT_C; i++) { - _port_out(i, CRT_I); - _port_out(regs[CRT + i], CRT_D); - } + _port_out(i, CRT_I); + _port_out(regs[CRT + i], CRT_D); + } for (i = 0; i < GRA_C; i++) { - _port_out(i, GRA_I); - _port_out(regs[GRA + i], GRA_D); - } + _port_out(i, GRA_I); + _port_out(regs[GRA + i], GRA_D); + } for (i = 0; i < ATT_C; i++) { - _port_in(IS1_R); /* reset flip-flop */ - vga_delay(); - _port_out(i, ATT_IW); - vga_delay(); - _port_out(regs[ATT + i], ATT_IW); - vga_delay(); - } + _port_in(IS1_R); /* reset flip-flop */ + vga_delay(); + _port_out(i, ATT_IW); + vga_delay(); + _port_out(regs[ATT + i], ATT_IW); + vga_delay(); + } /* Ensure the VGA screen is turned on */ PM_vgaUnblankDisplay(); |
