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-rw-r--r--arch/x86/cpu/baytrail/cpu.c101
1 files changed, 26 insertions, 75 deletions
diff --git a/arch/x86/cpu/baytrail/cpu.c b/arch/x86/cpu/baytrail/cpu.c
index 1d482064b2..a0117308ae 100644
--- a/arch/x86/cpu/baytrail/cpu.c
+++ b/arch/x86/cpu/baytrail/cpu.c
@@ -10,79 +10,11 @@
#include <cpu.h>
#include <dm.h>
#include <asm/cpu.h>
+#include <asm/cpu_x86.h>
#include <asm/lapic.h>
-#include <asm/mp.h>
#include <asm/msr.h>
#include <asm/turbo.h>
-#ifdef CONFIG_SMP
-static int enable_smis(struct udevice *cpu, void *unused)
-{
- return 0;
-}
-
-static struct mp_flight_record mp_steps[] = {
- MP_FR_BLOCK_APS(mp_init_cpu, NULL, mp_init_cpu, NULL),
- /* Wait for APs to finish initialization before proceeding. */
- MP_FR_BLOCK_APS(NULL, NULL, enable_smis, NULL),
-};
-
-static int detect_num_cpus(void)
-{
- int ecx = 0;
-
- /*
- * Use the algorithm described in Intel 64 and IA-32 Architectures
- * Software Developer's Manual Volume 3 (3A, 3B & 3C): System
- * Programming Guide, Jan-2015. Section 8.9.2: Hierarchical Mapping
- * of CPUID Extended Topology Leaf.
- */
- while (1) {
- struct cpuid_result leaf_b;
-
- leaf_b = cpuid_ext(0xb, ecx);
-
- /*
- * Bay Trail doesn't have hyperthreading so just determine the
- * number of cores by from level type (ecx[15:8] == * 2)
- */
- if ((leaf_b.ecx & 0xff00) == 0x0200)
- return leaf_b.ebx & 0xffff;
- ecx++;
- }
-}
-
-static int baytrail_init_cpus(void)
-{
- struct mp_params mp_params;
-
- lapic_setup();
-
- mp_params.num_cpus = detect_num_cpus();
- mp_params.parallel_microcode_load = 0,
- mp_params.flight_plan = &mp_steps[0];
- mp_params.num_records = ARRAY_SIZE(mp_steps);
- mp_params.microcode_pointer = 0;
-
- if (mp_init(&mp_params)) {
- printf("Warning: MP init failure\n");
- return -EIO;
- }
-
- return 0;
-}
-#endif
-
-int x86_init_cpus(void)
-{
-#ifdef CONFIG_SMP
- debug("Init additional CPUs\n");
- baytrail_init_cpus();
-#endif
-
- return 0;
-}
-
static void set_max_freq(void)
{
msr_t perf_ctl;
@@ -175,19 +107,38 @@ static int baytrail_get_info(struct udevice *dev, struct cpu_info *info)
return 0;
}
-static int cpu_x86_baytrail_bind(struct udevice *dev)
+static int baytrail_get_count(struct udevice *dev)
{
- struct cpu_platdata *plat = dev_get_parent_platdata(dev);
+ int ecx = 0;
+
+ /*
+ * Use the algorithm described in Intel 64 and IA-32 Architectures
+ * Software Developer's Manual Volume 3 (3A, 3B & 3C): System
+ * Programming Guide, Jan-2015. Section 8.9.2: Hierarchical Mapping
+ * of CPUID Extended Topology Leaf.
+ */
+ while (1) {
+ struct cpuid_result leaf_b;
+
+ leaf_b = cpuid_ext(0xb, ecx);
+
+ /*
+ * Bay Trail doesn't have hyperthreading so just determine the
+ * number of cores by from level type (ecx[15:8] == * 2)
+ */
+ if ((leaf_b.ecx & 0xff00) == 0x0200)
+ return leaf_b.ebx & 0xffff;
- plat->cpu_id = fdtdec_get_int(gd->fdt_blob, dev->of_offset,
- "intel,apic-id", -1);
+ ecx++;
+ }
return 0;
}
static const struct cpu_ops cpu_x86_baytrail_ops = {
- .get_desc = x86_cpu_get_desc,
+ .get_desc = cpu_x86_get_desc,
.get_info = baytrail_get_info,
+ .get_count = baytrail_get_count,
};
static const struct udevice_id cpu_x86_baytrail_ids[] = {
@@ -199,7 +150,7 @@ U_BOOT_DRIVER(cpu_x86_baytrail_drv) = {
.name = "cpu_x86_baytrail",
.id = UCLASS_CPU,
.of_match = cpu_x86_baytrail_ids,
- .bind = cpu_x86_baytrail_bind,
+ .bind = cpu_x86_bind,
.probe = cpu_x86_baytrail_probe,
.ops = &cpu_x86_baytrail_ops,
};
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