diff options
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/cpu/armv7/mx6/clock.c | 61 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/mx7/soc.c | 20 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/crm_regs.h | 103 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx7/imx-regs.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/imx-common/dma.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/imx-common/regs-apbh.h | 6 | ||||
| -rw-r--r-- | arch/arm/include/asm/imx-common/regs-bch.h | 4 |
7 files changed, 188 insertions, 10 deletions
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index 64514b1634..27a3f2f4e6 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -18,6 +18,8 @@ enum pll_clocks { PLL_BUS, /* System Bus PLL*/ PLL_USBOTG, /* OTG USB PLL */ PLL_ENET, /* ENET PLL */ + PLL_AUDIO, /* AUDIO PLL */ + PLL_VIDEO, /* AUDIO PLL */ }; struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; @@ -204,7 +206,7 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num) } static u32 decode_pll(enum pll_clocks pll, u32 infreq) { - u32 div; + u32 div, test_div, pll_num, pll_denom; switch (pll) { case PLL_SYS: @@ -227,6 +229,44 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq) div &= BM_ANADIG_PLL_ENET_DIV_SELECT; return 25000000 * (div + (div >> 1) + 1); + case PLL_AUDIO: + div = __raw_readl(&imx_ccm->analog_pll_audio); + if (!(div & BM_ANADIG_PLL_AUDIO_ENABLE)) + return 0; + /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */ + if (div & BM_ANADIG_PLL_AUDIO_BYPASS) + return MXC_HCLK; + pll_num = __raw_readl(&imx_ccm->analog_pll_audio_num); + pll_denom = __raw_readl(&imx_ccm->analog_pll_audio_denom); + test_div = (div & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT) >> + BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT; + div &= BM_ANADIG_PLL_AUDIO_DIV_SELECT; + if (test_div == 3) { + debug("Error test_div\n"); + return 0; + } + test_div = 1 << (2 - test_div); + + return infreq * (div + pll_num / pll_denom) / test_div; + case PLL_VIDEO: + div = __raw_readl(&imx_ccm->analog_pll_video); + if (!(div & BM_ANADIG_PLL_VIDEO_ENABLE)) + return 0; + /* BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC is ignored */ + if (div & BM_ANADIG_PLL_VIDEO_BYPASS) + return MXC_HCLK; + pll_num = __raw_readl(&imx_ccm->analog_pll_video_num); + pll_denom = __raw_readl(&imx_ccm->analog_pll_video_denom); + test_div = (div & BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT) >> + BP_ANADIG_PLL_VIDEO_POST_DIV_SELECT; + div &= BM_ANADIG_PLL_VIDEO_DIV_SELECT; + if (test_div == 3) { + debug("Error test_div\n"); + return 0; + } + test_div = 1 << (2 - test_div); + + return infreq * (div + pll_num / pll_denom) / test_div; default: return 0; } @@ -437,7 +477,7 @@ static u32 get_mmdc_ch0_clk(void) u32 cbcmr = __raw_readl(&imx_ccm->cbcmr); u32 cbcdr = __raw_readl(&imx_ccm->cbcdr); - u32 freq, podf, per2_clk2_podf; + u32 freq, podf, per2_clk2_podf, pmu_misc2_audio_div; if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || is_cpu_type(MXC_CPU_MX6SL)) { @@ -472,8 +512,21 @@ static u32 get_mmdc_ch0_clk(void) freq = mxc_get_pll_pfd(PLL_BUS, 0); break; case 3: - /* static / 2 divider */ - freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2; + pmu_misc2_audio_div = PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm->pmu_misc2)); + switch (pmu_misc2_audio_div) { + case 0: + case 2: + pmu_misc2_audio_div = 1; + break; + case 1: + pmu_misc2_audio_div = 2; + break; + case 3: + pmu_misc2_audio_div = 4; + break; + } + freq = decode_pll(PLL_AUDIO, MXC_HCLK) / + pmu_misc2_audio_div; break; } } diff --git a/arch/arm/cpu/armv7/mx7/soc.c b/arch/arm/cpu/armv7/mx7/soc.c index c777922e9d..1d8e470971 100644 --- a/arch/arm/cpu/armv7/mx7/soc.c +++ b/arch/arm/cpu/armv7/mx7/soc.c @@ -130,6 +130,24 @@ static void init_csu(void) writel(CSU_INIT_SEC_LEVEL0, CSU_IPS_BASE_ADDR + i * 4); } +static void imx_enet_mdio_fixup(void) +{ + struct iomuxc_gpr_base_regs *gpr_regs = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* + * The management data input/output (MDIO) requires open-drain, + * i.MX7D TO1.0 ENET MDIO pin has no open drain, but TO1.1 supports + * this feature. So to TO1.1, need to enable open drain by setting + * bits GPR0[8:7]. + */ + + if (soc_rev() >= CHIP_REV_1_1) { + setbits_le32(&gpr_regs->gpr[0], + IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK); + } +} + int arch_cpu_init(void) { init_aips(); @@ -138,6 +156,8 @@ int arch_cpu_init(void) /* Disable PDE bit of WMCR register */ imx_set_wdog_powerdown(false); + imx_enet_mdio_fixup(); + #ifdef CONFIG_APBH_DMA /* Start APBH DMA */ mxs_dma_init(); diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 13e0a3d907..22212c2202 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -103,6 +103,97 @@ struct mxc_ccm_reg { u32 analog_pfd_528_set; u32 analog_pfd_528_clr; u32 analog_pfd_528_tog; + /* PMU Memory Map/Register Definition */ + u32 pmu_reg_1p1; + u32 pmu_reg_1p1_set; + u32 pmu_reg_1p1_clr; + u32 pmu_reg_1p1_tog; + u32 pmu_reg_3p0; + u32 pmu_reg_3p0_set; + u32 pmu_reg_3p0_clr; + u32 pmu_reg_3p0_tog; + u32 pmu_reg_2p5; + u32 pmu_reg_2p5_set; + u32 pmu_reg_2p5_clr; + u32 pmu_reg_2p5_tog; + u32 pmu_reg_core; + u32 pmu_reg_core_set; + u32 pmu_reg_core_clr; + u32 pmu_reg_core_tog; + u32 pmu_misc0; + u32 pmu_misc0_set; + u32 pmu_misc0_clr; + u32 pmu_misc0_tog; + u32 pmu_misc1; + u32 pmu_misc1_set; + u32 pmu_misc1_clr; + u32 pmu_misc1_tog; + u32 pmu_misc2; + u32 pmu_misc2_set; + u32 pmu_misc2_clr; + u32 pmu_misc2_tog; + /* TEMPMON Memory Map/Register Definition */ + u32 tempsense0; + u32 tempsense0_set; + u32 tempsense0_clr; + u32 tempsense0_tog; + u32 tempsense1; + u32 tempsense1_set; + u32 tempsense1_clr; + u32 tempsense1_tog; + /* USB Analog Memory Map/Register Definition */ + u32 usb1_vbus_detect; + u32 usb1_vbus_detect_set; + u32 usb1_vbus_detect_clr; + u32 usb1_vbus_detect_tog; + u32 usb1_chrg_detect; + u32 usb1_chrg_detect_set; + u32 usb1_chrg_detect_clr; + u32 usb1_chrg_detect_tog; + u32 usb1_vbus_det_stat; + u32 usb1_vbus_det_stat_set; + u32 usb1_vbus_det_stat_clr; + u32 usb1_vbus_det_stat_tog; + u32 usb1_chrg_det_stat; + u32 usb1_chrg_det_stat_set; + u32 usb1_chrg_det_stat_clr; + u32 usb1_chrg_det_stat_tog; + u32 usb1_loopback; + u32 usb1_loopback_set; + u32 usb1_loopback_clr; + u32 usb1_loopback_tog; + u32 usb1_misc; + u32 usb1_misc_set; + u32 usb1_misc_clr; + u32 usb1_misc_tog; + u32 usb2_vbus_detect; + u32 usb2_vbus_detect_set; + u32 usb2_vbus_detect_clr; + u32 usb2_vbus_detect_tog; + u32 usb2_chrg_detect; + u32 usb2_chrg_detect_set; + u32 usb2_chrg_detect_clr; + u32 usb2_chrg_detect_tog; + u32 usb2_vbus_det_stat; + u32 usb2_vbus_det_stat_set; + u32 usb2_vbus_det_stat_clr; + u32 usb2_vbus_det_stat_tog; + u32 usb2_chrg_det_stat; + u32 usb2_chrg_det_stat_set; + u32 usb2_chrg_det_stat_clr; + u32 usb2_chrg_det_stat_tog; + u32 usb2_loopback; + u32 usb2_loopback_set; + u32 usb2_loopback_clr; + u32 usb2_loopback_tog; + u32 usb2_misc; + u32 usb2_misc_set; + u32 usb2_misc_clr; + u32 usb2_misc_tog; + u32 digprog; + u32 reserved1[7]; + /* For i.MX 6SoloLite */ + u32 digprog_sololite; }; #endif @@ -1136,4 +1227,16 @@ struct mxc_ccm_reg { #define BM_ANADIG_ANA_MISC0_REFTOP_SELBIASOFF 0x00000008 +#define BM_PMU_MISC2_AUDIO_DIV_MSB (1 << 23) +#define BP_PMU_MISC2_AUDIO_DIV_MSB 23 + +#define BM_PMU_MISC2_AUDIO_DIV_LSB (1 << 15) +#define BP_PMU_MISC2_AUDIO_DIV_LSB 15 + +#define PMU_MISC2_AUDIO_DIV(v) \ + (((v & BM_PMU_MISC2_AUDIO_DIV_MSB) >> \ + (BP_PMU_MISC2_AUDIO_DIV_MSB - 1)) | \ + ((v & BM_PMU_MISC2_AUDIO_DIV_LSB) >> \ + BP_PMU_MISC2_AUDIO_DIV_LSB)) + #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h index e28a807ec2..58a25c7b16 100644 --- a/arch/arm/include/asm/arch-mx7/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7/imx-regs.h @@ -272,6 +272,8 @@ struct src { #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT 5 #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK 0x40u #define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT 6 +#define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_MASK (3 << 7) +#define IOMUXC_GPR_GPR0_ENET_MDIO_OPEN_DRAIN_SHIFT 7 /* GPR1 Bit Fields */ #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_MASK 0x1u #define IOMUXC_GPR_GPR1_GPR_WEIM_ACT_CS0_SHIFT 0 diff --git a/arch/arm/include/asm/imx-common/dma.h b/arch/arm/include/asm/imx-common/dma.h index 7d421b3967..1aec4f9d5a 100644 --- a/arch/arm/include/asm/imx-common/dma.h +++ b/arch/arm/include/asm/imx-common/dma.h @@ -59,7 +59,7 @@ enum { MXS_DMA_CHANNEL_AHB_APBH_RESERVED1, MXS_MAX_DMA_CHANNELS, }; -#elif defined(CONFIG_MX6) +#elif defined(CONFIG_MX6) || defined(CONFIG_MX7) enum { MXS_DMA_CHANNEL_AHB_APBH_GPMI0 = 0, MXS_DMA_CHANNEL_AHB_APBH_GPMI1, diff --git a/arch/arm/include/asm/imx-common/regs-apbh.h b/arch/arm/include/asm/imx-common/regs-apbh.h index ca77436004..391452cc12 100644 --- a/arch/arm/include/asm/imx-common/regs-apbh.h +++ b/arch/arm/include/asm/imx-common/regs-apbh.h @@ -96,7 +96,7 @@ struct mxs_apbh_regs { mxs_reg_32(hw_apbh_version) }; -#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6)) +#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7)) struct mxs_apbh_regs { mxs_reg_32(hw_apbh_ctrl0) mxs_reg_32(hw_apbh_ctrl1) @@ -275,7 +275,7 @@ struct mxs_apbh_regs { #define APBH_CTRL0_CLKGATE_CHANNEL_NAND7 0x0800 #define APBH_CTRL0_CLKGATE_CHANNEL_HSADC 0x1000 #define APBH_CTRL0_CLKGATE_CHANNEL_LCDIF 0x2000 -#elif defined(CONFIG_MX6) +#elif (defined(CONFIG_MX6) || defined(CONFIG_MX7)) #define APBH_CTRL0_CLKGATE_CHANNEL_OFFSET 0 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND0 0x0001 #define APBH_CTRL0_CLKGATE_CHANNEL_NAND1 0x0002 @@ -391,7 +391,7 @@ struct mxs_apbh_regs { #define APBH_CHANNEL_CTRL_FREEZE_CHANNEL_LCDIF 0x2000 #endif -#if defined(CONFIG_MX6) +#if (defined(CONFIG_MX6) || defined(CONFIG_MX7)) #define APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET 16 #endif diff --git a/arch/arm/include/asm/imx-common/regs-bch.h b/arch/arm/include/asm/imx-common/regs-bch.h index 5c477835fc..adfbace05d 100644 --- a/arch/arm/include/asm/imx-common/regs-bch.h +++ b/arch/arm/include/asm/imx-common/regs-bch.h @@ -123,7 +123,7 @@ struct mxs_bch_regs { #define BCH_FLASHLAYOUT0_NBLOCKS_OFFSET 24 #define BCH_FLASHLAYOUT0_META_SIZE_MASK (0xff << 16) #define BCH_FLASHLAYOUT0_META_SIZE_OFFSET 16 -#if defined(CONFIG_MX6) +#if (defined(CONFIG_MX6) || defined(CONFIG_MX7)) #define BCH_FLASHLAYOUT0_ECC0_MASK (0x1f << 11) #define BCH_FLASHLAYOUT0_ECC0_OFFSET 11 #else @@ -154,7 +154,7 @@ struct mxs_bch_regs { #define BCH_FLASHLAYOUT1_PAGE_SIZE_MASK (0xffff << 16) #define BCH_FLASHLAYOUT1_PAGE_SIZE_OFFSET 16 -#if defined(CONFIG_MX6) +#if (defined(CONFIG_MX6) || defined(CONFIG_MX7)) #define BCH_FLASHLAYOUT1_ECCN_MASK (0x1f << 11) #define BCH_FLASHLAYOUT1_ECCN_OFFSET 11 #else |
