2 files changed, 2 insertions, 46 deletions

diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h
index 4710d88b4d..ceb3367449 100644
--- a/arch/arm/include/asm/arch-omap4/clocks.h
+++ b/arch/arm/include/asm/arch-omap4/clocks.h
@@ -242,55 +242,10 @@
 #define DPLL_NO_LOCK	0
 #define DPLL_LOCK	1
 
-#define NUM_SYS_CLKS	7
-
-struct dpll_regs {
-	u32 cm_clkmode_dpll;
-	u32 cm_idlest_dpll;
-	u32 cm_autoidle_dpll;
-	u32 cm_clksel_dpll;
-	u32 cm_div_m2_dpll;
-	u32 cm_div_m3_dpll;
-	u32 cm_div_m4_dpll;
-	u32 cm_div_m5_dpll;
-	u32 cm_div_m6_dpll;
-	u32 cm_div_m7_dpll;
-};
-
-/* DPLL parameter table */
-struct dpll_params {
-	u32 m;
-	u32 n;
-	s8 m2;
-	s8 m3;
-	s8 m4;
-	s8 m5;
-	s8 m6;
-	s8 m7;
-};
-
-extern const u32 sys_clk_array[8];
-
 void scale_vcores(void);
 void do_scale_tps62361(int gpio, u32 reg, u32 volt_mv);
 u32 get_offset_code(u32 offset);
-u32 omap_ddr_clk(void);
 void do_scale_vcore(u32 vcore_reg, u32 volt_mv);
-void setup_post_dividers(u32 const base, const struct dpll_params *params);
-u32 get_sys_clk_index(void);
-void enable_basic_clocks(void);
-void enable_basic_uboot_clocks(void);
-void enable_non_essential_clocks(void);
-void do_enable_clocks(u32 const *clk_domains,
-		      u32 const *clk_modules_hw_auto,
-		      u32 const *clk_modules_explicit_en,
-		      u8 wait_for_enable);
-const struct dpll_params *get_mpu_dpll_params(void);
-const struct dpll_params *get_core_dpll_params(void);
-const struct dpll_params *get_per_dpll_params(void);
-const struct dpll_params *get_iva_dpll_params(void);
-const struct dpll_params *get_usb_dpll_params(void);
-const struct dpll_params *get_abe_dpll_params(void);
 
 struct omap4_scrm_regs {
 	u32 revision;           /* 0x0000 */
diff --git a/arch/arm/include/asm/arch-omap4/omap.h b/arch/arm/include/asm/arch-omap4/omap.h
index 86ba3359ec..1c0ce9b38b 100644
--- a/arch/arm/include/asm/arch-omap4/omap.h
+++ b/arch/arm/include/asm/arch-omap4/omap.h
@@ -179,7 +179,8 @@ struct control_lpddr2io_regs {
 #define OMAP4_SRAM_SCRATCH_EMIF_T_NUM	(SRAM_SCRATCH_SPACE_ADDR + 0xC)
 #define OMAP4_SRAM_SCRATCH_EMIF_T_DEN	(SRAM_SCRATCH_SPACE_ADDR + 0x10)
 #define OMAP_SRAM_SCRATCH_PRCM_PTR      (SRAM_SCRATCH_SPACE_ADDR + 0x14)
-#define OMAP4_SRAM_SCRATCH_SPACE_END	(SRAM_SCRATCH_SPACE_ADDR + 0x18)
+#define OMAP_SRAM_SCRATCH_DPLLS_PTR     (SRAM_SCRATCH_SPACE_ADDR + 0x18)
+#define OMAP4_SRAM_SCRATCH_SPACE_END	(SRAM_SCRATCH_SPACE_ADDR + 0x1C)
 
 /* ROM code defines */
 /* Boot device */