diff options
Diffstat (limited to 'arch/arm/include/asm/arch-mx6')
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/clock.h | 2 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/crm_regs.h | 34 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/hab.h | 139 | ||||
| -rw-r--r-- | arch/arm/include/asm/arch-mx6/imx-regs.h | 57 |
4 files changed, 79 insertions, 153 deletions
diff --git a/arch/arm/include/asm/arch-mx6/clock.h b/arch/arm/include/asm/arch-mx6/clock.h index 2b220d6f8f..14505239e8 100644 --- a/arch/arm/include/asm/arch-mx6/clock.h +++ b/arch/arm/include/asm/arch-mx6/clock.h @@ -66,6 +66,8 @@ int enable_spi_clk(unsigned char enable, unsigned spi_num); void enable_ipu_clock(void); int enable_fec_anatop_clock(int fec_id, enum enet_freq freq); void enable_enet_clk(unsigned char enable); +int enable_lcdif_clock(u32 base_addr); void enable_qspi_clk(int qspi_num); void enable_thermal_clk(void); +void mxs_set_lcdclk(u32 base_addr, u32 freq); #endif /* __ASM_ARCH_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 10306cd776..13e0a3d907 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -174,6 +174,9 @@ struct mxc_ccm_reg { #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26) #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26 +/* LCDIF on i.MX6SX/UL */ +#define MXC_CCM_CBCMR_LCDIF1_PODF_MASK (0x7 << 23) +#define MXC_CCM_CBCMR_LCDIF1_PODF_OFFSET 23 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23) #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21) @@ -210,7 +213,10 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23) #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23 -/* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */ +/* LCFIF2_PODF on i.MX6SX */ +#define MXC_CCM_CSCMR1_LCDIF2_PODF_MASK (0x7 << 20) +#define MXC_CCM_CSCMR1_LCDIF2_PODF_OFFSET 20 +/* ACLK_EMI on i.MX6DQ/SDL/DQP */ #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20) #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20 /* CSCMR1_GPMI/BCH exist on i.MX6UL */ @@ -400,6 +406,20 @@ struct mxc_ccm_reg { #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19 /* ECSPI_CLK_SEL exists on i.MX6SX/SL/QP */ #define MXC_CCM_CSCDR2_ECSPI_CLK_SEL_MASK (0x1 << 18) +/* LCDIF1 on i.MX6SX/UL */ +#define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_MASK (0x7 << 15) +#define MXC_CCM_CSCDR2_LCDIF1_PRED_SEL_OFFSET 15 +#define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_MASK (0x7 << 12) +#define MXC_CCM_CSCDR2_LCDIF1_PRE_DIV_OFFSET 12 +#define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_MASK (0x7 << 9) +#define MXC_CCM_CSCDR2_LCDIF1_CLK_SEL_OFFSET 9 +/* LCDIF2 on i.MX6SX */ +#define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_MASK (0x7 << 6) +#define MXC_CCM_CSCDR2_LCDIF2_PRED_SEL_OFFSET 6 +#define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_MASK (0x7 << 3) +#define MXC_CCM_CSCDR2_LCDIF2_PRE_DIV_OFFSET 3 +#define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_MASK (0x7 << 0) +#define MXC_CCM_CSCDR2_LCDIF2_CLK_SEL_OFFSET 0 /* All IPU2_DI1 are LCDIF1 on MX6SX */ #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15) @@ -622,17 +642,16 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET) #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET) -#ifdef CONFIG_MX6SX +/* i.MX6SX/UL LCD and PXP */ #define MXC_CCM_CCGR2_LCD_OFFSET 28 #define MXC_CCM_CCGR2_LCD_MASK (3 << MXC_CCM_CCGR2_LCD_OFFSET) #define MXC_CCM_CCGR2_PXP_OFFSET 30 #define MXC_CCM_CCGR2_PXP_MASK (3 << MXC_CCM_CCGR2_PXP_OFFSET) -#else + #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET) #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET) -#endif /* Exist on i.MX6SX */ #define MXC_CCM_CCGR3_M4_OFFSET 2 @@ -685,6 +704,13 @@ struct mxc_ccm_reg { #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET) #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET) + +#define MXC_CCM_CCGR3_DISP_AXI_OFFSET 6 +#define MXC_CCM_CCGR3_DISP_AXI_MASK (3 << MXC_CCM_CCGR3_DISP_AXI_OFFSET) +#define MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET 8 +#define MXC_CCM_CCGR3_LCDIF2_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF2_PIX_OFFSET) +#define MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET 10 +#define MXC_CCM_CCGR3_LCDIF1_PIX_MASK (3 << MXC_CCM_CCGR3_LCDIF1_PIX_OFFSET) /* AXI on i.MX6UL */ #define MXC_CCM_CCGR3_AXI_CLK_OFFSET 28 #define MXC_CCM_CCGR3_AXI_CLK_MASK (3 << MXC_CCM_CCGR3_AXI_CLK_OFFSET) diff --git a/arch/arm/include/asm/arch-mx6/hab.h b/arch/arm/include/asm/arch-mx6/hab.h deleted file mode 100644 index d0eaa67180..0000000000 --- a/arch/arm/include/asm/arch-mx6/hab.h +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Copyright (C) 2012-2015 Freescale Semiconductor, Inc. All Rights Reserved. - * - * SPDX-License-Identifier: GPL-2.0+ - * -*/ - -#ifndef __SECURE_MX6Q_H__ -#define __SECURE_MX6Q_H__ - -#include <linux/types.h> - -/* -------- start of HAB API updates ------------*/ -/* The following are taken from HAB4 SIS */ - -/* Status definitions */ -enum hab_status { - HAB_STS_ANY = 0x00, - HAB_FAILURE = 0x33, - HAB_WARNING = 0x69, - HAB_SUCCESS = 0xf0 -}; - -/* Security Configuration definitions */ -enum hab_config { - HAB_CFG_RETURN = 0x33, /* < Field Return IC */ - HAB_CFG_OPEN = 0xf0, /* < Non-secure IC */ - HAB_CFG_CLOSED = 0xcc /* < Secure IC */ -}; - -/* State definitions */ -enum hab_state { - HAB_STATE_INITIAL = 0x33, /* Initialising state (transitory) */ - HAB_STATE_CHECK = 0x55, /* Check state (non-secure) */ - HAB_STATE_NONSECURE = 0x66, /* Non-secure state */ - HAB_STATE_TRUSTED = 0x99, /* Trusted state */ - HAB_STATE_SECURE = 0xaa, /* Secure state */ - HAB_STATE_FAIL_SOFT = 0xcc, /* Soft fail state */ - HAB_STATE_FAIL_HARD = 0xff, /* Hard fail state (terminal) */ - HAB_STATE_NONE = 0xf0, /* No security state machine */ - HAB_STATE_MAX -}; - -enum hab_reason { - HAB_RSN_ANY = 0x00, /* Match any reason */ - HAB_ENG_FAIL = 0x30, /* Engine failure */ - HAB_INV_ADDRESS = 0x22, /* Invalid address: access denied */ - HAB_INV_ASSERTION = 0x0c, /* Invalid assertion */ - HAB_INV_CALL = 0x28, /* Function called out of sequence */ - HAB_INV_CERTIFICATE = 0x21, /* Invalid certificate */ - HAB_INV_COMMAND = 0x06, /* Invalid command: command malformed */ - HAB_INV_CSF = 0x11, /* Invalid csf */ - HAB_INV_DCD = 0x27, /* Invalid dcd */ - HAB_INV_INDEX = 0x0f, /* Invalid index: access denied */ - HAB_INV_IVT = 0x05, /* Invalid ivt */ - HAB_INV_KEY = 0x1d, /* Invalid key */ - HAB_INV_RETURN = 0x1e, /* Failed callback function */ - HAB_INV_SIGNATURE = 0x18, /* Invalid signature */ - HAB_INV_SIZE = 0x17, /* Invalid data size */ - HAB_MEM_FAIL = 0x2e, /* Memory failure */ - HAB_OVR_COUNT = 0x2b, /* Expired poll count */ - HAB_OVR_STORAGE = 0x2d, /* Exhausted storage region */ - HAB_UNS_ALGORITHM = 0x12, /* Unsupported algorithm */ - HAB_UNS_COMMAND = 0x03, /* Unsupported command */ - HAB_UNS_ENGINE = 0x0a, /* Unsupported engine */ - HAB_UNS_ITEM = 0x24, /* Unsupported configuration item */ - HAB_UNS_KEY = 0x1b, /* Unsupported key type/parameters */ - HAB_UNS_PROTOCOL = 0x14, /* Unsupported protocol */ - HAB_UNS_STATE = 0x09, /* Unsuitable state */ - HAB_RSN_MAX -}; - -enum hab_context { - HAB_CTX_ANY = 0x00, /* Match any context */ - HAB_CTX_FAB = 0xff, /* Event logged in hab_fab_test() */ - HAB_CTX_ENTRY = 0xe1, /* Event logged in hab_rvt.entry() */ - HAB_CTX_TARGET = 0x33, /* Event logged in hab_rvt.check_target() */ - HAB_CTX_AUTHENTICATE = 0x0a,/* Logged in hab_rvt.authenticate_image() */ - HAB_CTX_DCD = 0xdd, /* Event logged in hab_rvt.run_dcd() */ - HAB_CTX_CSF = 0xcf, /* Event logged in hab_rvt.run_csf() */ - HAB_CTX_COMMAND = 0xc0, /* Event logged executing csf/dcd command */ - HAB_CTX_AUT_DAT = 0xdb, /* Authenticated data block */ - HAB_CTX_ASSERT = 0xa0, /* Event logged in hab_rvt.assert() */ - HAB_CTX_EXIT = 0xee, /* Event logged in hab_rvt.exit() */ - HAB_CTX_MAX -}; - -/*Function prototype description*/ -typedef enum hab_status hab_rvt_report_event_t(enum hab_status, uint32_t, - uint8_t* , size_t*); -typedef enum hab_status hab_rvt_report_status_t(enum hab_config *, - enum hab_state *); -typedef enum hab_status hab_loader_callback_f_t(void**, size_t*, const void*); -typedef enum hab_status hab_rvt_entry_t(void); -typedef enum hab_status hab_rvt_exit_t(void); -typedef void *hab_rvt_authenticate_image_t(uint8_t, ptrdiff_t, - void **, size_t *, hab_loader_callback_f_t); -typedef void hapi_clock_init_t(void); - -#define HAB_ENG_ANY 0x00 /* Select first compatible engine */ -#define HAB_ENG_SCC 0x03 /* Security controller */ -#define HAB_ENG_RTIC 0x05 /* Run-time integrity checker */ -#define HAB_ENG_SAHARA 0x06 /* Crypto accelerator */ -#define HAB_ENG_CSU 0x0a /* Central Security Unit */ -#define HAB_ENG_SRTC 0x0c /* Secure clock */ -#define HAB_ENG_DCP 0x1b /* Data Co-Processor */ -#define HAB_ENG_CAAM 0x1d /* CAAM */ -#define HAB_ENG_SNVS 0x1e /* Secure Non-Volatile Storage */ -#define HAB_ENG_OCOTP 0x21 /* Fuse controller */ -#define HAB_ENG_DTCP 0x22 /* DTCP co-processor */ -#define HAB_ENG_ROM 0x36 /* Protected ROM area */ -#define HAB_ENG_HDCP 0x24 /* HDCP co-processor */ -#define HAB_ENG_RTL 0x77 /* RTL simulation engine */ -#define HAB_ENG_SW 0xff /* Software engine */ - -#ifdef CONFIG_MX6SX -#define HAB_RVT_BASE 0x00000100 -#else -#define HAB_RVT_BASE 0x00000094 -#endif - -#define HAB_RVT_ENTRY (*(uint32_t *)(HAB_RVT_BASE + 0x04)) -#define HAB_RVT_EXIT (*(uint32_t *)(HAB_RVT_BASE + 0x08)) -#define HAB_RVT_AUTHENTICATE_IMAGE (*(uint32_t *)(HAB_RVT_BASE + 0x10)) -#define HAB_RVT_REPORT_EVENT (*(uint32_t *)(HAB_RVT_BASE + 0x20)) -#define HAB_RVT_REPORT_STATUS (*(uint32_t *)(HAB_RVT_BASE + 0x24)) - -#define HAB_RVT_REPORT_EVENT_NEW (*(uint32_t *)0x000000B8) -#define HAB_RVT_REPORT_STATUS_NEW (*(uint32_t *)0x000000BC) -#define HAB_RVT_AUTHENTICATE_IMAGE_NEW (*(uint32_t *)0x000000A8) -#define HAB_RVT_ENTRY_NEW (*(uint32_t *)0x0000009C) -#define HAB_RVT_EXIT_NEW (*(uint32_t *)0x000000A0) - -#define HAB_CID_ROM 0 /**< ROM Caller ID */ -#define HAB_CID_UBOOT 1 /**< UBOOT Caller ID*/ - -/* ----------- end of HAB API updates ------------*/ - -#endif diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 74512ac08e..2f068e5c9b 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -264,6 +264,7 @@ #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000) #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000) #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) +#define MX6UL_LCDIF1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000) #ifdef CONFIG_MX6SX #define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000) #else @@ -300,8 +301,6 @@ #define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000) #define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000) #define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000) -#define LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000) -#define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000) #define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000) #define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000) #define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000) @@ -319,16 +318,11 @@ #define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000) #define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000) #endif +/* Only for i.MX6SX */ +#define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000) +#define MX6SX_LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000) #define MX6SX_WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000) -/* only for i.MX6SX/UL */ -#define WDOG3_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL) ? \ - MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR) - -#define CHIP_REV_1_0 0x10 -#define CHIP_REV_1_2 0x12 -#define CHIP_REV_1_5 0x15 -#define CHIP_REV_2_0 0x20 #if !(defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) #define IRAM_SIZE 0x00040000 #else @@ -336,9 +330,17 @@ #endif #define FEC_QUIRK_ENET_MAC +#include <asm/imx-common/regs-lcdif.h> #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include <asm/types.h> +/* only for i.MX6SX/UL */ +#define WDOG3_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL) ? \ + MX6UL_WDOG3_BASE_ADDR : MX6SX_WDOG3_BASE_ADDR) +#define LCDIF1_BASE_ADDR (is_cpu_type(MXC_CPU_MX6UL)) ? \ + MX6UL_LCDIF1_BASE_ADDR : MX6SX_LCDIF1_BASE_ADDR + + extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac); #define SRC_SCR_CORE_1_RESET_OFFSET 14 @@ -413,10 +415,37 @@ struct src { }; /* GPR1 bitfields */ +#define IOMUXC_GPR1_APP_CLK_REQ_N BIT(30) +#define IOMUXC_GPR1_PCIE_EXIT_L1 BIT(28) +#define IOMUXC_GPR1_PCIE_RDY_L23 BIT(27) +#define IOMUXC_GPR1_PCIE_ENTER_L1 BIT(26) +#define IOMUXC_GPR1_MIPI_COLOR_SW BIT(25) +#define IOMUXC_GPR1_DPI_OFF BIT(24) +#define IOMUXC_GPR1_EXC_MON_SLVE BIT(22) #define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21 #define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET) +#define IOMUXC_GPR1_MIPI_IPU2_MUX_IOMUX BIT(20) +#define IOMUXC_GPR1_MIPI_IPU1_MUX_IOMUX BIT(19) +#define IOMUXC_GPR1_PCIE_TEST_PD BIT(18) +#define IOMUXC_GPR1_IPU_VPU_MUX_IPU2 BIT(17) +#define IOMUXC_GPR1_PCIE_REF_CLK_EN BIT(16) +#define IOMUXC_GPR1_USB_EXP_MODE BIT(15) +#define IOMUXC_GPR1_PCIE_INT BIT(14) #define IOMUXC_GPR1_USB_OTG_ID_OFFSET 13 #define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET) +#define IOMUXC_GPR1_GINT BIT(12) +#define IOMUXC_GPR1_ADDRS3_MASK (0x3 << 10) +#define IOMUXC_GPR1_ADDRS3_32MB (0x0 << 10) +#define IOMUXC_GPR1_ADDRS3_64MB (0x1 << 10) +#define IOMUXC_GPR1_ADDRS3_128MB (0x2 << 10) +#define IOMUXC_GPR1_ACT_CS3 BIT(9) +#define IOMUXC_GPR1_ADDRS2_MASK (0x3 << 7) +#define IOMUXC_GPR1_ACT_CS2 BIT(6) +#define IOMUXC_GPR1_ADDRS1_MASK (0x3 << 4) +#define IOMUXC_GPR1_ACT_CS1 BIT(3) +#define IOMUXC_GPR1_ADDRS0_OFFSET (1) +#define IOMUXC_GPR1_ADDRS0_MASK (0x3 << 1) +#define IOMUXC_GPR1_ACT_CS0 BIT(0) /* GPR3 bitfields */ #define IOMUXC_GPR3_GPU_DBG_OFFSET 29 @@ -465,6 +494,14 @@ struct src { #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2 #define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET) +/* gpr12 bitfields */ +#define IOMUXC_GPR12_ARMP_IPG_CLK_EN BIT(27) +#define IOMUXC_GPR12_ARMP_AHB_CLK_EN BIT(26) +#define IOMUXC_GPR12_ARMP_ATB_CLK_EN BIT(25) +#define IOMUXC_GPR12_ARMP_APB_CLK_EN BIT(24) +#define IOMUXC_GPR12_DEVICE_TYPE (0xf << 12) +#define IOMUXC_GPR12_PCIE_CTL_2 BIT(10) +#define IOMUXC_GPR12_LOS_LEVEL (0x1f << 4) struct iomuxc { #if (defined(CONFIG_MX6SX) || defined(CONFIG_MX6UL)) |
