diff options
Diffstat (limited to 'arch/arm/cpu')
| -rw-r--r-- | arch/arm/cpu/armv7/stv0991/clock.c | 14 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/stv0991/pinmux.c | 14 |
2 files changed, 28 insertions, 0 deletions
diff --git a/arch/arm/cpu/armv7/stv0991/clock.c b/arch/arm/cpu/armv7/stv0991/clock.c index aca6aba414..70b8a8d984 100644 --- a/arch/arm/cpu/armv7/stv0991/clock.c +++ b/arch/arm/cpu/armv7/stv0991/clock.c @@ -13,6 +13,13 @@ static struct stv0991_cgu_regs *const stv0991_cgu_regs = \ (struct stv0991_cgu_regs *) (CGU_BASE_ADDR); +void enable_pll1(void) +{ + /* pll1 already configured for 1000Mhz, just need to enable it */ + writel(readl(&stv0991_cgu_regs->pll1_ctrl) & ~(0x01), + &stv0991_cgu_regs->pll1_ctrl); +} + void clock_setup(int peripheral) { switch (peripheral) { @@ -20,6 +27,13 @@ void clock_setup(int peripheral) writel(UART_CLK_CFG, &stv0991_cgu_regs->uart_freq); break; case ETH_CLOCK_CFG: + enable_pll1(); + writel(ETH_CLK_CFG, &stv0991_cgu_regs->eth_freq); + + /* Clock selection for ethernet tx_clk & rx_clk*/ + writel((readl(&stv0991_cgu_regs->eth_ctrl) & ETH_CLK_MASK) + | ETH_CLK_CTRL, &stv0991_cgu_regs->eth_ctrl); + break; default: break; diff --git a/arch/arm/cpu/armv7/stv0991/pinmux.c b/arch/arm/cpu/armv7/stv0991/pinmux.c index 6d4414aaa5..1d086a235d 100644 --- a/arch/arm/cpu/armv7/stv0991/pinmux.c +++ b/arch/arm/cpu/armv7/stv0991/pinmux.c @@ -41,6 +41,20 @@ int stv0991_pinmux_config(int peripheral) CFG_GPIOB_16_UART_TX, &stv0991_creg->mux7); break; + case ETH_GPIOB_10_31_C_0_4: + writel(readl(&stv0991_creg->mux6) & 0x000000FF, + &stv0991_creg->mux6); + writel(0x00000000, &stv0991_creg->mux7); + writel(0x00000000, &stv0991_creg->mux8); + writel(readl(&stv0991_creg->mux9) & 0xFFF00000, + &stv0991_creg->mux9); + /* Ethernet Voltage configuration to 1.8V*/ + writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) | + ETH_VDD_CFG, &stv0991_creg->vdd_pad1); + writel((readl(&stv0991_creg->vdd_pad1) & VDD_ETH_PS_MASK) | + ETH_M_VDD_CFG, &stv0991_creg->vdd_pad1); + + break; default: break; } |
