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-rw-r--r--arch/arm/cpu/tegra-common/ap.c14
1 files changed, 12 insertions, 2 deletions
diff --git a/arch/arm/cpu/tegra-common/ap.c b/arch/arm/cpu/tegra-common/ap.c
index c4eb137480..aebe29e4b7 100644
--- a/arch/arm/cpu/tegra-common/ap.c
+++ b/arch/arm/cpu/tegra-common/ap.c
@@ -20,10 +20,14 @@
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
* MA 02111-1307 USA
*/
+
+/* Tegra AP (Application Processor) code */
+
#include <common.h>
#include <asm/io.h>
#include <asm/arch/gp_padctrl.h>
#include <asm/arch-tegra/ap.h>
+#include <asm/arch-tegra/clock.h>
#include <asm/arch-tegra/fuse.h>
#include <asm/arch-tegra/pmc.h>
#include <asm/arch-tegra/scu.h>
@@ -58,6 +62,12 @@ int tegra_get_chip_type(void)
return TEGRA_SOC_T25;
}
break;
+ case CHIPID_TEGRA30:
+ switch (tegra_sku_id) {
+ case SKU_ID_T30:
+ return TEGRA_SOC_T30;
+ }
+ break;
}
/* unknown sku id */
return TEGRA_SOC_UNKNOWN;
@@ -93,7 +103,7 @@ static u32 get_odmdata(void)
u32 bct_start, odmdata;
- bct_start = readl(AP20_BASE_PA_SRAM + NVBOOTINFOTABLE_BCTPTR);
+ bct_start = readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BCTPTR);
odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
return odmdata;
@@ -127,5 +137,5 @@ void s_init(void)
"orr r0, r0, #0x41\n"
"mcr p15, 0, r0, c1, c0, 1\n");
- /* FIXME: should have ap20's L2 disabled too? */
+ /* FIXME: should have SoC's L2 disabled too? */
}
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