diff options
Diffstat (limited to 'arch/arm/cpu/armv7')
| -rw-r--r-- | arch/arm/cpu/armv7/am33xx/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/am33xx/mem.c | 98 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/am33xx/sys_info.c | 41 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap-common/Makefile | 4 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap-common/emif-common.c | 6 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap-common/hwinit-common.c | 15 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap-common/mem-common.c | 117 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap3/Makefile | 1 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/hw_data.c | 40 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/hwinit.c | 3 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/prcm-regs.c | 8 | ||||
| -rw-r--r-- | arch/arm/cpu/armv7/omap5/sdram.c | 19 |
12 files changed, 212 insertions, 141 deletions
diff --git a/arch/arm/cpu/armv7/am33xx/Makefile b/arch/arm/cpu/armv7/am33xx/Makefile index 5566310d94..aae3f096b2 100644 --- a/arch/arm/cpu/armv7/am33xx/Makefile +++ b/arch/arm/cpu/armv7/am33xx/Makefile @@ -14,7 +14,6 @@ endif obj-$(CONFIG_TI816X) += clock_ti816x.o obj-y += sys_info.o -obj-y += mem.o obj-y += ddr.o obj-y += emif4.o obj-y += board.o diff --git a/arch/arm/cpu/armv7/am33xx/mem.c b/arch/arm/cpu/armv7/am33xx/mem.c deleted file mode 100644 index 56c9e7dbce..0000000000 --- a/arch/arm/cpu/armv7/am33xx/mem.c +++ /dev/null @@ -1,98 +0,0 @@ -/* - * (C) Copyright 2010 - * Texas Instruments, <www.ti.com> - * - * Author : - * Mansoor Ahamed <mansoor.ahamed@ti.com> - * - * Initial Code from: - * Manikandan Pillai <mani.pillai@ti.com> - * Richard Woodruff <r-woodruff2@ti.com> - * Syed Mohammed Khasim <khasim@ti.com> - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/cpu.h> -#include <asm/arch/mem.h> -#include <asm/arch/sys_proto.h> -#include <command.h> - -struct gpmc *gpmc_cfg; - - -void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, - u32 size) -{ - writel(0, &cs->config7); - sdelay(1000); - /* Delay for settling */ - writel(gpmc_config[0], &cs->config1); - writel(gpmc_config[1], &cs->config2); - writel(gpmc_config[2], &cs->config3); - writel(gpmc_config[3], &cs->config4); - writel(gpmc_config[4], &cs->config5); - writel(gpmc_config[5], &cs->config6); - /* Enable the config */ - writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) | - (1 << 6)), &cs->config7); - sdelay(2000); -} - -/***************************************************** - * gpmc_init(): init gpmc bus - * Init GPMC for x16, MuxMode (SDRAM in x32). - * This code can only be executed from SRAM or SDRAM. - *****************************************************/ -void gpmc_init(void) -{ - /* putting a blanket check on GPMC based on ZeBu for now */ - gpmc_cfg = (struct gpmc *)GPMC_BASE; -#if defined(CONFIG_NOR) -/* configure GPMC for NOR */ - const u32 gpmc_regs[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1, - STNOR_GPMC_CONFIG2, - STNOR_GPMC_CONFIG3, - STNOR_GPMC_CONFIG4, - STNOR_GPMC_CONFIG5, - STNOR_GPMC_CONFIG6, - STNOR_GPMC_CONFIG7 - }; - u32 size = GPMC_SIZE_16M; - u32 base = CONFIG_SYS_FLASH_BASE; -#elif defined(CONFIG_NAND) -/* configure GPMC for NAND */ - const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1, - M_NAND_GPMC_CONFIG2, - M_NAND_GPMC_CONFIG3, - M_NAND_GPMC_CONFIG4, - M_NAND_GPMC_CONFIG5, - M_NAND_GPMC_CONFIG6, - 0 - }; - u32 size = GPMC_SIZE_256M; - u32 base = CONFIG_SYS_NAND_BASE; -#else - const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 }; - u32 size = 0; - u32 base = 0; -#endif - /* global settings */ - writel(0x00000008, &gpmc_cfg->sysconfig); - writel(0x00000000, &gpmc_cfg->irqstatus); - writel(0x00000000, &gpmc_cfg->irqenable); -#ifdef CONFIG_NOR - writel(0x00000200, &gpmc_cfg->config); -#else - writel(0x00000012, &gpmc_cfg->config); -#endif - /* - * Disable the GPMC0 config set by ROM code - */ - writel(0, &gpmc_cfg->cs[0].config7); - sdelay(1000); - /* enable chip-select specific configurations */ - enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size); -} diff --git a/arch/arm/cpu/armv7/am33xx/sys_info.c b/arch/arm/cpu/armv7/am33xx/sys_info.c index 50eb598ff2..2ce682f6b1 100644 --- a/arch/arm/cpu/armv7/am33xx/sys_info.c +++ b/arch/arm/cpu/armv7/am33xx/sys_info.c @@ -79,12 +79,24 @@ u32 get_sysboot_value(void) } #ifdef CONFIG_DISPLAY_CPUINFO +static char *cpu_revs[] = { + "1.0", + "2.0", + "2.1"}; + + +static char *dev_types[] = { + "TST", + "EMU", + "HS", + "GP"}; + /** * Print CPU information */ int print_cpuinfo(void) { - char *cpu_s, *sec_s; + char *cpu_s, *sec_s, *rev_s; switch (get_cpu_type()) { case AM335X: @@ -94,28 +106,21 @@ int print_cpuinfo(void) cpu_s = "TI81XX"; break; default: - cpu_s = "Unknown cpu type"; + cpu_s = "Unknown CPU type"; break; } - switch (get_device_type()) { - case TST_DEVICE: - sec_s = "TST"; - break; - case EMU_DEVICE: - sec_s = "EMU"; - break; - case HS_DEVICE: - sec_s = "HS"; - break; - case GP_DEVICE: - sec_s = "GP"; - break; - default: + if (get_cpu_rev() < ARRAY_SIZE(cpu_revs)) + rev_s = cpu_revs[get_cpu_rev()]; + else + rev_s = "?"; + + if (get_device_type() < ARRAY_SIZE(dev_types)) + sec_s = dev_types[get_device_type()]; + else sec_s = "?"; - } - printf("%s-%s rev %d\n", cpu_s, sec_s, get_cpu_rev()); + printf("%s-%s rev %s\n", cpu_s, sec_s, rev_s); return 0; } diff --git a/arch/arm/cpu/armv7/omap-common/Makefile b/arch/arm/cpu/armv7/omap-common/Makefile index 59f5352b26..5f5132f661 100644 --- a/arch/arm/cpu/armv7/omap-common/Makefile +++ b/arch/arm/cpu/armv7/omap-common/Makefile @@ -27,8 +27,4 @@ obj-y += boot-common.o obj-y += lowlevel_init.o endif -ifndef CONFIG_SPL_BUILD -ifneq ($(CONFIG_OMAP44XX)$(CONFIG_OMAP54XX),) obj-y += mem-common.o -endif -endif diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 429c4becf3..71c0cc8f2e 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -1384,8 +1384,10 @@ void sdram_init(void) if (sdram_type == EMIF_SDRAM_TYPE_DDR3 && (!in_sdram && !warm_reset())) { - do_bug0039_workaround(EMIF1_BASE); - do_bug0039_workaround(EMIF2_BASE); + if (emif1_enabled) + do_bug0039_workaround(EMIF1_BASE); + if (emif2_enabled) + do_bug0039_workaround(EMIF2_BASE); } debug("<<sdram_init()\n"); diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 8ebc0ce251..ba97d9ec56 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -185,7 +185,7 @@ u32 omap_sdram_size(void) { u32 section, i, valid; u64 sdram_start = 0, sdram_end = 0, addr, - size, total_size = 0, trap_size = 0; + size, total_size = 0, trap_size = 0, trap_start = 0; for (i = 0; i < 4; i++) { section = __raw_readl(DMM_BASE + i*4); @@ -194,8 +194,8 @@ u32 omap_sdram_size(void) addr = section & EMIF_SYS_ADDR_MASK; /* See if the address is valid */ - if ((addr >= DRAM_ADDR_SPACE_START) && - (addr < DRAM_ADDR_SPACE_END)) { + if ((addr >= TI_ARMV7_DRAM_ADDR_SPACE_START) && + (addr < TI_ARMV7_DRAM_ADDR_SPACE_END)) { size = ((section & EMIF_SYS_SIZE_MASK) >> EMIF_SYS_SIZE_SHIFT); size = 1 << size; @@ -208,12 +208,15 @@ u32 omap_sdram_size(void) sdram_end = addr + size; } else { trap_size = size; + trap_start = addr; } - } - } - total_size = (sdram_end - sdram_start) - (trap_size); + + if ((trap_start >= sdram_start) && (trap_start < sdram_end)) + total_size = (sdram_end - sdram_start) - (trap_size); + else + total_size = sdram_end - sdram_start; return total_size; } diff --git a/arch/arm/cpu/armv7/omap-common/mem-common.c b/arch/arm/cpu/armv7/omap-common/mem-common.c index afc1bc185e..944ef840a1 100644 --- a/arch/arm/cpu/armv7/omap-common/mem-common.c +++ b/arch/arm/cpu/armv7/omap-common/mem-common.c @@ -2,31 +2,136 @@ * (C) Copyright 2010 * Texas Instruments, <www.ti.com> * - * Steve Sakoman <steve@sakoman.com> + * Author : + * Mansoor Ahamed <mansoor.ahamed@ti.com> + * + * Initial Code from: + * Manikandan Pillai <mani.pillai@ti.com> + * Richard Woodruff <r-woodruff2@ti.com> + * Syed Mohammed Khasim <khasim@ti.com> * * SPDX-License-Identifier: GPL-2.0+ */ +#include <common.h> +#include <asm/io.h> #include <asm/arch/cpu.h> +#include <asm/arch/mem.h> #include <asm/arch/sys_proto.h> +#include <command.h> +#include <linux/mtd/omap_gpmc.h> struct gpmc *gpmc_cfg; +#if defined(CONFIG_OMAP34XX) +/******************************************************** + * mem_ok() - test used to see if timings are correct + * for a part. Helps in guessing which part + * we are currently using. + *******************************************************/ +u32 mem_ok(u32 cs) +{ + u32 val1, val2, addr; + u32 pattern = 0x12345678; + + addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs); + + writel(0x0, addr + 0x400); /* clear pos A */ + writel(pattern, addr); /* pattern to pos B */ + writel(0x0, addr + 4); /* remove pattern off the bus */ + val1 = readl(addr + 0x400); /* get pos A value */ + val2 = readl(addr); /* get val2 */ + writel(0x0, addr + 0x400); /* clear pos A */ + + if ((val1 != 0) || (val2 != pattern)) /* see if pos A val changed */ + return 0; + else + return 1; +} +#endif + +void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base, + u32 size) +{ + writel(0, &cs->config7); + sdelay(1000); + /* Delay for settling */ + writel(gpmc_config[0], &cs->config1); + writel(gpmc_config[1], &cs->config2); + writel(gpmc_config[2], &cs->config3); + writel(gpmc_config[3], &cs->config4); + writel(gpmc_config[4], &cs->config5); + writel(gpmc_config[5], &cs->config6); + /* Enable the config */ + writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) | + (1 << 6)), &cs->config7); + sdelay(2000); +} + /***************************************************** * gpmc_init(): init gpmc bus + * Init GPMC for x16, MuxMode (SDRAM in x32). * This code can only be executed from SRAM or SDRAM. *****************************************************/ void gpmc_init(void) { + /* putting a blanket check on GPMC based on ZeBu for now */ gpmc_cfg = (struct gpmc *)GPMC_BASE; - +#if defined(CONFIG_NOR) +/* configure GPMC for NOR */ + const u32 gpmc_regs[GPMC_MAX_REG] = { STNOR_GPMC_CONFIG1, + STNOR_GPMC_CONFIG2, + STNOR_GPMC_CONFIG3, + STNOR_GPMC_CONFIG4, + STNOR_GPMC_CONFIG5, + STNOR_GPMC_CONFIG6, + STNOR_GPMC_CONFIG7 + }; + u32 size = GPMC_SIZE_16M; + u32 base = CONFIG_SYS_FLASH_BASE; +#elif defined(CONFIG_NAND) +/* configure GPMC for NAND */ + const u32 gpmc_regs[GPMC_MAX_REG] = { M_NAND_GPMC_CONFIG1, + M_NAND_GPMC_CONFIG2, + M_NAND_GPMC_CONFIG3, + M_NAND_GPMC_CONFIG4, + M_NAND_GPMC_CONFIG5, + M_NAND_GPMC_CONFIG6, + 0 + }; + u32 size = GPMC_SIZE_256M; + u32 base = CONFIG_SYS_NAND_BASE; +#elif defined(CONFIG_CMD_ONENAND) + const u32 gpmc_regs[GPMC_MAX_REG] = { ONENAND_GPMC_CONFIG1, + ONENAND_GPMC_CONFIG2, + ONENAND_GPMC_CONFIG3, + ONENAND_GPMC_CONFIG4, + ONENAND_GPMC_CONFIG5, + ONENAND_GPMC_CONFIG6, + 0 + }; + u32 base = PISMO1_ONEN_BASE; + u32 size = PISMO1_ONEN_SIZE; +#else + const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 }; + u32 size = 0; + u32 base = 0; +#endif /* global settings */ - writel(0, &gpmc_cfg->irqenable); /* isr's sources masked */ - writel(0, &gpmc_cfg->timeout_control);/* timeout disable */ - + writel(0x00000008, &gpmc_cfg->sysconfig); + writel(0x00000000, &gpmc_cfg->irqstatus); + writel(0x00000000, &gpmc_cfg->irqenable); + writel(0x00000000, &gpmc_cfg->timeout_control); +#ifdef CONFIG_NOR + writel(0x00000200, &gpmc_cfg->config); +#else + writel(0x00000012, &gpmc_cfg->config); +#endif /* * Disable the GPMC0 config set by ROM code - * It conflicts with our MPDB (both at 0x08000000) */ writel(0, &gpmc_cfg->cs[0].config7); + sdelay(1000); + /* enable chip-select specific configurations */ + enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size); } diff --git a/arch/arm/cpu/armv7/omap3/Makefile b/arch/arm/cpu/armv7/omap3/Makefile index 39ff2575bc..cf86046353 100644 --- a/arch/arm/cpu/armv7/omap3/Makefile +++ b/arch/arm/cpu/armv7/omap3/Makefile @@ -9,7 +9,6 @@ obj-y := lowlevel_init.o obj-y += board.o obj-y += clock.o -obj-y += mem.o obj-y += sys_info.o ifdef CONFIG_SPL_BUILD obj-$(CONFIG_SPL_OMAP3_ID_NAND) += spl_id_nand.o diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c index ad971327bf..4baca11d7a 100644 --- a/arch/arm/cpu/armv7/omap5/hw_data.c +++ b/arch/arm/cpu/armv7/omap5/hw_data.c @@ -372,6 +372,38 @@ struct vcores_data dra752_volts = { .iva.pmic = &tps659038, }; +struct vcores_data dra722_volts = { + .mpu.value = 1000, + .mpu.efuse.reg = STD_FUSE_OPP_VMIN_MPU_NOM, + .mpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .mpu.addr = 0x23, + .mpu.pmic = &tps659038, + + .eve.value = 1000, + .eve.efuse.reg = STD_FUSE_OPP_VMIN_DSPEVE_NOM, + .eve.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .eve.addr = 0x2f, + .eve.pmic = &tps659038, + + .gpu.value = 1000, + .gpu.efuse.reg = STD_FUSE_OPP_VMIN_GPU_NOM, + .gpu.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .gpu.addr = 0x2f, + .gpu.pmic = &tps659038, + + .core.value = 1000, + .core.efuse.reg = STD_FUSE_OPP_VMIN_CORE_NOM, + .core.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .core.addr = 0x27, + .core.pmic = &tps659038, + + .iva.value = 1000, + .iva.efuse.reg = STD_FUSE_OPP_VMIN_IVA_NOM, + .iva.efuse.reg_bits = DRA752_EFUSE_REGBITS, + .iva.addr = 0x2f, + .iva.pmic = &tps659038, +}; + /* * Enable essential clock domains, modules and * do some additional special settings needed @@ -558,6 +590,13 @@ void hw_data_init(void) *ctrl = &dra7xx_ctrl; break; + case DRA722_ES1_0: + *prcm = &dra7xx_prcm; + *dplls_data = &dra7xx_dplls; + *omap_vcores = &dra722_volts; + *ctrl = &dra7xx_ctrl; + break; + default: printf("\n INVALID OMAP REVISION "); } @@ -580,6 +619,7 @@ void get_ioregs(const struct ctrl_ioregs **regs) break; case DRA752_ES1_0: case DRA752_ES1_1: + case DRA722_ES1_0: *regs = &ioregs_dra7xx_es1; break; diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index 93feb1623c..a8a474a88b 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -336,6 +336,9 @@ void init_omap_revision(void) case DRA752_CONTROL_ID_CODE_ES1_1: *omap_si_rev = DRA752_ES1_1; break; + case DRA722_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = DRA722_ES1_0; + break; default: *omap_si_rev = OMAP5430_SILICON_ID_INVALID; } diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c index 7292161f3c..ff08ef4247 100644 --- a/arch/arm/cpu/armv7/omap5/prcm-regs.c +++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c @@ -447,10 +447,10 @@ struct omap_sys_ctrl_regs const dra7xx_ctrl = { .control_wkup_control_spare_r = 0x4AE0C5B4, .control_wkup_control_spare_r_c0 = 0x4AE0C5B8, .control_srcomp_east_side_wkup = 0x4AE0C5BC, - .control_efuse_1 = 0x4AE0C5C0, - .control_efuse_2 = 0x4AE0C5C4, - .control_efuse_3 = 0x4AE0C5C8, - .control_efuse_4 = 0x4AE0C5CC, + .control_efuse_1 = 0x4AE0C5C8, + .control_efuse_2 = 0x4AE0C5CC, + .control_efuse_3 = 0x4AE0C5D0, + .control_efuse_4 = 0x4AE0C5D4, .control_efuse_13 = 0x4AE0C5F0, }; diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index 16a91f911a..e2ebab8262 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -229,6 +229,17 @@ const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = { .is_ma_present = 0x1 }; +/* + * DRA722 EVM EMIF1 CONFIGURATION + */ +const struct dmm_lisa_map_regs lisa_map_2G_x_2 = { + .dmm_lisa_map_0 = 0x0, + .dmm_lisa_map_1 = 0x0, + .dmm_lisa_map_2 = 0x80600100, + .dmm_lisa_map_3 = 0xFF020100, + .is_ma_present = 0x1 +}; + static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) { switch (omap_revision()) { @@ -255,6 +266,7 @@ static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) break; } break; + case DRA722_ES1_0: default: *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1; } @@ -275,8 +287,11 @@ static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs break; case DRA752_ES1_0: case DRA752_ES1_1: - default: *dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2; + break; + case DRA722_ES1_0: + default: + *dmm_lisa_regs = &lisa_map_2G_x_2; } } @@ -463,6 +478,7 @@ static void emif_get_ext_phy_ctrl_const_regs(u32 emif_nr, break; case DRA752_ES1_0: case DRA752_ES1_1: + case DRA722_ES1_0: if (emif_nr == 1) { *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1; *size = @@ -630,6 +646,7 @@ const struct read_write_regs *get_bug_regs(u32 *iterations) break; case DRA752_ES1_0: case DRA752_ES1_1: + case DRA722_ES1_0: bug_00339_regs_ptr = dra_bug_00339_regs; *iterations = sizeof(dra_bug_00339_regs)/ sizeof(dra_bug_00339_regs[0]); |
